EDK : FSL macros defined by Xilinx are wrong

[Vaughn Betz]

As others have posted, there is a Cyclone II device with an LE count close
to that of the APEX 20KE device you are using, and that's probably your best
bet. If you use Cyclone I, the 1C6 device has ~6,000 LEs, while the 1C12
has approximately 12,000 LEs, so you'll have to pick between those two.

Cyclone I and II each fit about 11% more logic than APEX 20KE per logic
cell. So the 2C8 actually has more logic capacity than the 20K200E -- the
2C8 has the equivalent of over 9,000 APEX LEs. The reason is that the
routing and multiplexers between the LUT and FF in the logic cell were
redesigned between APEX and Stratix / Cyclone, and this redesign lets us use
both the LUT and FF in a logic cell simultaneously more often than we could
in the APEX FPGAs. The net impact is fewer LEs per design, and the last
result I saw showed that we needed 11% fewer LEs in Cyclone than APEX, on
average.

In terms of speed, Cyclone and Cyclone II are much faster than APEX 20KE.
Cyclone is approximately 50% faster than APEX 20KE, and Cyclone II is
approximately 70% faster than APEX 20KE, again on average. So if you can
close timing in a 20KE, it'll be very easy (generally trivial) to close in
Cyclone. As well, if you're bringing data in at a high rate on I/Os and
widening your internal datapath so the FPGA fabric can process it at a
slower rate, the higher speed of Cyclone I/II mean you can probably run your
datapath narrower and faster. If you can do this, it saves LEs, and lets
you go down to a smaller device.

So basically Cyclone I or II is a better choice than APEX for modern
designs.

Vaughn
Altera
[v b e t z (at) altera.com]


"HamishR" <h.rawnsley@gmail.com> wrote in message
news:1126760594.019460.259480@g43g2000cwa.googlegroups.com...

If you are not using the full resources of the APEX device then you
will hopefully fit your design into a EP2C8 (8256 LEs). You should
actually get better fitting with these newer devices due to more
advanced routing. These have embedded multipliers too so if you use
multiplication you'll save a ton of space.

Hamish


htoerrin wrote:
Eithout knowing anything about your application,...

I believe that if you managed to run things in a 20KE, you will
definetly be able to run it in a CycloneII. My experience is that
CycloneII is more powerful than 20KE, although not as powerful as the
Stratix families. But as long as you don't intend to actively use the
DSP blocks, the large RAM's and lots of clocks, CycloneII will do the
job.

Havard

 

[Mike Harrison]

FOR SOLUTION-2 that
Websites to Get economical chips of SDRAM nad VRAM
Easiest way to get chips would be to strip them off a module

FOR SOLUTION-3 that
Links Where to get SSDRAM Socket....
Suggestion to do it on Single sided PCB...

Digikey stock a range of sockets. For a standard Unbuffered SDRAM, the part number is WM1712-ND

 

[Mike Harrison]

FOR SOLUTION-1 that
Websites to Get economical FPGA or Extention boards having
SDRAM Socket in it (I m using VHDl and FPGA of Xilinx (any))

This low-cost board has 32mbytes of SDRAM onboard :
http://www.xess.com/prod034.php3

 

[Tony30]

Hi,

1. I dont know of any extention boards for DDR. I also don't know of
any cheap development kits for DDR. Xilinx DDR Development ML361 cost
around $2,500 (http://www.hitechglobal.com/xilinx/ml361.htm).

2. no clue here.

3.) I think you are looking for DIMM Socket Connectors -
http://www.mouser.com/index.cfm?handler=displayproduct&lstdispproductid=633171&e_categoryid=619&e_pcodeid=82902


I think #3 would be very hard. If you have time and lots money I would
do this (in fact I am for my Masters Project, but I am doing DDR2 with
this board - http://www.hitechglobal.com/ted/virtex4ddr.htm). Building
your own board is hard, requires board design skills, more importantly
board design software.

My best advice is go with number 1. Much easier.

Good luck. I wish you the best.


-Tony

 

[Falk Brunner]

"they call me frenchy" <solarfrenchyNO@SPAMhouseofharmonystudios.com>
schrieb im Newsbeitrag

Right, but my question (as elementary as it may be) was whether PDM
would work for such an application or whether PWM is preferred for any
particular reason. Both of them seem to acheive the same thing in
different ways assuming the frequency is adequately high.

For LEDs, PWM is just as good as PDM. PDM has the advantage that you can use
lower clock frequencies, but this is not a real advantage.

Regards
Falk

 

[dlharmon]

On 2005-09-16, Mike Harrison <mike@whitewing.co.uk> wrote:

FOR SOLUTION-2 that
Websites to Get economical chips of SDRAM nad VRAM
Easiest way to get chips would be to strip them off a module

FOR SOLUTION-3 that
Links Where to get SSDRAM Socket....
Suggestion to do it on Single sided PCB...

Digikey stock a range of sockets. For a standard Unbuffered SDRAM, the part number is WM1712-ND

Digikey stocks Micron now. No need to strip chips off a module.

Darrell Harmon
http://dlharmon.com/dspcard

 

[JJ]

Telenochek wrote:

Hi!
I was wondering if anyone has any recommendations for software that is
designed for drawing architectural level diagrams or block diagrams for
hardware design.
(lets say a microprogrammed pipelined processor).
Currently I am using Microsoft Visio 2003, and its okay, but it never
hurts to try and find something better (if you know what I mean)

Also does anyone know what software tools are used to draw the timing
diagrams in various datasheets?

Any help will be highly appreciated!
Thank you!

Yes

I spent several months preparing a paper (on a pipelined processor) and
docs trying to use relatively free software Windows like Open Office
but the graphics really just were awefull.


I remembered how much fun I had on the old Mac 20yrs ago with MacDraw
so I dug up Canvas by deneba who also did a Windows version starting
around early 90s.

Basically its a CAD program as easy to use as the old MacDraw but much
more powerful, it doesn't do the links thing like Visio or OO but after
using OO version of that I got sick of that feature in a hurry.

In canvas when you need to make up arrays it figures how to auto step &
repeat, many Win programs copy right on top of same, what good is that.

It allows hierarchy grouping ungrouping etc.

Its stipple pattern choices are very dated though right out of MacPaint
1 1984.

You can control your grid and resolutions.

Its follows good interface design and installs by just dragging (old
version).

It starts in <<1s while OO,Acrobat_reader starts in 10-20secs.

Overall I found I could do all my schematic and other drawings in a
half hour instead of hitting the wall. Downside of course these
schematics are for artwork only, not machine readable. Works well with
OO etc and the final PDFs looks good.

They are still around but seem to have moved on to high end drawing.

From the web its looks familiar but the price is much higher (about
same as Visio). It started out life as a $50 desk accessory.

You can probably find quite a few Windows native CAD programs (some
even free) but I always find they get the whole user experience wrong
in some terrible way, I have tried way too many and forget them.

regards

johnjakson at usa dot_com...

PS if you want to see what my graphics look like, drop a note, may take
a week though.

 

[Telenochek]

Unless there is a paying audience for a design review,
I just use a pen and notebook to block things out
then get on with the design and simulation work.

Yes I did a lot of that.
I am trying to get away from it as much as possible, paying audience or
not.
If you do the diagram on a computer, its already documented.
Then its easy to change the design, keep track of versions,
copy one block to another design, reuse your blocks.
Major time saver even with a moderately user-friendly program.

Most synthesis tools can draw block diagrams for
you once the top entities/modules are complete.

Yes, but the idea is to have a block diagram before touching
VHDL/Verilog.

Thanks for the TimingDesigner link!
(No, I am not actually designing a datasheet, I am designing
multithreaded process)

 

[Brad Smallridge]

Hmm. Sounds a bit complicated.

I was thinking of starting without the OPB because there seems to be
a learning curve there. I take it that there is already a Cypress program
that communicates to the OPB and PowerPC. If I want to communicate
directly to the Xilinx fabric, is there an example program to do this, and
does it fit into the Keil compiler linked-4K-byte free evalutation? It
seems to me that if you could get a report out of a chosen BRAM you
could look inside the chip somewhat like ChipScope. Although ChipScope
is another tool that I don't have.

Since your original request was to use the USB interface to write a
register element in the design. You could take the USB-to-LCD design
that I mentioned before, open the project in EDK, remove the OPB LCD
peripheral and replace it with a bare bones OPB IPIF peripheral and
tie the write and read buses to your register, modify the software to
write the USB data new memory location, resynthesize, place and route
and try it out on the ML403.

Ed

 

[Steven J. Hill]

Jock wrote:

We have an MCS_86 output file for an Xilinx 4000 series device. However, all
the design files are missing and we need to modify it.

Is there any software available that would allow me to reverse engineer the
output file?

No. It is a bit stream and there is not way to reverse engineer back to

the original design.

-Steve

 

[Hahnsolo]

In order to program the V4 I would have to use the jtag cable? Also
what is "serial data flash"? an add on?

Thanks

 

[Adrian Knoth]

Ram <r_fpga_dev@yahoo.com> wrote:

Just wondering, is it normal for the installer to finish and not add any
icons or anything?

Under Unix? Sure, you cannot know the user's desktop environment.

Perhaps there are some recommendations in the FHS (or LSB), but
I wouldn't currently rely on it.


--
mail: adi@thur.de http://adi.thur.de PGP: v2-key via keyserver

Lieber Gras rauchen als Grass lesen (gesprochen kommt das besser)

 

[Mike Treseler]

pinkotronic wrote:

But I don't really understand what "Thold" mean.. and i'm not sure my
solution is to increase it..

Consider a synchronous design.

--Mike Treseler

 

[Peter Alfke]

Tutorial explanation:
In order to capture data reliably, the D input of each flip-flop must
be valid at least a SET-UP TIME before the active clock edge, and must
be stable until a HOLD-TIME after the active clock edge.
Modern flip-flops never have a positive hold time, and a synchronous
design will have no hold-time issues. But long clock delay differences
can cause the input to change well before the clock edge. Then you can
have a race condition. Unreliable at any clock rate!
Design synchronously, and always use low-skew global clock
distribution!
Peter Alfke, Xilinx
===============
Mike Treseler wrote:

pinkotronic wrote:

But I don't really understand what "Thold" mean.. and i'm not sure my
solution is to increase it..

Consider a synchronous design.

--Mike Treseler

 

[Austin Franklin]

I found "equivalent_register_removal", but so far, that hasn't worked
either...but that seems to be the right attribute, now I just have to get it
to work...as register_duplication is apparently not the right attribute.

"Austin Franklin" <austin@darkr00m.com> wrote in message
news:EIZXe.347$X6.321@fe05.lga...

Hi,

What is the XST equivelent of Synplify's "synthesis syn_preserve = 1" (for
Verilog)? I've tried using "
synthesis attribute register_duplication xx "yes" " (closest thing I found
so far that may be what I'm looking for) with xx equal to the module name,
the module instance, the signal...nothing seems to work. I have register
dulpication selected in the properties for "implement design"...

Any help appreciated.

Austin

 

[Stephane]

nice job!

You're referenced from the Mediatronix web site, but not from
http://www.xilinx.com/ipcenter/processor_central/picoblaze/picoblaze_user_resources.htm

You did not updated the "Last Changed" date at the bottom of your page
since V0.3.

M6 wrote:

I've created an IDE for the picoblaze-3 microcontroller (Xilinx TM).
The IDE is an open-source project (GPL-license) and works under the
Linux operating system.

The IDE supports the following:
- Editor with syntax highlighting,
- Assemble and export to: HEX, VHDL or MEM files,
- Simulate the source code and see/modify the scratchpad, registers and
I/O ports.

For those who are interested, checkout: http://www.xs4all.nl/~marksix

Regards,

Mark Six

 

[Alex Freed]

CMOS wrote:

hi all,
anyone know how to use digilent USB2 module in B1 connector of the
spartan3 starter kit?

CMOS

Cut the trace from pin 6 on the USB board or it will hold PROG-B in the
wrong state. Now you can use USB for fast i/o, but some other means to
load the bitstream: JTAG only works in A1.

 

[hetfield]

Thanks for your answer, but I want to count the "1" bits during only
one or two clock cycles.
I use 10 MHz clock in my system for synchronization.
And the input bit stream is about 150 bits long.
Moreover, input bit stream changes on every clock rising edges.
That why I cannot apply simple counter on this problem.

 

[John_H]

hetfield wrote:

Thanks for your answer, but I want to count the "1" bits during only
one or two clock cycles.
I use 10 MHz clock in my system for synchronization.
And the input bit stream is about 150 bits long.
Moreover, input bit stream changes on every clock rising edges.
That why I cannot apply simple counter on this problem.

So 1) how fast is the clock for your input bit stream and 2) why wait
100 ns before starting to count?

 

[Austin Franklin]

Hi,

I figured out how to get it to work. There is a flag in the synthesis
options to enable/disable this...that seemes to work, but obviously
globally.

To get it to work on individual registers, instead of globally, the
directive seems like it has to be after the reg statement. I'm not sure why
as the documentation shows that you have to name the register specifically
in the directive...except that perhaps it's a single pass compiler. I had
the directive just above the reg statement...and it complained it couldn't
find the reg. Putting it on the same line worked.

Austin


"Austin Franklin" <austin@darkr00m.com> wrote in message
news:Y1%Xe.409$X6.170@fe05.lga...

I found "equivalent_register_removal", but so far, that hasn't worked
either...but that seems to be the right attribute, now I just have to get
it
to work...as register_duplication is apparently not the right attribute.

"Austin Franklin" <austin@darkr00m.com> wrote in message
news:EIZXe.347$X6.321@fe05.lga...
Hi,

What is the XST equivelent of Synplify's "synthesis syn_preserve = 1"
(for
Verilog)? I've tried using "
synthesis attribute register_duplication xx "yes" " (closest thing I
found
so far that may be what I'm looking for) with xx equal to the module
name,
the module instance, the signal...nothing seems to work. I have
register
dulpication selected in the properties for "implement design"...

Any help appreciated.

Austin