EDK : FSL macros defined by Xilinx are wrong

[Duane Clark]

Brian C. Van Essen wrote:

I am attempting to simulate a very basic system built with Xilinx EDK
7.1.02i, using VHDL. After generating the ModelSim specific compiler
scripts, I can execute a do system.do, which works okay, but when I
execute the vsim system command I get the following results. I have
had similar problems when trying to do a Verilog/VHDL mixed simulation
system. Looking around on the Xilinx web site, I see that someone else
has had a similar problem
(http://toolbox.xilinx.com/cgi-bin/forum?50@233.ec6BaE6ihO8.4@.ee8f9bc),
but I did not see any responses or suggestions.

Any help would be appreciated.

Thanks,
Brian

-------------

ModelSim> vsim system_conf system
# vsim system_conf system
...
Loading c:\Modeltech_6.1a\win32/../ieee.vital_primitives(body)
# Loading Z:/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.vpkg(body)
# ** Warning: (vsim-3479) Time unit 'ps' is less than the simulator
resolution (1ns).
# Time: 0 ns Iteration: 0 Region:
/system/microblaze_0/microblaze_0/decode_i/prefetch_buffer_i/using_fpga/prefetch_buffers__0/srl16e_i
#

Have you tried running with the simulation resolution set to 'ps'? That
would normally be done in the modelsim.ini file or the project.mpf file,
by changing the "Resolution" line.

** Fatal: INTERNAL ERROR in reset_trigger_process().
# Time: 0 ns Iteration: 0 Process:
/system/mb_opb/mb_opb/opb_arbiter_i/opb_arbiter_core_i/multi_master_gen/park_lock_i/grant_gen__1/reggrnt_gen/reggrnt_process
File:
C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_e/hdl/vhdl/park_lock_logic.vhd
#

FATAL ERROR while loading design
# Error loading design

These kinds of problems can be difficult to debug in Modelsim. I try to
narrow down the problem by trying to load individual pieces of the
project. That is, when you get the "Load Design" dialog, pick an entity
for just a portion of the design. You are not going to simulate the
pieces of the design, because all you care about for this testing is
whether they will simply load.

For example, pick the entity that is in park_lock_logic.vhd. If that
loads, then the problem is elsewhere. If not, the problem is either that
entity or one of the entities contained within it. It is a bit of a
trial and error method, but I have always been able to find the problem
file with this method.

 

[Ray Andraka]

Bubba wrote:

Multiplier



Is there a good algorithm (small) to multiply two 36 bit “signed” numbers to
get a 72 bit result.




The mult18x18s are signed multipliers, there is no option to make them

unsigned. You can use them as unsigned 17x17 by forcing the MSB to '0'.
In order to build a larger multiplier out of smaller ones, you must
treat only the most significant 'digit' (where the input to each smaller
multiplier represents a digit) as signed, all the lower order digits
must be unsigned. Hence, with the Xilinx multipliers, splitting your
input into two words will get you up to a 35x35 multiplier. If you
attempt 36x36, you will need a third multiplier in each dimension, which
means 9 multipliers. You can create 1x35, 35x1 and 1x1 unsigned
multipliers in the fabric to complete your multiplication to avoid using
up multiplier blocks.


--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Luc]

If you could live with an external PPC, Lattice and Altera have both a
FPGA fabric with Serdes on it.
Altera: Startix GX
Lattice: ORTx2G5 (Ethernet), ORSOx2G5 (SONET) where x stands for 4 or
8 (# of channels) delivering up to 3.7Gbps Serdes channels with
excellent Jitter specs

One suggestion: get away from the on board processor. It kills your
SerDes performance.

Luc

On Tue, 30 Aug 2005 10:53:21 GMT, "blah" <blah@blah.ca> wrote:

Does anyone know of another FPGA (other than Virtex series from Xilinx) that
has an embedded processor comparable to the PowerPC 405 as well as 3Gbps
Serdes?

 

[Ed McGettigan]

Eric wrote:

"...Altera continues to sell Excalibur devices, this product family is
not recommended for new designs. Designs requiring embedded processors
should consider Altera's NiosŽ II processor.

Excalibur devices integrate a 200-MHz processor with the APEX™ 20KE
FPGA architecture, balancing the price, performance, and system
integration requirements of system-on-a-programmable-chip (SOPC)
designs."

Not sure if this is just research or product development, but you could
still get Excalibur devices.
Eric

You can probably still get the Altera EPXA1, EPXA4 or EPXA10 devices, but
they have been mostly erradicated from the Altera web site and they don't
want you to use them as you noted above.

http://www.altera.com/products/devices/arm/arm-index.html

Also, these devices don't include a high speed transceiver as the OP wanted.

Ed

 

[Larry Doolittle]

On 2005-08-30, Hw <localhost@com.com> wrote:

I have trouble finding an 8-input+ ADC, 8-bit resolution+, 1
Msamples/sec that doesn't cost an arm and a leg.

A new design I am working on will need an FPGA anyway, so I wanted to
suck the ADC+uC functionality into the FPGA (probably Xilinx) if
possible.

You will have trouble competing on cost and performance with e.g.,
LTC2236, 10-bit 25 MS/s for $4.67 in singles. All you need to add
is an external 8:1 multiplexer like a MAX4312 ($4.45).

That ADC part has a 6-cycle latency, at 25 MS/s that's only 240 ns.
You could stop it down to 8 MS/s (to lower power dissipation)
and still hit your 1 us latency and throughput goals. Depends
on what clocks you have available.

- Larry

 

[Brian C. Van Essen]

On 2005-08-30 11:18:29 -0700, Mike Treseler <mike_treseler@comcast.net> said:

Brian C. Van Essen wrote:
I am attempting to simulate a very basic system built with Xilinx EDK
ModelSim> vsim system_conf system

** Fatal: INTERNAL ERROR in reset_trigger_process().
# Time: 0 ns Iteration: 0 Process:
/system/mb_opb/mb_opb/opb_arbiter_i/opb_arbiter_core_i/multi_master_gen/park_lock_i/grant_gen__1/reggrnt_gen/reggrnt_process
File:
C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_e/hdl/vhdl/park_lock_logic.vhd
#
FATAL ERROR while loading design
# Error loading design

Bring up park_lock_logic.vhd
and find reset_trigger_process
Check the declarations of all
array indexes used there.

I fixed a similar problem by changing
an array index type from integer to natural.


-- Mike Treseler

Well, I have tried to find the reset_trigger_process in all of the

libraries vhdl files, but was unable to. I am guessing that it is part
of a library like unisim (which is commented to be a Xilinx library).
If that is the case, then I am not sure how to correct it if the
library is already compiled. Does anyone else have a working
environment with these settings.

It is important to note that this error does not appear when using a
system that only has a PowerPC. Thus, it seems isolated to a component
required by the Microblaze.

Again, any more feedback would be wonderful.

-- Brian Van Essen

 

[Aurelian Lazarut]

yijun_lily@yahoo.com wrote:

Hello,

I want to implemented a gated clock signal that is active for only a
certain period. What is the best way?

I did it like this (I know that is bad)


then don't (if you know is bad)

leave the clock to run and use CE (chip enable) driven by your counter
to mask the unwanted clock cycles
Aurash

wire clock_coding;
assign clock_coding = (counter > 5 && counter < 120)?clock:1'b0;

Thanks,

--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/

phone: 353 01 4032639
fax: 353 01 4640324

 

[Jan Panteltje]

On a sunny day (Wed, 31 Aug 2005 01:10:30 +0200) it happened "Pierre de Vos"
<pierre.devos@webmail.co.za> wrote in <df2p1d$7bj$1@ctb-nnrp2.saix.net>:

If you have real _images_ to display then you need some image
compression, that's quite harder and there is no guarantee that the
image you'll need to store will be compressible into what space you have.


Sylvain


It's a B/W LCD 1 bit per pixel and basically I display line graphics using
an in memory frame buffer and blasting the buffer to the LCD from the CPU.

Pierre
run length encoding?

 

[AdamS]

I'm not very fammiliar with the USB protocol, but I think It's an
impossible mission.

 

[Gabor]

yijun_lily@yahoo.com wrote:

Hello,

I want to implemented a gated clock signal that is active for only a
certain period. What is the best way?

I did it like this (I know that is bad)

wire clock_coding;
assign clock_coding = (counter > 5 && counter < 120)?clock:1'b0;

Thanks,

This isn't necessarily bad. It's O.K. to gate clocks when they
are slow enough to avoid setup or hold issues. The code you wrote
would work O.K. if counter increments on negedge clock so you won't
glitch when the count changes.

In ASIC's you can save power by gating clocks, but in an FPGA
you're probably better off using a clock enable, because the
clock global routing is already there and flip-flops all come with
enable inputs whether you use them or not.

Regards,
Gabor

 

[Gabor]

Marco wrote:

Hallo,
have connected an external signal to my spartan 3. When the external
peripheral goes into power down mode, the signal goes into Hi-Z state.

I have made a process sensitive to the external signal.

if (ext_signal = 'Z') then
...

Using this syntax the fpga doesn't "see" the high impdance state and
considerthe signal 0 or 1.

What could I do?

Many Thanks
Marco

This depends on the normal state of the signal when the peripheral
is powered on. For example if it is usually high, you could add
a pulldown to the pin and watch for it to go low when the peripheral
powers down. If the signal is usually switching, you could add
some logic to count time since the last transition and indicate
that the signal is inactive if it hasn't changed in some time-out
period. You should still place a pullup or pulldown on the I/O
to prevent unwanted toggling from noise.

If you have several pins connected to the peripheral, you could pull
them all down and look for all pins zero. This reduces the chance of
mistakenly detecting a powered down peripheral (assuming all pins
low is not a typical state of the interface).

 

[Philip Freidin]

On Wed, 31 Aug 2005 07:19:41 -0700, dima2882 <vadimv@ieee.org> wrote:

Hi all

I want to use FPGAs in 100 or 144 pin quad flat-pack (QFP) packaging.
I really want to be able to socket these somehow. Ideally, I want to
have a ZIF socket that is soldered to the circuit board, and can hold
the chip without any soldering, by pressure alone. Also, I am hoping
for the socket to have a lever such that the chip can be
inserted/extracted with no force. This operation would hopefully
resemble DIP ZIF sockets. Does anyone know where these can be
obtained for >$70?

Thanks a lot!

Don't know about the price ( I bet you really meant "<" ) but this
is the company that makes these sockets:

http://www.yamaichi.com/

Look at Series IC149 and IC51



Philip

 

[Bob Perlman]

Hi -

On 31 Aug 2005 06:35:48 -0700, "Gabor" <gabor@alacron.com> wrote:

yijun_lily@yahoo.com wrote:
Hello,

I want to implemented a gated clock signal that is active for only a
certain period. What is the best way?

I did it like this (I know that is bad)

wire clock_coding;
assign clock_coding = (counter > 5 && counter < 120)?clock:1'b0;

Thanks,

This isn't necessarily bad. It's O.K. to gate clocks when they
are slow enough to avoid setup or hold issues.

If you're clocking everything with a single clock edge, hold time
violations are not a function of clock speed; there is no "slow
enough."

Bob Perlman
Cambrian Design Works

 

[Mike Treseler]

Brian C. Van Essen wrote:

Well, I have tried to find the reset_trigger_process in all of the
libraries vhdl files, but was unable to.

Was there source code at:
C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_e/hdl/vhdl/park_lock_logic.vhd
?

I am guessing that it is part
of a library like unisim (which is commented to be a Xilinx library).
If that is the case, then I am not sure how to correct it if the library
is already compiled.

If you don't have the source, you
can't debug it, only the owner can:
http://www.xilinx.com/support/techsup/tappinfo.htm

Or if you have a Mentor Modelsim license
open a case with them.

Again, any more feedback would be wonderful.

If you need IP by others, buy the source code.


-- Mike Treseler

 

[Brad Smallridge]

Z is for data bus drivers. I don't think
you can use it at an input and have it make any sense.

You should probably pull down or pull up your input
pins in PACE. I don't know if there is a way to sense
that the device has outputed Zs and therefore has gone
into powerdown.

Brad Smallridge
b r a d @ a i v i s i o n . c o m

 

[Marco]

"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message
news:11hbuit7s8ddf1c@corp.supernews.com...

Z is for data bus drivers. I don't think
you can use it at an input and have it make any sense.

You should probably pull down or pull up your input
pins in PACE. I don't know if there is a way to sense
that the device has outputed Zs and therefore has gone
into powerdown.

Brad Smallridge
b r a d @ a i v i s i o n . c o m

I have seen I can chhose pull up or pull down into PACE, but could you
explain what does it means pull up, or pull down, please?

Thanks
Marco

 

[Andy Peters]

Marco wrote:

Hallo,
have connected an external signal to my spartan 3. When the external
peripheral goes into power down mode, the signal goes into Hi-Z state.

I have made a process sensitive to the external signal.

if (ext_signal = 'Z') then
...

Using this syntax the fpga doesn't "see" the high impdance state and
considerthe signal 0 or 1.

What could I do?

I'd be very surprised if the synthesis tool (I presume XST?) didn't
complain or error out on that (ext_signal = 'Z') comparison. There's
no way for the FPGA logic to detect that a signal is undriven, which is
what happens when a driver is tristated.

About all you can do is to figure out some way for your peripheral to
signal that it's powered up. I don't know the details of your
peripheral, so that's something you'll have to figure out.

-a

 

[Mike Harrison]

On Wed, 31 Aug 2005 23:49:24 -0500, Andrew Dyer <amdyer@gmail.com> wrote:

On Wed, 31 Aug 2005 19:04:24 +0000, Mike Harrison wrote:

Does anyone know how feasible it is to drive a TFT panel LVDS interface (sometimes called Panel-link
I think) direct from the S3 I/Os ? If so, what sort of frequency can you get up to - I saw a mention
recently about using the DDR registers to reduce the data rate but couldn't immediately see any
Xilinx appnotes when I had a quick look.

Also, as the IO banks on the lower-end dev boards tend to be tied to +3.3v, but LVDS needs 2.5v,
what happens if you lie to the software about the supply - will it work to any useful degree
(interested in lvds output only)?

Funny you should mention this - I am working on exactly this at
work right now.

It's not working right now, but the basics are in place. clock
runs and I see data coming out of the fpga, but I think I might
be shifting bits in the wrong place. Panel stuff is annoying in
that the data streams are organized in 7-bit chunks which means
you have to do some trickery to do shifting via the DDR registers.

What frequency/display format are you aiming for ?

The DDR trick is nice, otherwise you end up doing a fair bit
of monkeying with RLOC attributes if you want to run an s3 -4
speed grade part at 200+ Mhz.

Our board has a selectable 2.5V/3.3V bank for doing either LVTTL
or LVDS panel stuff.

I assume you know about the TTL to LVDS chips made for this from
National and others?

Yes - I bought a couple to play with after messing with a ttl (parallel) style interface, but I was
wondering how possible it would be without..

 

[Mike Harrison]

On Thu, 01 Sep 2005 00:32:32 +0200, Sylvain Munaut <com.246tNt@tnt> wrote:

Mike Harrison wrote:
Does anyone know how feasible it is to drive a TFT panel LVDS interface (sometimes called Panel-link
I think) direct from the S3 I/Os ? If so, what sort of frequency can you get up to - I saw a mention
recently about using the DDR registers to reduce the data rate but couldn't immediately see any
Xilinx appnotes when I had a quick look.

Look at
http://www.xilinx.com/bvdocs/appnotes/xapp298.pdf

It's not for TFT panels but for their TX side, they serialize 10 bits by
using a 5x clock and DDR flips flops with a differential output.


Also, as the IO banks on the lower-end dev boards tend to be tied to +3.3v, but LVDS needs 2.5v,
what happens if you lie to the software about the supply - will it work to any useful degree
(interested in lvds output only)?

Well, on lower end board, the trace might not be routed as differential
anyway. The Avnet spartan 3 board (the PCI one) I have has 4 LVDS pairs
connected on 2.5v rail.

That's definitly something I'd like to do. I might try it soon with an
old laptop scree if I find the doc for it.

TFT panel docs are a bit scarce but from what I've seen, they are all very similar to each other
within any given resolution. If you have the whole laptop lid, you will have the cable/flexi which
will help identify the connections.
Here are some links to tft pinouts and data I found a while ago. Most concern ttl-style panels but
even the LVDS ones are based on this, so give a starting point for experimenting with timings etc.
Some LVDS panels have an identifiable LVDS-to-TTL converter chip, so the pinouts can be derived by
beeping out the pins.

http://www.optrex.com/products/groupdetail.asp?g=TFT&s=12.1
http://www.linux-hacker.net/cgi-bin/UltraBoard/UltraBoard.pl?Action=ShowPost&Board=verytech&Post=152&Idle=0&Sort=0&Order=Descend&Page=0&Session=
http://support.advantech.com.tw/Cservice/LCD.nsf/f99b88c84af1eeff482565ec000759ea?OpenView&Start=1&Count=30&Expand=17.1#17.1

 

[Ben Jones]

Hi Martin,

I am using the Xilinx ISE 7.1 with ModelSim 6.0a and I have a problem
when I use the "Perform Timing-Driven Packing and Placement" option for
the mapping process.
snip

No, it is most likely not your error. There are known problems with the
DSP48 register-balancing feature of the mapper. Set the variable
XIL_MAP_NO_DSP_AUTOREG in your environment and your problem will most likely
disappear.

You may find that upgrading to the latest service pack will also fix it, but
unfortunately this is far from certain I'm afraid. If you can submit your
design (or part of it) to Xilinx for analysis, that would be really great.
The Map team are keen to get to the bottom of these problems.

Sorry for the inconvenience...

Cheers,

-Ben-