EDK : FSL macros defined by Xilinx are wrong

Jim Granville skrev:

Mak wrote:
Hello all,

I am interested in designing a custom board with serial interface and I
am searching for RS232 port driver ICs which can support baud rates
higher than 230kbps.

There are many PCI or USB to serial interface options available which
support bauds of upto 920kbps. I have designed a UART interface in FPGA
but need higher baud rate driver ics to actaully get the performance I
require.

Any recommendations?

I think you are asking about the level translators ?
You have tried the usual suspects at Maxim and Linear ?
You might also want a 3.3V supply interface device.

http://www.maxim-ic.com/Interface.cfm
shows 150 devices under "RS-232 Line Driver/Receivers"

-jg

If you follow the rs-232 spec you can't go above ~115.2Kbit, to go
above that you need a level translator that supports higher speeds,
usually
with an extra pin that enables a higher slew rate

-Lasse

 

[zoinks@mytrashmail.com]

I installed the EDK and ISE service packs. I still get the same error,
even after re-creating the system from scratch

to use the XUP board I simply d/l-ed and copied the XUPv2P pack to a
dir and specified that during the BSB. Did I forget to do something?

With the peripheral list I mean the list that is shown at the end of
the BSB. In particular the drop-down list you see when you are to
select in which memory peripheral the test-software should be loaded.

All the weird behaviour only occurs when I choose to use external DDR
memory.

I'll post the project when I have access to it.

 

[Sebastian Schmidt]

Hi.

I read the memory over the JTAG interface with the In-System Memory
Content Editor.

Sebastian.

Am 05.09.2005, 17:30 Uhr, schrieb <ALuPin@web.de>:

How do you read and write the memory?In simulation ?
Or in real hardware (How did you debug that) ?

Rgds
André


Sebastian Schmidt schrieb:

Hi.

I have a problem with the In-System Memory Editor in Quarts II 4.1.
I can read the memory contents and get the correct values when I do
not write the memory before.
But when I write any values (including the old memory contents) to
the memory and read thereafter, I get false values.
This only happens when using ram, when using the memory editor on
LPM_CONSTANT, I always read the correct values.
I verified that no logic of my design is responsible for that, by
creating a memory from the MegaWizard Plugin Manager and setting the
memory as the top level module, thus no other logic is there besides
the memory.

Can anybody help?

Sebastian Schmidt.

--
Erstellt mit Operas revolutionärem E-Mail-Modul: http://www.opera.com/mail/

 

[Symon]

Hi Ulises,
I looked at this briefly a while ago. My initial impression of reading the
datasheet is that if the cache is turned on, the accesses are in 8-word
chunks, i.e. 32 bytes at a time. In this case the mask pins aren't needed.
Quote "The PPC405x3 implements separate instruction-cache and data-cache
arrays. Each is 16 KB in size, is two-way set-associative, and operates
using 8 word (32 byte) cache lines. The caches are non-blocking, allowing
the PPC405x3 to overlap instruction execution with reads over the PLB (when
cache misses occur)."
I haven't tried this yet, so, like you Ulises, I'd appreciate it if someone
else can confirm this mode of operation is valid.
Thanks, Syms
"I. Ulises Hernandez" <delete@e-vhdl.com> wrote in message
news:dfhobc$6in$1@nwrdmz02.dmz.ncs.ea.ibs-infra.bt.com...

Hello everybody,

Hopefully someone can give me a hand with a PPC405 issue...

How do you configure the PPC so that it only performs 32-bit aligned
accesses to DDR? The DDR2 module I am interfacing is byte wide and I do
NOT have access to the Data Mask pins, a DDR Word becomes 8 (bits/byte) x
4 (Burst Length) = 32 bits wide...

Thanks in advance,

--
Ulises Hernandez
" I'm not normally a praying man, but if you're up there, please save me,
Superman!" - Homer Simpson ;O)

 

[Andrew FPGA]

If you are using modelsim search their documentation for signal_spy.

ALuPin@web.de wrote:

One possibility could be to route the internal signal
to an output pin.

Rgds
André

 

[huangjie]

Hi Austin , Is Xilinx doing more work on this ?
Hi All !
I did a simulation use HyperLynx. Below is the circuit:

PCI-Driver -------- 15 nH Inductor -------7.6cm,88.5ohms,447ps
transmission line ----
---PCI Receiver ------- 7.6cm,88.5ohms,447ps transmission line ---PCI
Receiver.

PCI receiver use xc2s200-pq208 PCI33M 5V
I think voltage across the Inductor is crossed by ground bounce .
Result:
When PCI-Driver use xc3s200-pq208 PCI33-3, the max voltage is 490mV.
When PCI-Driver use xc2s200-pq208 PCI33M5V, the max voltage is 370mV.
Question:
This result accords with spartan3-SSO guidelines ( SSO number is 1
for PQ208 ), but
not accords with spartan2(SSO number is 4 for PQ208). And my
xc2s200-pq208 board
works well .
Why ?

 

[dfx]

When we worked with one of our leading networking clients last year,
they identified Xilinx WASSO (weighted avg SSO) calcs as being
"necessary but not sufficient" for project success, and asked us to do
something about making it easier to calculate. After our client runs
WASSO, they still do a *detailed* SI analysis - but will not invest the
time doing so until the WASSO numbers are OK. They even "derate" the
passing WASSO levels further. While this may be extra-conservative,
their revenues and margins indicate they are doing a lot right

We have since integrated WASSO calculations into the latest release of
DesignF/X Pin Assignment (DPA), with lots of inputs from users and
Xilinx FAEs, on a number of other features as well. (Disclosure: DPA is
available only for Xilinx FPGAs at this time, and our company is a
Xilinx EDA Alliance Partner.)

Of interest to this group and this thread in particular is that DPA is
free to use for under 600 pins, WASSO setup is easy, and calculations
are updated as pin assignment progresses, along with IO standard
assignment, etc. You can download DPA from our website at
http://www.prodacc.com

Good luck in all your projects!

Manu Pillai

 

[I. Ulises Hernandez]

Thanks for your replies...

See below for my comments.

"Kolja Sulimma" <news@sulimma.de> wrote in message
news:431c93f2$0$24158$9b4e6d93@newsread4.arcor-online.net...

Symon wrote:
Hi,
Hmm, that's a shame, It'd be nice to save the I/Os I'd need for byte
masking.

Exactly what we thought ;O)

Did you put the cache into "write back" mode?

I am not sure if that is the case, I'll double check! I am not a software
expert... just trying to speed up things in this project giving a hand to
the softies. I am actually the guy who wrote the HDL for the PPC system on
this card and part of it is the PLB_DDR2 controller.

Hopefully someone with more experience will help us out when they get
back
from their labor day holiday! Also, I should ask my FAE I suppose!
Cheers, Syms.

If it happens rarely you can create a bus error and trap it to a service
routine that berforms a 32-bit wide read-modify-write transaction to do
the byte write.

Ok, I see what you mean... the plan is to use Montavista Linux on the card
and I am not sure how easy would be to add such service. I'll check with the
software guys.

Of course you can as well add hardware that does this to the memory
controller.

32-bit wide read-modify-write transaction to do byte writes... that is going
to be the solution for the meantime, messy PLB_DDR2 controller but, it will
get us further.

Also, make sure that the compiler knows that the memory region is
cachable. In an embedded world it could be that all addresses default to
address space with side effects. In that case the compiler has no choice
but to perform access to data of type byte as individual byte accesses.

I have checked that and it is cacheable...

Regards,
U. Hernandez

Kolja Sulimma

 

The wren port is set to 0, so that no writes occur out of the logic.

But you said in your post before that you write to the memory?

But when I write any values (including the old memory contents) to
the memory and read thereafter

 

[gallen]

Let me be more specific than Marko was.

<= is a non-blocking assign. It is typically used for sequential
blocks of code. That means any block of code that has an edge
sensitive element in the sensitivity list:

always @ (posedge clk)
q <= d;

The above example is how non-blocking assigns would typically be used.

= is a blocking assign and it is used everywhere else. That is it is
used in initial blocks, assign statements, parameter assignments,
defparam statements and (typically) combinational always blocks:

reg combout;

always @ (stuff or things)
begin
combout = 0;
if(stuff)
combout = 1;
if(things)
combout = 0;
end

Statements such as above can be written using blocking (=) assign.
Basically, you can write code as a c programmer would. combout takes a
value of zero, then if stuff is set combout gets set to 1, but if then
things is set, combout is set back to zero. Dispite the sequential
nature of this, it is important to remember that this happens in zero
time. When this gets synthesized it will be turned into a
combinational block that has the following truth table:
s = stuff
t = things
c = combout
s t c
0 0 0
0 1 0
1 0 1
1 1 0

I hope that clears things up a bit.

-Arlen

 

[Newman]

After reviewing the LogiCore Multiplier Generator v7.0, it looks like I
can just specify a smaller width for the Output Option. Any other
suggestions are welcomed.

-Newman

Newman wrote:

Hi,
I am getting ready to clean up some XST(Verilog) warnings, and want
to open a discussion on how to eliminate/suppress unused bits coming
from instantiated modules. (e.g. WARNING:Xst:646 - Signal <temp<11:0
is assigned but never used.
To further clarify, say that temp is actually a [35:0] wire that
connects to the output of a coregen 18x18 multiplier, but the lower 12
bits are intentionally not used. Does anybody have any Verilog type
suggestions on how to eliminate the warning. I looked at ISE's 7.1
message filtering, but was wondering about reasonable alternatives?

- Newman

 

[Gabor]

Jeff Cunningham wrote:

Signals defined in a VHDL package can be global in scope.
-Jeff

In Verilog it's even easier. You can specify any signal
using the module hierarchy and "." as a separator like:

top.instance1.signame

 

[Brad Smallridge]

Make sure JP1 is jumpered. Upper Right Corner.

 

[Al Clark]

"Luis Cupido" <cupidoREMOVE@REMOVEua.pt> wrote in
news:newscache$0vhemi$3um$1@newsfront4.netvisao.pt:

Hi,

I've been using the 25P10 flash to configure cyclone devices,
as far as I can see they are exactly equal to the EPCS1
(even silicon ID is the same, I suspect it is the same chip inside)

All altera devices (in AS) I tested can read it and configure fine,
however the Quartus II fail to load data into the 25P10...
(I must use another software to load the 25p10 and that is less
convenient)

Does anybody knows why... what is the trick used ?

Luis C.

This is very interesting since the configuration roms are expensive
compared to typical SPI flash. I noticed that Lattice is pushing the fact
that they can configure using cheap standard SPI flash.

Do you use the 25p10 A version. Have you tried SST parts?


--
Al Clark
Danville Signal Processing, Inc.
--------------------------------------------------------------------
Purveyors of Fine DSP Hardware and other Cool Stuff
Available at http://www.danvillesignal.com

 

[Sylvain Munaut]

Amit Kasat wrote:

Sylvain Munaut wrote:

Hi,

I need to define some environment variable to
change the behavior of the synthesis tool in order
for my design to compile (XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING).

I'd like to define that inside the EDK project, without having to modify
my system or user wide environment. I've tried adding that to the
system_incl.make but that file is overwritten at each build ...

What's the proper way to do that ? The search I've done so far didn't
get many relevant results ...


Sylvain


Sylvain,
Create a copy of system.make (call it mysystem.make) and in XPS
Project Options dialog box, point XPS to this makefile. In this
makefile, you can set the environment variable. Note that
system_incl.make and system.make are always overwritten, but you can
point XPS to use your own makefile (which is to replace system.make) and
thus change environment.

Thanks,
Amit

Yes great thanks !


Sylvain

 

[Duane Clark]

jcarr@linuxmachines.com wrote:

OT: I'll go on for what it's worth here is my attempt to use the driver
-- I'm guessing I'm not making the correct /dev/ entries for iMPACT.
Maybe someone else knows if this is possible?

Jeff

root@jcarr:/home/gpl_xilinx_driver/xilinx_pp# make
make -C /lib/modules/2.6.11-1-686-smp/build
SUBDIRS=/home/gpl_xilinx_driver/xilinx_pp modules
make[1]: Entering directory `/usr/src/kernel-headers-2.6.11-1-686-smp'
CC [M] /home/gpl_xilinx_driver/xilinx_pp/xilinx_pp.o
Building modules, stage 2.
MODPOST
...

I have no idea whether it works on a 2.6 kernel. But I notice you didn't
mention installing the windrvr6 and xpc4drvr drivers. I believe these
are needed before loading the xilinx_pp driver (at least that is what I
do). In my 2.4 kernel, I have in /etc/rc.d/rc.local:

source /lib/modules/misc/install_windrvr6 windrvr6
source /lib/modules/misc/install_xpc4drvr

 

[Duane Clark]

Tim Verstraete wrote:

Hey,

Do some of you also have a problem with adding probes in fpga editor and
then generating the bit file? i have the same problem sometimes with
chipscope (especially when i assigned the wrong one and then change it back
to the right one and then generate the bit file) .... when i generate the
bit file in those 2 situations the fpga editor just closes and crashes ...

Yes, after adding probes in the 7.1 version of fpga editor, trying to
generate a bitfile crashes every time for me. And that is both using the
Linux and the Windows version of fpga_editor.

I have not messed with the 7.1 version of Chipscope yet, but I guess
I'll have a chance to check out the crashing there soon.

 

[Peter Harrison]

"Simon Peacock" <simon$actrix.co.nz> wrote in message
news:431ebdbc@news2.actrix.gen.nz...

almost right
01101 /= -3
11101 = -3

you need to sign extend ;-)

Simon

Surely not for the example given. The fifth bit there was the carry bit from

a 4 bit operation. Thus the answer only takes 4 bits and is correct. The
carry bit is used for error detection. If the carry into the MSB and the
carry out of it are different, the 2's complement operation has overflowed.
The overflow bit in a processor is just the result of an exclusive or on the
two carries.

Pete Harrison

Sylvain's original sums:

Signed and unsigned addition are the same. Their results is to be
interpreted differently though ...

Let's says the number are 4 bits unsigned :

1001 = 9
0100 = 4
--------
01101 = 13

now if they are 4 signed :
1001 = -7
0100 = 4
---------
01101 = -3

 

[Newman]

Lina wrote:

Does anyone know? Please help me!

Thank you!

Lina

Lina,
I've used Memec's DS-KIT_2VP4LC product. I got it to boot from Flash
on an old style P160. The newer ones are a bit different. I also got
it to work booting from an ACE-CF. That was a bit more of a challenge.
I had to rework the ACE connector to fit with their ACE-CF module.
Had to fiddle with formatting the drive and put debug code in the
driver to attain visibility to debug the interface. The Flash
interface was much easier to get going.

-Newman

 

[jai.dhar@gmail.com]

Sorry, my bad. I know I have programmed them using the ASMI interface
in NIOS (is this what you are referring to by external prog.
software?), but I haven't tried using the BB cable directly to the
flash device.

On the note that it must be shipped with something special in it..
..Altera clames the device is shipped with the memory all reset to
FF's... where could they possibly store something? Jim's test
definitely sounds like something interesting to try. It's a shame
because I can't use anything more than a 4 Mbit flash device for
configuration since Quartus only supports 1 and 4 (for me at least). I
have a 32-mbit ST Micro flash device that I'm using as secondary flash
holding user-code, but I can't seem to get it working as a primary
configuration device.

Maybe the $12 increase in price over the STM counterparts is actually
something functionally different rather than a re-label