EDK : FSL macros defined by Xilinx are wrong

[Ray Andraka]

Ram wrote:

Vladislav:

Vladislav Muravin wrote:



First, I understand your situation and solidate with you.



Thank you.



Second, despite that DigiKey list those FPGAs for such high price, which
may be a bit old (?), the same devices from Virtex-II family are much
cheaper than the ones you have been screwed up with, if you check with the
distributor. Check out also the prices for similar devices, so that you
would not be screwed up with the offer...



I understand.

Two or three other people also wrote me and told me that these parts are out
of date and that there are newer parts which are cheaper, therefore I would
probably not get very much per device.

As I said, I simply wish to recover what I can. Therefore, as long as the
offer isn't insulting (such as 50 cents per chip), I would still entertain
it.

Thank you all for your kindness.

Ram.


Your best bet may be to ebay the lot. The XCV1000-4's are the oldest of

the virtex line. The price you quoted is close to the price Xilinx
asked when these were the latest and greatest (btw, the 1000's were the
biggest in that family). That family has been superceded several times
over (virtexE, then virtex2 then virtex2pro and now virtex4), and even
the low cost Spartan3 line now reaches this 1M gate density, and will
significantly outperform it at a greatly reduced cost. BTW,, Digi-key's
chip prices for Xilinx have historically been way higher than you can
get the chips from just about any place else.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Marco]

"John_H" <johnhandwork@mail.com> wrote in message
news:bDHRe.27$tN4.242@news-west.eli.net...

Look closely at the datasheet for the A/D converter. How do they say you
should acquire a reading and how are you trying to acquire it?

To start acquiring chipselect must go high for 1 clock cycle.
At the falling edge the adc starts conversion. (it's falling edge
sensitive).
After 5 clock cycles the serial data out goes from Hi-Z state to 0.
After 1 clock cycle it starts sending data through serial data out for 16
clock cycles.
Then it goes into power down state and waits for a chipselect.

I have made a state machine which follows that. Into post-place simulation
works well.

Marco

 

[huangjie]

Thanks for John_H 's replay !
I will continue use spartan3 since your boards can run well.
Any one know how Xilinx calclate the SSO number ?
Use the following formula ?
Vgnd = L * 1.52* deltaV *C / (( T(10%-90%))^2) ?
I found this in book <<High Speed Digital Design>> (Section 2.4.1.4 ).
Xilinx may be use it because this formula is linear for L and C that
mentioned in xapp689 by xilinx.
When I read xapp689, I thought Xilinx maybe make some mistake in
calclating SSO number for PCI
because PCI has no capacitance load while they use capacitance.
There perhaps some other mistake in calculate the SSO number . Because
the higher package inductance
the slower ouput. So package inductance is not the most significant
factor .
Though I write these and post it , I am not know if it is right .

Thanks to anyone for any words!

 

[Martin]

Thank you,

I will try to find an older version of the ISE Webpack on the Xilinx
website. (No luck so far, if anybody has a link I would like to hear
about it.)

[Barely resisting the urge to rant about bad quality software]

 

[Marc Randolph]

Brad Smallridge wrote:

Where would the 35 MHz noise burst in the middle of the data come from,
and why? What do you think it would look like?

It's a six layer board, I don't know where the noise would come from.
Like I said, I'm looking for a low-end solution here.

Howdy Brad,

That question was actually for Mark.

Brad, you didn't mention exactly how the clocks are fed to/between the
two FPGA's, nor how far apart the devices are.

I guess it's a synchonous source type clock, although, know that
this is the first that I am using these terms. So the 30MHz is routed
to a pin, travels about an inch, to the global clock input of the
destination Spartan. I put a DCM there, with a fixed delay now
at about 4ns, to allow some setup time for the parallel data that I
have now.

Sorry, I'm still not clear. Do I understand you that you have a single
30 MHz clock feeding both FPGA's, routed in a daisy-chain fashion, with
the second leg of the daisy-chain being only 1" long (those devices
must be really close together)? On both devices does the clock go into
the GCLK input?

Considering you are
talking about 9 bits x 30 MHz, it sounds like you're needing to
transfer at max, 270 Mbits/sec.

That's right.

As long as your traces are nice and
short, you should be able to cut this down to a single LVCMOS25 net (or
single LVDS diff pair if you want some added security and if you have a
diff pair set up between the two devices).

I did pair up the lines, in case I wanted to do just that. So what
performance increase could I expect there, ballpark?

If you do a Google search on something like "lvds advantages cmos OR
lvcmos", you'll get a number of hits, including an appnote from one of
my more favorite companies:

http://www.pericom.com/pdf/applications/AN041.pdf

Note that they list CMOS (including LVCMOS) as having a max speed of
"less than 100 Mbps". This is really, really conservative. We have a
few LVCMOS25 busses on some of our boards running at over 300 MHz.
It's all dependant on distance and slew rate.

Do I need to add termination resistor to do this?

LVDS requires a 100 ohm termination at the receiver. If memory serves,
the S3 doesn't have 100 ohm on-chip termination, so yes, you'd need to
put one as close to the pins as possible.

You may want to compare the effort and complexity of a bit aligner in
the receiver as opposed to chewing up one more pin for a bit alignment
sync pulse.

Seems to me that the source clock should be an adequate sync pulse. No?

When you take a byte (or 9 bits, in your case) and send it one after
another in a serial fashion, how are you going to know where the first
byte ends and the second byte begins? There are a VERY large number of
ways to do this.

Regards,

Marc

 

[Austin Lesea]

?

Anyone bothered to do a simulation?

IBIS, or hspice?

Flying or driving blind is not recommended.

Back of envelope calculations are worthless.

Austin

huangjie wrote:

Thanks for John_H 's replay !
I will continue use spartan3 since your boards can run well.
Any one know how Xilinx calclate the SSO number ?
Use the following formula ?
Vgnd = L * 1.52* deltaV *C / (( T(10%-90%))^2) ?
I found this in book <<High Speed Digital Design>> (Section 2.4.1.4 ).
Xilinx may be use it because this formula is linear for L and C that
mentioned in xapp689 by xilinx.
When I read xapp689, I thought Xilinx maybe make some mistake in
calclating SSO number for PCI
because PCI has no capacitance load while they use capacitance.
There perhaps some other mistake in calculate the SSO number . Because
the higher package inductance
the slower ouput. So package inductance is not the most significant
factor .
Though I write these and post it , I am not know if it is right .

Thanks to anyone for any words!

 

[John_H]

My understanding is "no."
Consider System Verilog if you "have" to use multi-dimensional input/output
ports.
The method Verilog designers often use is to make a multi-dimensional port
into a simple vector, pass tha vector, then change the vector back to the
multi-dimensional port.

"vssumesh" <vssumesh_asic@yahoo.com> wrote in message
news:1125654950.934300.218330@f14g2000cwb.googlegroups.com...

Hello all
Is it possible to instantiate multi dimensional input/output port in
verilog2001.
I tried the following code.

module A(in,out);
input [7:0]in[7:0];
output [7:0]out[7:0];

but it did gave an error in the Xilinx ISE 6.2....

Sumesh

 

[Paul Hartke]

What do you mean by the peripheral list?

That's what the target architecture should be.

Never run across either of these--can you post the *.mhs and *.xmp
files?

Paul

"zoinks@mytrashmail.com" wrote:

I just installed and updated both the EDK and ISE 7.1
I'm using the XUP Virtex-II Pro, and downloaded the accompanying BSB
package.

When I generate a design using BSB (selecting the XUP as a design
platform of course) I notice two things:

A second DDR memory is added to the peripheral list, altough I have no
idea where it comes from and what it does (it's called
DDR-DRAM<something&gt. However, the biggest problem is that I cannot
start the bitstream generation, it quits immediatly with:

ERROR:MDT - Invalid target architecture 'xc2vp30ff896-7'
ERROR:MDT - Invalid target architecture ''
ERROR:MDT - platgen failed with errors!
make: *** [implementation/system.bmm] Error 2
Done.

How can I fix this? Any help would be appreciated.

 

vssumesh wrote:

Thanks john for your replay... i will follow that way.
I am not familier with system verilog. What is the difference with
normal verilog. Can i use it on the tool chain (model sim xilinx etc)
and get the same output.

The difference Verilog and System Verilog is that your toolset (XST)
doesn't support System Verilog


You could try VHDL; multidimensional arrays have been supported on
ports for synthesis for a long time. Only kidding. John's suggestion
of a 1 dimensional port is probably the best for you.

Regards,
Allan

 

[Falk Brunner]

<denizdikmen@gmail.com> schrieb im Newsbeitrag
news:1125575027.735673.124800@g44g2000cwa.googlegroups.com...

Hello,

I want to connect a LED with Uf=1.8V and If=20mA to a CPLD (XC2C512).
But from the datasheet I get that the current is limited to I_OH and
I_OL = 8mA. Is this right? Means this that I couldn't use this LED with
1.8V? Have I to operate the LED with 8mA and the corresponding voltage
(using a resistor in series)?

You can easyly drive a 20mA LED with the Coolrunner-II. The current given in
the datasheet is the guarenteed maximum under certain measurement conditions
(Rise time, output LOW/HIGH level). For a LED this doesnt matter at all.
There is a typical I/O curve in the datasheet, from there you can see that
the output resistance is ~25 ohm. So if you draw 20mA, the output voltage
will be 0.5V away from GND or VCC (depending if you sink or source the
current). Just go ahead, calculate the appropiate current limiting resistor
value and drive the LED with 20mA. Only keep in mind that you should not
drive a logic inputs with this LED in parallel, since the the output
voltages ar not more full specification compliant (but it will work thou)

Regards
Falk

 

[John Adair]

Using a LED with a forward voltage similar to that available is likely to
give problems. The series resistor normally fitted gives a determination of
currrent but does need some voltage itself. The smaller the notional voltage
used across the resistor the wider the span of currents that may result due
to tolerances. In short using small resistor voltage gives relatively
un-predicatable currents. No resistor at all is asking for a LED meltdown
assuming it actually lights at all.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development
Board.
http://www.enterpoint.co.uk
<denizdikmen@gmail.com> wrote in message
news:1125575027.735673.124800@g44g2000cwa.googlegroups.com...

Hello,

I want to connect a LED with Uf=1.8V and If=20mA to a CPLD (XC2C512).
But from the datasheet I get that the current is limited to I_OH and
I_OL = 8mA. Is this right? Means this that I couldn't use this LED with
1.8V? Have I to operate the LED with 8mA and the corresponding voltage
(using a resistor in series)?

Regards
Deniz

 

[John Adair]

We should have something for you in Raggedstone1 when it launches if you
want to play with this.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development
Board.
http://www.enterpoint.co.uk

"Mike Harrison" <mike@whitewing.co.uk> wrote in message
news:6evbh15t3h637dafnv0qobaplj710kg9uj@4ax.com...

Does anyone know how feasible it is to drive a TFT panel LVDS interface
(sometimes called Panel-link
I think) direct from the S3 I/Os ? If so, what sort of frequency can you
get up to - I saw a mention
recently about using the DDR registers to reduce the data rate but
couldn't immediately see any
Xilinx appnotes when I had a quick look.

Also, as the IO banks on the lower-end dev boards tend to be tied to
+3.3v, but LVDS needs 2.5v,
what happens if you lie to the software about the supply - will it work to
any useful degree
(interested in lvds output only)?

 

[John_H]

My apologies - the case number was primarily for Austin's use if he wanted
to see the traffic in the AE group about what has transpired so far. I
don't know that the case can be accessed through mysupport by those who
didn't submit the case.

"huangjie" <huangjielg@gmail.com> wrote in message
news:1125684166.632535.180980@o13g2000cwo.googlegroups.com...

John_h Wrote "My case # is 597160 if you'd like to track down the
active case to see
what's going on".
Where to find more information about case # 597160 ?

 

[Jim Granville]

denizdikmen@gmail.com wrote:

Hello,

I want to connect a LED with Uf=1.8V and If=20mA to a CPLD (XC2C512).
But from the datasheet I get that the current is limited to I_OH and
I_OL = 8mA. Is this right? Means this that I couldn't use this LED with
1.8V? Have I to operate the LED with 8mA and the corresponding voltage
(using a resistor in series)?

Look at the MAX DC voltage specifications, and the Typical I/O curves.
Vol is < 0.4V @ 8mA, or 50 ohms (Max) RdsON.

Typical is just over 2x beter than the worst case, and Typical current
is ~30mA, so a worst-case port might deliver only 15mA (and still be
in-spec) - thus 20mA is pushing it, from a single pin, for volume
production.

You can draw a load-line on the I/O curves, to see the LED current.
eg assume a 3.3Vcc, and 1.8V Vf on LED, your load line will start at
X=1.5V, and will hit the Y axis at 1.5V/Rseries

A Y intercept of 30mA is appx 50 Ohms, and the Vol curve intercepts
the 1.5V<=>30mA load line, at appx 22mA
A 100 Ohms load line, gives ~12.5mA etc.

-jg

 

[Alex Gibson]

<zoinks@mytrashmail.com> wrote in message
news:1125675810.601949.45830@o13g2000cwo.googlegroups.com...

I just installed and updated both the EDK and ISE 7.1
I'm using the XUP Virtex-II Pro, and downloaded the accompanying BSB
package.

When I generate a design using BSB (selecting the XUP as a design
platform of course) I notice two things:

A second DDR memory is added to the peripheral list, altough I have no
idea where it comes from and what it does (it's called
DDR-DRAM<something&gt. However, the biggest problem is that I cannot
start the bitstream generation, it quits immediatly with:

ERROR:MDT - Invalid target architecture 'xc2vp30ff896-7'
ERROR:MDT - Invalid target architecture ''
ERROR:MDT - platgen failed with errors!
make: *** [implementation/system.bmm] Error 2
Done.

How can I fix this? Any help would be appreciated.

Installed any service packs yet ?
7.1 was unuseable for me without service packs for exactly the same setup.

Alex

 

[Falk Brunner]

"Mak" <mansoor.naseer@gmail.com> schrieb im Newsbeitrag
news:1125778063.960873.207120@g43g2000cwa.googlegroups.com...

There are many PCI or USB to serial interface options available which
support bauds of upto 920kbps. I have designed a UART interface in FPGA
but need higher baud rate driver ics to actaully get the performance I
require.

Use RS422 or RS485. This tranceivers support up to 10 Mbit/s. Much more
recommended than RS232 (differential, lower voltage swing, EMC etc.)

Regards
Falk

 

[Slurp]

"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message
news:3nugdcF3d1k8U1@individual.net...

"Mak" <mansoor.naseer@gmail.com> schrieb im Newsbeitrag
news:1125778063.960873.207120@g43g2000cwa.googlegroups.com...

There are many PCI or USB to serial interface options available which
support bauds of upto 920kbps. I have designed a UART interface in FPGA
but need higher baud rate driver ics to actaully get the performance I
require.

Use RS422 or RS485. This tranceivers support up to 10 Mbit/s. Much more
recommended than RS232 (differential, lower voltage swing, EMC etc.)

Regards
Falk

Or if you want to go even faster use LVDS.

Slurp

 

[Jim Granville]

Mak wrote:

Hello all,

I am interested in designing a custom board with serial interface and I
am searching for RS232 port driver ICs which can support baud rates
higher than 230kbps.

There are many PCI or USB to serial interface options available which
support bauds of upto 920kbps. I have designed a UART interface in FPGA
but need higher baud rate driver ics to actaully get the performance I
require.

Any recommendations?

I think you are asking about the level translators ?
You have tried the usual suspects at Maxim and Linear ?
You might also want a 3.3V supply interface device.

http://www.maxim-ic.com/Interface.cfm
shows 150 devices under "RS-232 Line Driver/Receivers"

-jg

 

[Paul Hartke]

Do you think another group is really required for this relatively small
community?

John Williams already has a good email list and archive at
http://www.itee.uq.edu.au/~listarch/partial-reconfig/ that has been
pretty active for almost two years now.

Paul

Michael wrote:

My name is Michael and I am entering this technique of partial re-configuration.

I am starting new Group of PR users. And you are most welcome to join it.

Group name: Partial_reconfiguration Group home page: <http://groups.google.com/group/Partial_reconfiguration> Group email address: Partial_reconfiguration@googlegroups.com

Regards,

Michael Zilbershlag - CEO Genesis-OS

 

[Kumar]

Write a VHDL program

4 bit add pipe
(a) behavioural arch
(b) structural arch
Can u tell?