EDK : FSL macros defined by Xilinx are wrong

[Eric]

Hey Ankit,

I did a little bit of searching and I couldn't find an example of an
evolutionary alogrithm in VHDL.

All of the Genetic FPGA work I found is done on a PC, the end product
of the evolutionary algorithim is to create the VHDL. Not the VHDL
creating itself.

Take a look at this masters Thesis
http://www.ce.chalmers.se/~mek man/MasterThesis.pdf

First you Create a template statemachine.
Then run an evolutionary program on your PC. The fitness function is a
VHDL test bench that excites the "Evolved" VHDL code This is done using
Mentor or some other simulator. This processed is continued until the
"Evolved" VHDL description functions the way you want it. Then you
download it into a FPGA.

So you see the evolutionary process is run on a PC not the FPGA. The
FPGA VHDL code is the end product.

Eric

 

[Eric]

http://www.ce.chalmers.se/~mekman/MasterThesis.pdf

 

[Sean Durkin]

Andrew Greensted wrote:

If use use the xhost system, and manually set $DISPLAY project navigator
works. So perhaps it just doesn't like the way SSH tunnels the X stuff.

Shame, I'd have preferred doing it over ssh
I have ISE6.3 running on SuSE9.3, and it works fine over SSH. $DISPLAY

is set to "localhost:13.0" for example, no other settings were
neccessary in my case.

cu,
Sean

 

[Manfred Kraus]

Sorry, I can not resist.

Have you checked the boards from CESYS GmbH ?
http://www.segor.de/cesyse.htm


regards
Manfred



"Mike Harrison" <mike@whitewing.co.uk> schrieb im Newsbeitrag
news:i326g15o5vohtc4102td43lmdcsi5ejceg@4ax.com...

I'm looking for an easy-to-use USB2.0 hi-speed device solution with the
minimum of software work
required to get a lot of data from a device into a PC.

I've found https://www.quickusb.com/ which looks to be exactly what I
want, providing DLL calls to
use at the PC end to get chunks of data, but it seems somewhat expensive
($150), especially with
their connector break-out board ($79 for a PCB with 5 connectors on it!)

If that's the only thing around, I'll use it, but was wondering if anyone
knows of anything similar
that would be worth a look (lower priced would be nice..)

Also, does anyone have any feedback on this product & the company ( can't
say I'm impressed so far
after emailing an ordering enquiry 2 days ago with no reply yet...).
This is initially for a 1-off project, but as I may well need USB2 for
future production projects,
it would be useful to get familiar with something that had a price more
viable for production use.

 

[Pasacco]

Cycle accurate sampling can not be seen in VIO. That's was not a
problematic one. Thankyou for comment.

BTW, in the code below, I can not see the expected behavior of signal
'counter' in ILA.

Problem is that I only see : 4 4 4 4 .........

When rst = 0, en = 1, the signal change "0 1 2 3 4 " should be seen in
ILA waveform.
But actually so signal change can be seen.

What is the problem?
By the way, Is this problem?

Thankyou.

------------------------------------------------------------------------
-- Expected signal 'counter' behavior : 0 1 2 3 4 4 4 4 .....
------------------------------------------------------------------------
entity top is
port
( clk : in std_logic;
cnt : out std_logic_vector(3 downto 0) );
end top;

architecture behave of top is
signal counter : std_logic_vector(3 downto 0):=(others=>'0');

signal rst, en: std_logic; -- In VIO, reset=0, enable=1

begin
process(en,rst,clk,counter)
begin
if en='0' then
counter <= (others => '0');
elsif rst='1' then
counter <= (others => '0');
elsif counter <= "0011" then
if ( clk'event and clk = '1') then
counter <= counter + 1;
end if;
end if;
end process;
cnt <= counter(3 downto 0);
end behave;

 

[Adrian Knoth]

Andrew Greensted <ajg112@ohm.york.ac.uk> wrote:

Hi All,

Hi!

I'm trying to persuade xilinx ISE to display on a remote machine.

I cannot talk about ISE, but XPS works through ssh -X.

There is one thing worth mentioning it: if I try to run XPS on
my local display (no remote usage), I have to set DISPLAY
to ":0", but it is *not* working when DISPLAY is set to ":0.0" (which
is the default on my debian system).

HTH

--
mail: adi@thur.de http://adi.thur.de PGP: v2-key via keyserver

Win95 ist wirklich intelligent. Es macht immer das, was du nicht willst.

 

[Neo]

sure thats should be possible. there is something called as a
dont_touch attribute which you should look for.

 

[Symon]

<ScreamingFPGA@yahoo.com> wrote in message
news:1124328260.084464.275430@g44g2000cwa.googlegroups.com...

The old Volvo 240's had a 'Bulb Failure Warning Light' on the
dashboard. But what about the case where that bulb failed? Oh no!
Infinite recursion...

Luckily, in all the cars I've had, the warning bulbs all come on briefly as

you turn on the ignition. This way you know if they're working or not!
Cheers, Syms.

 

[Alex]

It is possible.
Check the constrain documentation. In XILINX the constrain called (if i am
not mistaken)
something like FSM_coding or similar.

--
Alex

 

[Ed McGettigan]

Pasacco wrote:

Yes, it is correct.

In ILA, we can see the transition of the signal in a cycle accurate
manner.

BTW, What I want to see in ILA , in the example above, is

'counter' signal change (0 -> 1 -> 2 -> 3 -> 4 ) part.

Those transitions occur during the first 4 clock cycles, after (rst='0'
and en='1').

In my exercise, I do not see them. I only see the value '4', whih is
the last value.

Is it possible to see, in ILA, those signal transition behaviors in the
example above?

I don't understand what you are looking for or what problem you
are having. You will need to explain it better for me to be able to
help you.

Also after reviewing your VHDL code again it is not written
in the standard way to define a registered counter and I am
not sure what would actually be synthesized in the design.

Specifically, you have any asynchronous comparison function
(counter <= "0001") before the clock edge definition
(clk'event and clk='1'). I'm not sure what would synthesized
with this code, probably a gated clock, but it likely won't
be what you intended.

Ed

 

[Marco]

"Kolja Sulimma" <news@sulimma.de> wrote in message
news:430492a6$0$25879$9b4e6d93@newsread2.arcor-online.net...

ADC_MUX is a transparent latch controlled by seq_daq_state. Therefore
synthesis treats seq_daq_state as a clock signal.

You need to either assign a value to ADC_MUX in all branches (including
the case that seq_daq_state=seq_daq_state_4 and mux_channel(1)='1') or
you to add an edge triggered DFF for ADC_MUX.

Kolja Sulimma

Marco schrieb:

when seq_daq_state_4 =
if ( mux_channel(1) = '1' ) then
Adc_Mux <= "001";
end if;

when seq_daq_state_5 =

I have modified every state where I verify if mux_channel is '0' or '1' into
the following:

when seq_daq_state_4 =>
Adc_Mux <= "001";

In this way Adc_Mux has a value set into all states, but XST adds BUFG to
signals in any case.

What could I do?

Marco

 

[Mike Treseler]

Marco wrote:

I need to use modelsim with a remote desktop, when someone is using the
remote computer.
With XP SP2 is possible applying a patch found on the web.
But in this way Modelsim doesn't accept license and closes itself.

Either the other user has the license tied up
or you need a new license file tied to the other computer.

-- Mike Treseler

 

[Vladislav Muravin]

This is a very interesting statement.

Other than www.opencores.org, try thinking about FPGA implementation of:

(*) H.264 codec
(**) Multi-Protocol Encalsulation of any data traffic + ATM SAR
(***) Ethernet switch (data processing path)
(****) Turbo Encoder / Decoder for Comm
(*****) LDPC codes for Comm
(******) Fast Filtering of Ethernet traffic
(*******) !!!!!! TDM Over IP (Packet) Circuit Emulation Data Processing
Engine
(********) T1/E1/T3/E3/T4/E4/Packet over SONET mapper

If you are really interested.... those are only samples of what could
actually done.

Vladislav


"easystep2" <chanhanmate260@yahoo-dot-com.no-spam.invalid> wrote in message
news:-fydnVSBw5z4b5_eRVn_vQ@giganews.com...

Hi friends,

I am new to this forum...and found that you guys are really helpful to
each other with strong knowledge on FPGAs. So i thought to get your
help. So i would really appreciate you guys if you can help me..

I am a graduate student and going to start my MS final project in this
fall semester. My interest lies in FPGA-based designs. These can be
either in cosumer, broadcast, medical, automotive etc.
industries....

So i need your help to find an interesting, new project topic (for
FPGA-based design) for me on whicd i can do some research and make
some thing new...

So i hope you guys would share your opinions....

thanks much

 

[Pete Fraser]

"Vladislav Muravin" <muravinv@advantech.ca> wrote in message
news:zW3Ne.12509$7R.712644@news20.bellglobal.com...

Antti,

Two things:

(*) What's the story with 5 bucks?

Antti has given a lot of good information to this group
in the past, so I was tempted to spend the five bucks
to find out. However, I decided to get a couple of tacos
for lunch instead.

(**) I could not find this reply && so can someone explain what the hell
is going here. This "someone" should be (Antti || Xilinx).

http://groups-beta.google.com/group/comp.arch.fpga/browse_frm/thread/ce4294513319e0a3/1f1c2f77eaefea10?lnk=st&q=%22this+may+have+been+a+mistake%22+group:comp.arch.fpga&rnum=1&hl=en#1f1c2f77eaefea10

 

[Ben Twijnstra]

Hi Designfreek,

Hi Guys
i am working on the image processing side and i wanted to impliment a
function on the APEX20KE device and the clock that i want to use is the
internal PLL so Kindly let me know how can i do that.

I guess Subroto's answer is as complete as it can get. Just a few comments:

Be sure that you're targeting an APEX20KEblablabla-X device - the non-X
devices' PLLs are untested.

I'd personally pick a newer Altera family member, such as the Cyclone or
Stratix devices - much more versatile PLLs and much higher performance -
but I guess you've got to work using an existing board.

Best regards,


Ben

 

[Pasacco]

Hi

Falling edge trigger, and now it works. Thankyou for nice comment and
correction.

With gratitude

 

[Vladislav Muravin]

Austin,

First, thank you for the prompt response; now i understand the picture.

Well.................. I have pretty similar personality to Antti's (not
entirely similar !!! )
So, statistically speaking, your explanation of your response whatever it
was (let's not call it apology, I hate this word) should have made a
difference and I would let Antti spend a few days and finally chill down.

And if Antti still reads this post, I would advise following of my "life
guidelines", which is "Try judging people not by mistakes they make, but
whether they can realize && acknowledge && let you know that they understand
they made one". After all, we are people first, and only then,
Angineers.............

Best regards.

Sincerely,
Vladislav



"Austin Lesea" <austin@xilinx.com> wrote in message
news:cy7Ne.3108$Z87.1391@newssvr14.news.prodigy.com...

Vlad,

No secret, it was I who offended Antti. I have apologized to him
personnally. I did not intend to slight him in any way. In fact, his
comments have been, and continue to be, very valuable to Xilinx.

I respect Antti, if and when he feels comfortable with posting again, or
when he feels it may be useful to post, it will be up to him to decide. I
can live with that. Everyone here has the right to post, or not to post,
and if they post, to post what they will.

It takes time and energy to post here, and some people get things done
without the bother. For example, the largest source of email addresses
for spam are harvested from newsgroups (unfortunately).

I reserve my right to reply to postings as well. I also have the best
email filtering imaginable (three levels), and our internet service
provider is daily driven crazy by the number of spam emails they have to
block for Peter and me.

I never intended to insult or offend anyone.

Austin


Vladislav Muravin wrote:

Antti,

Two things:

(*) What's the story with 5 bucks?
(**) I could not find this reply && so can someone explain what the hell
is going here. This "someone" should be (Antti || Xilinx).

Thanks

Vladislav

"Antti Lukats" <antti@openchip.org> wrote in message
news:ddt6pp$rjq$01$1@news.t-online.com...

Hi all

I am regret to inform you all that this the last time I either post or
reply to comp.arch.fpga newsgroup. This decision was triggered by an
reply from an Xilinx employee to one of my postings. If someone wants to
look up that posting then its around the sentence: "This may have been a
mistake" - I do understand that I may have understand the original
intentions of that posting and that sentence and the context wrong, but
that doesnt make any difference to my decision which is final. I will not
discuss this matter in public or make any comments on it. A small
explanation about the reasoning and background of my decision is
available but not for free and not for quoting or republishing by any
media.

http://shop.openchip.org/shop/product_info.php?cPath=28_29&products_id=36

Antti Lukats, posted to comp.arch.fpga at 1900PM on 16 August 2005

my final smile to all of you.

 

[Thomas Entner]

Hi rick,

the e-mail mysupport_cs@altera.com (from your discussion about this in the
past) has worked out fine for me. They have even changed the incorrect
e-mail-address on their web-page, now.

But for your orignal question: My bet is that they are located in India...
(not sure if I should place a smiley here).

Regarding the LAN I would contact a your FAE, this should be much easier
then via their web-page.

Regards,

Thomas

"jedi" <me@aol.com> schrieb im Newsbeitrag
news:YAXNe.103$kc4.37@read3.inet.fi...

Hello...


Can somebody tell me what people work behind Altera's mysupport?

Trying now since a month to explain them to change my contact details...
without success...now just no feedback anymore since 2 weeks!!!


Next problem coming in the form of a motherboard upgrade with
built-in LAN...probably takes half a year to switch Quartus/NIOS
license...



rick

 

[Mike Treseler]

James Morrison wrote:

This is the same discussion (I think) for every FPGA family
that doesn't have built-in tri-state buffers.

The discussion's over.
There haven't been any real
internal tri-buffs for many years.
It's actually a good thing.

All the modules can just hook up to the data bus and
the peripheral I/O as need be. All modules would be memory mapped and
would connect to the system data bus for uc control.

This is a very good idea. When the IO registers are
all in one module, changes are painful.

How I intended to implement this is with a tri-state like bus knowing
that the synthesizer would replace the tri-state bus with a mux. That
is actually what I want but I'm not sure how to get it.

Consider modeling what's really there --
gates and clock-enabled flops.
Separate writedata from readdata signals.
Write regs are clock enabled for the correct address in write mode.
Read regs drive readdata for the correct address in write mode.
Nothing to it.

Here's a cpu_reg example procedure.
It is intended to be called from a synchronous process.

-- Mike Treseler
---------------------------------------------------
procedure cpu_regs is -- CPU registers
-- this procedure does some post processing on the rx and tx
-- state variables and must *follow* those procedures.
begin
W : if write_stb = '1' then
case address is
when '0' =>
TXQ : Tx_v := writeData; -- grab a byte
kick : TxState_v := START; -- kick off tx
when others => -- nop for cpu write to unused address
end case;
end if W;
-- +----------------------------------------+
-- | Table 1 UART Memory Map |
-- +------+-----+-----+----------+----------+
-- |Name |Add |R/W |Data |Comment |
-- +------+-----+-----+----------+----------+
-- |TXQ |0 |W |7_downto_0| Transmit |
-- | | | | | Data |
-- +------+-----+-----+----------+----------+
-- |RXQ |0 |R |7_downto 0| Receive |
-- | | | | | Data |
-- +------+-----+-----+----------+----------+
-- |StatQ |1 |R |2->TxReady| Status |
-- | | | |1->RxError| Data |
-- | | | |0->RxReady| |
-- +------+-----+-----+----------+----------+
R : if read_stb = '1' then
case address is --
when '0' => -- Collect a byte from the input shifter
RXQ : read_data_v := Rx_v;
RxState_v := IDLE; -- restart the read cycle
when '1' =>
StatQ: if RxState_v = FULL then -- Update rx status:
RxReady : read_data_v(0) := '1'; -- data ready
elsif RxState_v = ERR then
RxError : read_data_v(1) := '1'; -- bad stop
RxState_v := IDLE; -- restart
end if;
if TxState_v = IDLE then
TX_Ready : read_data_v(2) := '1'; -- Update tx
end if;
when others =>
end case;
end if R;
end procedure cpu_regs;
-- For details see http://home.comcast.net/~mike_treseler/

 

[MikeJ]

What I am trying to do is to hookup multiple peripheral modules that
have all functionality and address decoding contained in separate trees
in the hierarchy. The ides is that I can add a uart, digital io, ...
peripherals at the top level and none of the logic for the other modules
needs to change. All the modules can just hook up to the data bus and
the peripheral I/O as need be. All modules would be memory mapped and
would connect to the system data bus for uc control.

How I intended to implement this is with a tri-state like bus knowing
that the synthesizer would replace the tri-state bus with a mux. That
is actually what I want but I'm not sure how to get it.

How is this for an idea : (Some examples from www.fpgaarcade.com.)

This is in the Bally code top level. It intantiates a cpu and number of
peripherals. I bring out of each peripheral an "output enable" signal and
the data bus, then build a mux to to the biz at the top level. Big
multiplexers are expensive (you are building a priority mux so be careful -
if you preserve the hierarchy in the synthesis tool it won't spot they are
exclusive) but for an 8 bit data bus you can get away with it. If nobody is
enabled I return a "floated high" bus, but you can do a bus hold by
registering the muxer result, and returning that as the default. The vic-20
does that I think.

Cheers,
MikeJ

peripheral instantiation :

u_data : BALLY_DATA
port map (
I_MXA => cpu_addr,
I_MXD => cpu_data_out,
O_MXD => mx_data,
O_MXD_OE_L => mx_data_oe_l,

-- cpu control signals
I_M1_L => cpu_m1_l,
I_RD_L => cpu_rd_l,
etc
I
mux :

cpu_src_data_mux : process(rom_dout, sys_cs_l, I_CAS_DATA, cas_cs_l,
I_EXP_OE_L, I_EXP_DATA, exp_buzoff_l,
mx_addr_oe_l, mx_addr, mx_data_oe_l, mx_data,
mx_io_oe_l, mx_io)
begin
-- nasty mux
if (I_EXP_OE_L = '0') or (exp_buzoff_l = '0') then
cpu_data_in <= I_EXP_DATA;
elsif (sys_cs_l = '0') then
cpu_data_in <= rom_dout;
elsif (cas_cs_l = '0') then
cpu_data_in <= I_CAS_DATA;
elsif (mx_addr_oe_l = '0') then
cpu_data_in <= mx_addr;
elsif (mx_data_oe_l = '0') then
cpu_data_in <= mx_data;
elsif (mx_io_oe_l = '0') then
cpu_data_in <= mx_io;
else
cpu_data_in <= x"FF"; -- emulate floating bus pulled hi
end if;
end process;