EDK : FSL macros defined by Xilinx are wrong

[Marko]

Yes, I had that problem. I presume you meant a .coe file. Turns out
this is a simulation problem when using that particular core (version
6.2 I believe). In my case, I reverted back to the ver 6.1 core and
was able to input a .coe file. After that, simulation worked fine.


On 22 Aug 2005 04:59:41 -0700, "alpha" <zhg.liu@gmail.com> wrote:

Hi, I am using ISE7.1i + SP3 target on a Virtex-4 FX12 fpga. The dual
port block ram core generated by Coregen does not contain the
initialization data defined in a .ceo file. The simulation using
Modelsim is OK after I modified .v file to specify the correct .mif
file.

Anyone has same problem and how to solve?
Thanks

 

[alpha]

Yes version 6.2 core has problem. Not only for Simulation, but also for
real implementation. You can modify paremeter c_has_default_data(=0)
and c_mem_init_file(=your .mif file name) in generated .v file. This
will allow Modelsim work. But still has issue to generate .bit file. I
have to switch to single port memory. It works. So I believe it is a
tools' bug. Do not know why Xilinx's software has so many problems?




Marko wrote:

Yes, I had that problem. I presume you meant a .coe file. Turns out
this is a simulation problem when using that particular core (version
6.2 I believe). In my case, I reverted back to the ver 6.1 core and
was able to input a .coe file. After that, simulation worked fine.


On 22 Aug 2005 04:59:41 -0700, "alpha" <zhg.liu@gmail.com> wrote:

Hi, I am using ISE7.1i + SP3 target on a Virtex-4 FX12 fpga. The dual
port block ram core generated by Coregen does not contain the
initialization data defined in a .ceo file. The simulation using
Modelsim is OK after I modified .v file to specify the correct .mif
file.

Anyone has same problem and how to solve?
Thanks

 

[Marco]

"Marco" <marcotoschi@nospam.it> wrote in message
news:def8gn$711$1@news.ngi.it...

Hallo,
I have made a small microcontroller based on microblaze, with a Spartan 3
starter board.

At power on, I would load bitstream into fpga and my software into board
ram.

I have programmed using impact the board flash rom with file: download.bit
(generated with edk). (49% occupied).

Before uploading I have updated it with bootloader (it should be loaded
into block ram).

When I power on the board, now the fpga is configured by itself.

Now I should copy my software into flash rom.

Bootloader, at boot, should copy it into board ram and execute, but I'm
not able.

I have tried with Program Flash Memory tool, without obtaining any result.

It writes:

Processor started. Type "stop" to stop processor

And I can't write like into xmd consolle.


What could I do?

Many Thanks
Marco

I'm using a 2 Mbit flash and fpga code is 1 Mbit.

I would write my software after the fpga code.

I have read also XAPP482, but I don't have understood the way to write after
1 Mbit.

It tells to:
1)convert the elf file into mem with data2mem
2)use pc_ublaze.pl to add software to prom.

Marco

 

[John Adair]

Our Broaddown4 product may be able to come close to you requirements when it
launches early Q4.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development
Board.
http://www.enterpoint.co.uk


"Nicholas Weaver" <nweaver@soda.csua.berkeley.edu> wrote in message
news:defppv$1ppo$1@agate.berkeley.edu...

We are looking at some research prototyping of IDS work. We are
currently doing 1 Gbps prototyping on a current board, but are looking
at 10 Gbps prototyping.

Are there any FPGA boards available with:

SRAM (a few MB minimum)
A large FPGA
2 or more! 10 Gigabit ethernet interfaces.

As a bonus, 2 10-GigE plus a PCI slot would be ideal. We MIGHT be
able to get away with a single 10 GigE interface, but that would be
far, FAR from ideal.
--
Nicholas C. Weaver. to reply email to "nweaver" at the domain
icsi.berkeley.edu

 

[cyd]

Peter,

It has been awhile, It took awhile but have understood your concern
good advice. Some of my best case jitter has been an order of magnitude
better than the worst case scenarios given app notes and the DCM
wizard. I write because I wanted to confirm that this is not the case
for the buufered output of the DCM, namely, CLKIN_IBUFG_OUT.
This is merely a input clock buffer, used for high clock fan out, as I
understand it. My question, Peter, is there any jitter attached to the
ibufg componenet, and using this output from the DCM is not constrained
by the DCM jitter problem, right?

thans

Cy

 

[CMOS]

yes, if you buy it from xilinx, you will get all of it. but if you buy
it from digilent, you will not get the evaluation software. im not sure
whether im getting the other parts like JTAG cable and power adaptor if
i buy it from digilent. I prefer to buy it from digilent, because i
want to have a better device with atleast 400K gates. Im not sure
whether the starter kit is available with a better device.

 

[huangjie]

Perhaps "configuring" means after "configuring" data can be lost after
power down,
programming means NOT.

 

[Symon]

"echoisme" <ghy@eyou.com> wrote in message
news:1124873209.675446.63180@g44g2000cwa.googlegroups.com...

In Xilinx application Note XAPP501, there are two phrase ---
"configuring Xilinx FPGAs" and "programming CPLDs and PROMs"
i am not a english-speaker, and cann't fully understand the difference
of the two words "configuring" and "programming",
anybody can explain that for me? thanks a lot!

The main difference between the words is the spelling! In this context they

mean the same thing, i.e. loading a bitstream into a device. The writer may
be trying to convey some difference between a volatile configuration memory
device and a non-volatile one. I would suggest "configuring" is the better
choice for both sets of devices. To most engineers, "Programming" can also
mean the act of writing code that is subsequently to be compiled into a
bitstream, cf. "Computer programming".
The problem with English is that it has too many words. Inevitably some of
them have to mean nearly the same thing. Good for English poetry, bad for
English students!
Cheers, Syms.
p.s. Rather than "echoisme" I would choose "iamecho". ;-)

 

[Marc Randolph]

pho wrote:

Hello,
I would to use a simple/easy way to send, in multicast address, some IP
packets
fprm a FPGA Xilinx VIRTEX4 to a Ethernet network. But I don't want to
use the
PowerPC and its EMAC controller. I read that the PHY interface can be
set in hardware register but I don't know if I can use the PHY
interface as a simple
FIFO.
Is there someone who uses that way to send IP packets to a network.
I know it is strange ... but I just want to read some IP paquets define
into my FPGA.

Howdy Philippe,

Yes, it is pretty simple to compose a packet of your choice and have
the FPGA feed it to a phy (either an internal phy to the FPGA or an
external xMII-type phy). phy's have simple FIFO interfaces with a
small amount of extra signalling to indicate SOP, EOP, and idle times.
A V2Pro works as well as a V4 for this type of thing.

The easiest way would be to have a BRAM initialized with the packet
that you want to send. When given a go signal by software, a counter
can be kicked off to automaticly read the contents of the BRAM, feeding
each byte to the phy. And since BRAM's are dual-port, the next step
would be to allow read/write access to that packet in real time -
allowing the destination address (or any other byte in the packet) to
be modified on the fly.

Be sure your counter stops reading at the end of the BRAM and doesn't
wrap around to zero, continously flooding your local network with
packets (hopefully that isn't your goal to begin with).

Marc

 

[Gabor]

apsolar@rediffmail.com wrote:

Hi Guys
I was able to implement Genetic algorithms on software.
Now I am taking my project to the next level by simulating hardware
like logic gates (AND,OR,NOT) as classes in software.
Then I can create objects of these classes and evolve a circuit with
the help of these gates. Maybe evolve a NAND gate. I think it is
feasible but I would like your suggestions on this idea.
Your suggestions did help me completing the previous software to solve
an equation genetically.
I was just wondering how should I represent a circuit in the form of a
chromosome('010011010' or 'A!B&|C').Mutation is the next process and
what could possibly be a fitness function.

Ankit Parikh
Manukau Institute of Technology

Expressing gates AND OR NOT is the easy part. You need to decide
whether you want the interconnect to be defined such that an
arbitrary sequence results in a single function of inputs or
if it can express multiple disjoint functions. For the second
case what if you add a fourth "gate" type of BUF or unary pass-
through. Then in a sequence where you have unary NOT and BUF
and two-input AND and OR, each instance of NOT or BUF indicates
an input to the function. Each AND or OR would take its inputs
from the two nearest preceding function outputs. If more than
two instances occur without AND or OR, there would be a "break"
and a new function would start. For example:

NOT BUF AND NOT NOT OR BUF AND

would encode in1 & !in2 .break. (!in3 | !in4) & in5

however adding another AND or OR at the end of this sequence
would then combine the two functions:

NOT BUF AND NOT NOT OR BUF AND AND

would encode (in1 & !in2) & ((!in3 | !in4) & in5)

This seems simple enough, except that as your sequence grows
you build functions of more and more inputs, and you need a
way to encode re-use of existing inputs (e.g. mapping in4
of the above equation to in2). Perhaps someone can come up
with an interesting way to do this...

Regards,
Gabor

 

[Andrew Greensted]

Andrew Greensted wrote:

I'm trying to persuade xilinx ISE to display on a remote machine.

I've got X11 forwarding over SSH working fine. but for some reason the
project navigator just will not display.

After installing the latest Solaris Patch Cluster, I've been able to
resolve this.
Be warned though, one of the Solaris Patches breaks X11 Forwarding. You
need to disable the IPv6 stuff to get it to work again.
There's some info here:
http://supportforum.sun.com/salerts/index.php?t=msg&th=864&start=0&rid=0

Hope this helps someone.
Andy

--
Dr. Andrew Greensted Department of Electronics
Bio-Inspired Engineering University of York, YO10 5DD, UK

Tel: +44(0)1904 432379 Mailto: ajg112@ohm.york.ac.uk
Fax: +44(0)1904 433224 Web: www.bioinspired.com/users/ajg112

 

[geoffrey wall]

yes i have tried it with impact open, and also with impact closed
neither way seems to work

thanks

--
Geoffrey Wall
Masters Student in Electrical/Computer Engineering
Florida State University, FAMU/FSU College of Engineering
wallge@eng.fsu.edu
Cell Phone:
850.339.4157

ECE Machine Intelligence Lab
http://www.eng.fsu.edu/mil
MIL Office Phone:
850.410.6145

Center for Applied Vision and Imaging Science
http://cavis.fsu.edu/
CAVIS Office Phone:
850.645.2257
"Duane Clark" <dclark@junkmail.com> wrote in message
news:JUJOe.362$sV7.103@newssvr21.news.prodigy.com...

geoffrey wall wrote:
I am trying to use chipscope to debug a simple design
on the digilent spartan 3 starter board
I insert a chipscope core using ISE 7.1
i synthesize my design and download it to the board
via impact.
now when I do analyze design using chipscope from within ISE
chipscope starts, and I click the open cable icon in the upper left
corner
and the machine just sits for awhile, searching each LPT port
(yes the parallel jtag cable is connected to the machine and the board)
each of them time out i guess, and chipscope tells me:

ERROR: Socket Open Failed. localhost/127.0.0.1:50001
localhost
java.net.ConnectException: Connection refused: connect
ERROR: Socket communication not open.

any ideas?


Did you first close impact? Only one can be open at a time; they
apparently compete for the port.

 

[Nicholas Weaver]

In article <1124872726.737546.229630@o13g2000cwo.googlegroups.com>,
pho <philippe.hostiou@orange.fr> wrote:

Hello,

I would to use a simple/easy way to send, in multicast address, some
IP packets fprm a FPGA Xilinx VIRTEX4 to a Ethernet network. But I
don't want to use the PowerPC and its EMAC controller. I read that
the PHY interface can be set in hardware register but I don't know if
I can use the PHY interface as a simple FIFO.

Actually, its the MAC you want to use, not the PHY. THere is a fair
amount of overhead/complexity in the PHY layer which the MAC abstracts
into "Send data stream/receive data stream".

The V4-FX Tri-mode MAC can be accessed in a raw mode, without the
powerPC. You want to use the raw client MAC interface to do this
sending. See the users guide for this:
http://direct.xilinx.com/bvdocs/userguides/ug074.pdf

(starting at page 33)

It's not that hard (it's VERY similar to the raw client GEMAC core
that xilinx has available:

For sending, you have a data valid signal, you get a data aack signal
and you start clocking the data a byte at a time.

Likewise, for receiving, you get a data valid signal, you clock in the
data a word at a time.

If you are in full duplex mode, you don't even have to worry about
collisions, just send the data.
--
Nicholas C. Weaver. to reply email to "nweaver" at the domain
icsi.berkeley.edu

 

[austin]

All,

'Reconfigurable' has now been extended to imply that while the device is
operating, a section of it may be re-configured (changed to perform a
new or different function) and then seemlessly used.

The meaning is broader that the original.

The ICAP (internal configuration access port) means you can perform this
re-configuration from internal control sources, while performing other
functions. I believe both of these capabilties are unique to Xilinx,
starting with Virtex II.

Spartan does not provide this ICAP feature. To them, re-configure,
really means to configure the entire device, again. This is he original
pre-Virtex II definition. Although, any new design may be loaded at the
user's direction given there is more than one design to load, and a
means to control which one gets loaded.

I also know that internal partial reconfiguration is seldom used, as
there is very little tool support to enable designers to take advantage
of it. The software defined radio (SDR) application appears to be the
market driver here, with new tools being built right now to allow
designers to use one small FPGA in a SDR that is able to modulate and
demodulate dozens of over the air channel standards (SSB AM, NB FM, QAM,
GMSK, etc etc etc...) merely by recognizing the senders format (using
microblaze or the 405PPC), followed by a partial reconfiguration of mod
and demod functions, all in time to listen to who called you, and answer
back.

Exciting.

Austin


Symon wrote:

"echoisme" <ghy@eyou.com> wrote in message
news:1124940523.012775.76130@g44g2000cwa.googlegroups.com...

thanks, everybody
then what is difference between "reconfigurable" and "programmable"?
i am really confused with them for a long time!


In the context we're discussing, "reconfigurable" implies the device can be
programmed more than once. "Programmable" implies it can be configured at
least once.
Cheers, Syms.

p.s. So, "configurable" means the same as "programmable". Adding "re" at the
beginning of either word means you can do it more than once!

 

[Thomas Entner]

As far as I know, this should be possible with 4 multipliers, if everything
is unsigned. I could imagine that you also get away with 4 signed
multipliers, if you cut a bit or two from your a and b.

Regards,

Thomas

www.entner-electronics.com

"Bubba" <blabla@bredband.net> schrieb im Newsbeitrag
news:431037f6$0$18636$14726298@news.sunsite.dk...

Multiplier



Is there a good algorithm (small) to multiply two 36 bit "signed" numbers
to
get a 72 bit result.



Is it possible to divide the 36 bit numbers into 18 bit parts and multiply
them separately and after some shifting add the results?



I would like to instantiate the MULT18X18 in the Spartan3 for this.



When I write it strait like this without any specific instantiation:



library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity test is

Port ( a : in std_logic_vector(35 downto 0);

b : in std_logic_vector(35 downto 0);

q : out std_logic_vector(71 downto 0));

end test;



architecture Behavioral of test is



begin

q <= signed(a)*signed(b);



end Behavioral;





It uses 9 MULT18X18!!!!!

 

[Sylvain Munaut]

Bubba wrote:

Multiplier



Is there a good algorithm (small) to multiply two 36 bit “signed” numbers to
get a 72 bit result.



Is it possible to divide the 36 bit numbers into 18 bit parts and multiply
them separately and after some shifting add the results?

Sure, google for "Karatsuba multiplication"
You should achieve that with just 3 multiplier and some adders.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity test is
Port ( a : in std_logic_vector(35 downto 0);
b : in std_logic_vector(35 downto 0);
q : out std_logic_vector(71 downto 0));
end test;

architecture Behavioral of test is
begin
q <= signed(a)*signed(b);
end Behavioral;


It uses 9 MULT18X18!!!!!

Try with USE IEEE.STD_LOGIC_SIGNED.ALL



Sylvain

 

[Fpga_Designer]

Hello ,

It was a simple error from my side. I included the Unisim libraries
between synthesis translate_off and translate_on. Once I remvoed those
it works fine

Thanks

 

[Alex Gibson]

"CMOS" <manusha@millenniumit.com> wrote in message
news:1125292691.124584.29570@f14g2000cwb.googlegroups.com...

does any one know where to find some example projects for spartan 3
starter board for digilent.
CMOS

http://www.xilinx.com/products/boards/DO-SPAR3-DK/reference_designs.htm

can also easily adapt a lot of the examples on www.fpga4fun.com and
http://www.xess.com/ho03000.html

 

[Marc Randolph]

abgoyal@gmail.com wrote:

Thanks, Marc and Mike, for your responses.

Marc, practially all of those links you listed (some i had not found on
my own, thanks again), talk about RAM, and write coherency etc. As i
only need a ROM, these are non-issues for me.

Howdy Abhishek,

I was only attempting to find examples of inferred memories with two
read ports. Just drop the write portion of the code, find a way to
INIT_ the BRAM, and you *might* have an inferred dual-port ROM. Unless
your syn tools decides you really wanted two single port ROM's ;-).

Mike, your option "2" is what I am doing right now, and I do have BRAMs
to spare so this is sufficient for now, as i am using the larger FPGA
for prototyping, but the rest of my design is so small that just cause
of the BRAM problem I will have to keep using this much more expensive
FPGA. If i can use a dual proted BRAM, then i can use the smaller
cheaper one.

I guess I can just go ahead and instantiate the BRAM blocks manually to
solve that problem.

From both of your responses, I guess the consensus that can be derived
is there is no portable way to infer a dual ported ROM. Is this true
for VHDL as well?

Depends on how you define portable, but in most senses of the word,
probably not.

I was hoping that some newsgroup members who work at one of the
synthesis tool-vendors would have some suggestions?

Indeed. Hopefully Ken McElvain will see this and add his Synplify take
on it.

Marc

 

[Eric]

"...Altera continues to sell Excalibur devices, this product family is
not recommended for new designs. Designs requiring embedded processors
should consider Altera's NiosŽ II processor.

Excalibur devices integrate a 200-MHz processor with the APEX™ 20KE
FPGA architecture, balancing the price, performance, and system
integration requirements of system-on-a-programmable-chip (SOPC)
designs."

Not sure if this is just research or product development, but you could
still get Excalibur devices.
Eric