EDK : FSL macros defined by Xilinx are wrong

[Alex]

Well it is fully asynchronous design - sort of concept-proof,
more in demonstration purposes. I know FPGA is not the proper platform
for it at all, however everything is working fine, apart that problem.

So can anyone help with the problem when the synthesiser optimize the
design by throwing buffer elements away?



--
Alex

 

[Marc Randolph]

dalai lamah wrote:

Which is the preferred way to generate the output clock for a deserializer
made with a shift register? For example, let's say I feed a 4-bit shift
register with a 500 MHz signal, so that I have to store four bits at 125
MHz into a BRAM (or just latch them). How do I generate this 125 MHz clock?
I can't use a DCM because the input frequency is out of range, but if I
generate the clock with common logic (e.g. a binary counter or a shift
register), how can I be sure that it won't violate the hold/setup times in
respect to the four output bits?

Howdy,

Two ways to solve this:

1. If the 125 MHz "clock" isn't needed for a considerable amount of
logic, strongly consider generating and using a clock enable that is
actually in the 500 MHz domain.

2. If you have a bunch of logic that needs to run at 125 MHz, the DCM
has a CLKIN_DIVIDE_BY_2 mode to handle higher frequencies:

http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/cgd/cgd0064_25.html

Have fun,

Marc

 

Peter, thanks for your reply.
Sudhir


Peter Alfke wrote:

Sudhir,
so you have two sets of synchronous signals (hopefully synchronized by
the same global clock) and you combine them through combinatorial logic
to generate 2 control signals for the counters.
Obviously, you will generate glitches on these outputs, as a result of
prop delay differences in the combinatorial logic. But these glitches
occur a few nanoseconds AFTER the active clock edge, and they are,
therefore, irrelevant and cause no harm.
The beauty of synchronous logic is that inputs need only be stable
during the set-up time BEFORE the clock edge.
Peter Alfke, Xilinx Applications (from home)

 

Hi Rob
I undertsand why you are making a point about crossover.I have done
exactly the same thing. I use a special class to compare and sort the
population based on their fitness. Keeping in mind 'elitism',I also
copy the best solution to the new population. Then from a population of
six, I select 4 best values and average out consequent numbers.
Mutation- to randomise mutation process ,I select 4 members after
crossover and either add 1 0r subtract 1 depending on computer clock
ticks.This process is completely random.
Here's a piece of code for the above:

//Elitism - copy the best solution to the next generation
Array.Sort(RepopulationPercentage);
Best = RepopulationPercentage[popsize-1].accessElement;
listBox1.Items.Add("Best = "+Best);

//Crossover
int m=popsize-1;
listBox1.Items.Add("After Crossover");
listBox1.Items.Add(population[0]);
for(i=1;i<popsize-1;i++) //elements
{
population.SetValue((int)((RepopulationPercentage[m].accessElement+RepopulationPercentage[m-1].accessElement)/2),i);
listBox1.Items.Add(population);
m--;
}
if(dt.Ticks%2 == 0)
population[popsize-1]=Best - 1;
else
population[popsize-1]=Best + 1;

//Mutation
listBox1.Items.Add("After Mutation");
listBox1.Items.Add(population[0]);
for(i=1;i<popsize;i=i+2) //elements
{
if(dt.Ticks%2 == 0)
population.SetValue((int)(population+1),i);
else
population.SetValue((int)(population-1),i);
listBox1.Items.Add(population);
}

Eric's psuedo code and a genetic algorithm template from a website
helped me write the code.
Ankit

 

[Andy Peters]

Alex wrote:

Hi guys.

Implementing asynchronous delays in my design via a chain of buffer
elements
(I know it's a bad practise, but I need few ns delays) I faced the
problem with
removing them from the design, as Xilinx synthesiser removes these
elements from
the design, although the OPTIMIZE option is off.

So I'd like to ask if anyone can tell me where I missed something, and
also if someone
already implemented small delays via internal FPGA units (not RC
chains)which elements
may provide the biggest delay (in order to save space).

Why do you need an async delay?

-a

 

[Andy Peters]

Fpga_Designer wrote:

Hello all,

I am currently using xilinx modular design flow to develop a simple
design. The top level design has an inout port for communicating data
between an external memory and fpga. I have implemented the necessary
control logic for this port in one of the modules and port mapped the
port of the module to the top level inout port. After having done this
when I run (ngdbuild -modular initial top.edd) with all the modules
instantiated (black boxes only) I receive the following error
"ERROR:NgdBuild:456 - logical net '***' has both active and tristate
drivers".

Can anyone suggest what needs to be done in this regard.

Did you simulate your design?

The error is clear -- you have two drivers on the same net. A
simulation would have shown this.

-a

 

[Andy Peters]

311f037@gmail.com wrote:

Hey!

SUpposing im using Xilinx ISE 4.2, how do I go about creating an EDIF
file to load into this as thats the only thing I seem to be able to
import into the 4.2v

So what do I need to do? somehow find a compiler? or a simulator? will
these output and EDIF from my VHDL?

Both Mentor Precision Synthesis and Synplify compile with EDIF as the
result.

-a

 

[Alex]

Thanks it helped! Maybe if you have some experience you can suggest how
maximise delay,
using minimum hardware. I can gues that to use most of the slice hardware
something like a chain
LUT->mux->FF, but is it possible to implement two of chains within one
slice (Spartan3) via manual placing;
or maybe there are some other ways? The design is internal so I can't play
with IOB's and external logic.

Thanks

Look up the "keep" and "save" attributes.

Can't remember which does what (been too long since I played games like
you are doing), but if you want the logic there that you put in, and do
not want it optimized out.

Austin


Alex wrote:

Well it is fully asynchronous design - sort of concept-proof,
more in demonstration purposes. I know FPGA is not the proper platform
for it at all, however everything is working fine, apart that problem.
So can anyone help with the problem when the synthesiser optimize the
design by throwing buffer elements away?

--
Alex

 

[Vladislav Muravin]

Brian,

could you please paste your code here?

Vladislav

"Brian Dam Pedersen" <brian.pedersen@mail.danbbs.dk> wrote in message
news:4300b246$0$67262$157c6196@dreader2.cybercity.dk...

Hi group

I'm trying to infer an 18-bit rom to be put in a block RAM. I'm using a
case statement and a clocked address as described by Xilinx. My ROM is
1024 words, so I was thinking that this could be done using only one BRAM,
but the ISE 7.1 webpack creates two BRAMs in this case. Isn't it possible
to fit more than 16 bits of ROM into a single BRAM ? I can fit 18 bits of
RAM so why not ROM ?

-- Brian

 

[Jeremy Stringer]

311f037@gmail.com wrote:

Hey!

SUpposing im using Xilinx ISE 4.2, how do I go about creating an EDIF
file to load into this as thats the only thing I seem to be able to
import into the 4.2v

So what do I need to do? somehow find a compiler? or a simulator? will
these output and EDIF from my VHDL?

I did a google filetype:edif search to see whether this helps me
explain it further to myself, but it seems like a net list or something
that you create after placing the cells (or what ever its called) and I
havent done that, Ive typed my VHDL and made a UCF file, so what now?

Can anybody give me an overview (ASSII flow chart?? heh) of what I need
to do from VHDL to sythesising with ISE 4.2? its the steps in the
middle I can't figure out!

Sven, approximately the sequence of steps that you go through is this -

You take your VHDL (and constraints file - ucf for a xilinx native
flow), and run it through a synthesiser (AFAIK, this is XST for ISE).
This gives you a file with a set of primitives relevant to the FPGA you
are working with (EDIF for me)).

You then dump it through another couple of tools to get an .ncd, which
you run place and route tools on (You may get a few intermediate files -
my toolflow differs).

At the other end, you get a .bit, which is the file you load into your FPGA.

Shouldn't the GUI handle this? You probably want to figure out how to
get your vhdl files into your project - the ISE toolset should handle
the whole process of going from VHDL to bitstream.

The other point is that ISE 4.2 is quite old - you might want to
consider getting a more up-to-date set of tools (ex: 7.1 is out at the
moment). I know that schematic entry used to be popular - can you
confirm that you actually have a synth. tool?

You can download the webpack free from Xilinx, but if you're running
foundation, then that has more tools, and you probably want to try
getting the setup that you have working first.

Jeremy

 

[Uwe Bonnes]

Peter Alfke <peter@xilinx.com> wrote:

Jim, what do you suggest:
Whenever somebody in Xilinx suggests an application, all software is
put onhold until the new idea has passed all software?
Or: Whenever somebody in Xilinx suggests an application, it may not be
published until it has passed all software implementations?

The specific idea in this thread is over 30 years old, and had been
proven in many TTL designs, but had not been synthesized, because
synthesis did not exist at its birth.

Nevertheless, I have gone back and made some circuit ideas more
synthesis-friendly...
Peter Alfke

With the thread " ISE 7.1 'improvements' plus meandering.... " Jim probably
suggested to put more entries in a regression suite that is hopefully run
before each ISE release/service pack...

--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

 

[Austin Lesea]

Uwe Bonnes wrote:

Uwe,

I understand. Most regression test suites are huge designs intended to
cover as much ground as possible. Adding in a debounce ciruit as a
separate test isn't productive. Now having one "goofy" suite with ALL
of the strange and wonderful test cases that are three lines or less
would be useful....

Something to work towards.

Austin

Peter Alfke <peter@xilinx.com> wrote:

Jim, what do you suggest:
Whenever somebody in Xilinx suggests an application, all software is
put onhold until the new idea has passed all software?
Or: Whenever somebody in Xilinx suggests an application, it may not be
published until it has passed all software implementations?


The specific idea in this thread is over 30 years old, and had been
proven in many TTL designs, but had not been synthesized, because
synthesis did not exist at its birth.


Nevertheless, I have gone back and made some circuit ideas more
synthesis-friendly...
Peter Alfke


With the thread " ISE 7.1 'improvements' plus meandering.... " Jim probably
suggested to put more entries in a regression suite that is hopefully run
before each ISE release/service pack...

 

[Austin Lesea]

Paul,

Fastest way to get an answer to this is to open a webcase. We do
provide support for old software and devices.

Austin

Paul Urbanus wrote:

I am assisting in the debug of a board with XC5202 parts. The design is
done using Aldec schematics in the M1.4 environment. I have M1.5 set up
on Win2K in a VMWare virtual machine.

Q: Does anyone know the latest version of the Xilinx implemenation tools
which support the XC5200?

Q: Latest version of Foundation Express which supports XC5200?

Q: Can either of these older versions be installed/run from Windows 2000?

Q: How can I get the latest patches/service packs for tools with XC5200
support?

I have a valid license for Foundation Express version which supports
XC5200. Following is from my license.dat

PACKAGE FND-EXP-PC xilinxd 1.000 30A0C0B1948681FADED8 \
COMPONENTS="system-PC bit-PC \
xc3000D-PC xc4000X-PC xc5200X-PC \
ngd2vhdl-PC verilog-PC \
Foundation-PC X-VHDL-PC \
FPGA-Express:1997.110 \
FPGA-Express-VHDL-Base:1997.110 \
FPGA-Express-VLOG-Base:1997.110 \
FPGA-Express-XC3k-Optimizer:1997.110 \
FPGA-Express-XC4k-Optimizer:1997.110 \
FPGA-Express-XC5k-Optimizer:1997.110 \
FPGA-Express-XC9k-Optimizer:1997.110 \
FPGA-Express-Constraint-Mgr:1997.110 "

Does anyone know what version of Foundation Express this license applies
to?

To Xilinx: How can I get this license renewed? How can I get a copy of
the install CD and patches for this version of Foundation Express?


TIA
Urb


_______________________________________________________________________________

Posted Via Uncensored-News.Com - Accounts Starting At $6.95 -
http://www.uncensored-news.com
The Worlds Uncensored News Source

 

[Duane Clark]

Jeremy Stringer wrote:

Sven, approximately the sequence of steps that you go through is this -

You take your VHDL (and constraints file - ucf for a xilinx native
flow), and run it through a synthesiser (AFAIK, this is XST for ISE).
This gives you a file with a set of primitives relevant to the FPGA you
are working with (EDIF for me)).

Sven's problem is that he is using ISE 4.2, which I am fairly sure did
not come with a synthesis tool. I don't really see an easy solution for
him. Presumably he is trying to use a very old part, or else I don't
understand why he would be using ISE 4.2. A very old part would probably
require a very old synthesis tool.

 

[Bob]

On Tue, 16 Aug 2005 16:18:45 GMT, james <george@washington.edu> wrote:

On Tue, 16 Aug 2005 09:06:10 -0400, Bob <bob@notrealmail.com> wrote:

+<Hi does anybody have a design example of an image sensor connected to
+<programmable logic with HDL code?
+
+<I want to try this. I have not committed any hardware yet so a working
+<example would be a great starting point.
+
+<Mostly concerned with the physical connections and image sensor low
+<level interface code.
******

FIrst off you are ging to have to decide on type. Frame Transfer,
progressive scan or CMOS imager. Each one has their advantages and
disadvantages. External clock generation will differ with each. FOr
the most part the Frame Tranfer Imagers, mostly TI, have large gate
capacitances and the clock source for these chips are not drivable
from a FPGA. Peak currents to the SAG and IAG of the TI chips can be
in the range of 1 amp.

All imagers will clock each pixel out serially, that analog output is
then fed to an ADC. You can bin adjacent pixels to form larger pixels
and even bin rows to increase pixel size. SOme imagers allow this to
be done internal to the chip.

Then you need to determine what application this camera is used for.
Still pictures using fast integration times, slow integration times,
or video and how many FPS you want.

Each type of imager requires it own unique interface. So decide from
which type depending on apllication needs and then start thinking of
what circuits are needed around the imager.

james

I am looking for somthing realativly simple. I would like to keep the
power and complexity low. Frame rate is not very important to me.
I mostly want to learn so books, design examples app notes or your own
finished designs woould be great.
so simple cheep low power and low cost would be the driving factors.

I have found some stuff with google and am reading it now.
I looked at kodak and Micron web sites, but they dont have pricing or
avalibility on their sensors so other than looking at data sheets they
were not much help.

 

[Mike Treseler]

Bob wrote:

I have found some stuff with google and am reading it now.
I looked at kodak and Micron web sites, but they dont have pricing or
avalibility on their sensors so other than looking at data sheets they
were not much help.

http://www.google.com/search?q=image+sensor+reference+design+fpga

-- Mike Treseler

 

[Jim Granville]

Antti Lukats wrote:

Hi all

I am regret to inform you all that this the last time I either post or reply
to comp.arch.fpga newsgroup. This decision was triggered by an reply from an
Xilinx employee to one of my postings. If someone wants to look up that
posting then its around the sentence: "This may have been a mistake" - I do
understand that I may have understand the original intentions of that
posting and that sentence and the context wrong, but that doesnt make any
difference to my decision which is final.
snip

Whoa... Antti
- you must have a very thin skin, or give up easily (which I would not
have expected ) ?
Don't let any single person's posting bother you: it is important to
keep a view of the big picture, and keep your sense of humour intact.
Better to judge people by their long term nett contribution, and
whether they genuinely try to help, than by their etiquette.
Throwing the toys out of the cot has some dramatic appeal, but will
have little effect.

-jg

 

[Peter Alfke]

John,
your problem was caused by the fact that th FPGA CCLK pin (although the
driving output) is also the input from which the FPGA itself counts the
pulses. An extra glitch at this point, and FPGa and PROM get
out-of-synch.
Most designers investigate the CCLK line only at the PROM end, and miss
the glitch on the FPGA end.
I have explained this at least a hundred times, ever since the XC3000
days...
Peter Alfke, Xilinx Applications

 

[Jerome]

Hi,
Check http://www.xess.com/ho03000.html
Digital Camera Interface
"Bob" <bob@notrealmail.com> a écrit dans le message de
news:i5p3g154hbjm2msumgpsetip5gbnal44pn@4ax.com...

Hi does anybody have a design example of an image sensor connected to
programmable logic with HDL code?

I want to try this. I have not committed any hardware yet so a working
example would be a great starting point.

Mostly concerned with the physical connections and image sensor low
level interface code.

 

[Neo]

whats about this evolvable hardware?