EDK : FSL macros defined by Xilinx are wrong

Hello Paul and Ben,

In Quartus II 4.2 you will need a license for your encrypted core so
that you can compile it successfully with Incremental Compilation. This
restriction will be removed in Quartus II 6.0.

Alternatively in Quartus II 5.0 if you do not have a license one can
use Incremental Compilation and set all PARTITION_SOURCE settings to
POST_SYNTHESIS for the core.

Hope this helps,
Subroto Datta
Altera Corp.


Ben Twijnstra wrote:
Hi Paul,

I am currently using the evaluation open-core FIR compiler and NCO
compiler in the design and when I use these I am not able to perform
incremental synthesis. Does anyone know if you can perform incremental
synthesis with these cores once the cores are licensed? as synthesis steps
are taking upwards of 20-30 minutes at the moment and it is becoming quite
painful not having incremental systhesis.

You _should_ be OK with the licensed cores as well. The only difference
between the licensed and the unlicensed version is the Big Counter that
will shut the core down after an hour.

Better yet, in Quartus II 5.0 (out since June - why are you still on 4.2?)
you should also be able to do incremental P&R of your design.

This last bit may or may not cost you a bit of performance as the design
optimization is hindered by the fitting boundaries, but it should save you
loads of time between iterations.

Best regards,



Ben
Click to expand...
 
Actually I did use functions to perform the conversion. For some reason
it only complained when the function call was on the left hand side of
the port map.

Thanks for the help.
 
Genetic Algorithm pseudo code:

Problem: Solve 2x+1 = 7 (we know the answer is 3, but work with me)

Step #1 Generate a Random population of numbers:

Population = 1, 6, 8, 4

Step #2 Chose a fitness function. Ours will be Error = ABS(1-(2x +
1)/7)

Error(1) = ABS(1-(2x1+1/7)) = 0.57
Error(6) = ABS(1-(2x6+1/7)) = 0.86
Error(8) = ABS(1-(2x8+1/7)) = 1.43
Error(4) = ABS(1-(2x4+1/7)) = 0.29

The number with the smallest Error is closest to the answer. (Still
with me?)

Step #3 Repopulate your population based on your fitness function
results. This is the tough part to grasp. We need to normalize all of
the errors so we can get a repopulation percentage. This will help us
get the new population of numbers.

Take the total of the error 0.57 + 0.86 + 1.43 + 0.29 = 3.15

3.15/0.57 = 5.53
3.15/0.86 = 3.66
3.15/1.43 = 2.20
3.15/0.29 = 10.86

Take the total of the normalized error = 5.53 + 3.66 + 2.20 + 10.86
=22.25

Repopulation percentage for 1 = 5.53/22.25 = 25%
Repopulation percentage for 6 = 3.66/22.25 = 16%
Repopulation percentage for 8 = 2.20/22.25 = 10%
Repopulation percentage for 4 = 10.86/22.25 = 49 %

So now you repopulation your population, this means if you were
generating a random number from 0-100,
if the number was 0-24 the answer would be 1.
if the number was 25-41(25+16) the answer would be 6
if the number was 42-52(42+10) the answer would be 8
if the number was 53-100 the answer would be 4

So you can see the smaller the Error the greater chance the new
population will include that number

New Repopulation = 4, 4, 4, 1
So if you kept on repeating step 2 eventually you would have a
population of all 4's, but 4 is not the answer. So how do we get the
answer in our population if we don't have 3 in the initial
population?

The answer is step #4.

Step #4 mutation / crossover. In this example we'll just do mutation.
Just generate a random number and replace it in the population.

New population after mutation 4, 4, 4, 9

Step #5 repeat steps 2 - 4 until total Error is acceptable. In this
case until you get an Error of 0.


Kind of make sense???

I can give you sample code but it won't make sense unless you
understand the concept of evolutionary codes.

Eric
 
Unless you specify otherwise, ISE sets the I/O standard to ...

* LVCMOS25

* 12 mA output drive

* SLOW slew rate.

The output will follow whatever voltage level you have connected to the
respective VCCO input. In other words, even if ISE sets the I/O to
LVCMOS25 and you have VCCO = 3.3V, the output will drive 3.3V levels.

However, it's best to always set the I/O level appropriately so the
software can make sure that all your I/O assignments end up in the
proper I/O banks.
 
JD,

1. No you will not damage the FPGA with the core unpowered. However,
remember that there are intrinsic diodes from IO pins to Vcco, and to
ground. So if you connect Vcco to ground, and then connect all the IOs
to another operating chip, you will have a diode to ground forward
biased on every IO pin, probably blowing out the driving device, unless
it is tough enough to handle it, Often the FPGA is accused of damaging
the driver, as the FGPA will tolerate up to 200 mA sink or source for
weeks without damage (same as shorting one of our pins to ground or
Vcco, and leaving it there).

2. If the Vcco is just coming from a regulator or power supply, 99.99%
of all such supplies are open, until powered. Thus the diodes will
power ON the Vcco. That is harmless. The IOs power ON tristate, and
then wait for the core and aux supplies to come up before configuring.
Before, during, and immediately after configuring, all IO is tristate.
Right up until DONE goes high, and then your design decides what to do
with the IOs (they can stay tristate until your design sees a command
on a bus, etc.).

Austin
 
On Tue, 09 Aug 2005 19:16:32 -0500,
jeff.holley@latticesemi-dot-com.no-spam.invalid (jholley) wrote:

Javier Castillowrote:
Hello,

I am working on cryptographic application over VirtexII FPGAs. I
need to store a simmetric key inside a reg of the FPGA, but I dont
want that someboy could read it analizyng the bitstream. The
bitstream
could not be encrypted. Has anybody experience about hide data
inside
a FPGA?. Anyone knows some papers about this topic?

Regards

Javier

Javier,

If you use the new Lattice XP devices, the need for an external PROM
is eliminated and read back can be disabled. They do this by having
the Flash internal. Just offering another way to "skin the cat".

Regards,
Jeff Holley
Lattice FAE
(yes, I work for Lattice)
Click to expand...
Hello,
Thank you for your answer. I am not familiar with those type of FPGAs
and I dont know the configuration mechanism. Is it possible to
on-the-field reprogram a FLASH based FPGA using a external
microprocessor connected to Internet as in Xilinx IRL scheme?

Best Regards

Javier Castillo
 
"Javier Castillo" <jcastillo@opensocdesign.com> schrieb im Newsbeitrag
news:0lrjf1hssrhj01m0f3e4miu6rd6a3l5b92@4ax.com...
On Tue, 09 Aug 2005 19:16:32 -0500,
jeff.holley@latticesemi-dot-com.no-spam.invalid (jholley) wrote:

Javier Castillowrote:
Hello,

I am working on cryptographic application over VirtexII FPGAs. I
need to store a simmetric key inside a reg of the FPGA, but I dont
want that someboy could read it analizyng the bitstream. The
bitstream
could not be encrypted. Has anybody experience about hide data
inside
a FPGA?. Anyone knows some papers about this topic?

Regards

Javier

Javier,

If you use the new Lattice XP devices, the need for an external PROM
is eliminated and read back can be disabled. They do this by having
the Flash internal. Just offering another way to "skin the cat".

Regards,
Jeff Holley
Lattice FAE
(yes, I work for Lattice)

Hello,
Thank you for your answer. I am not familiar with those type of FPGAs
and I dont know the configuration mechanism. Is it possible to
on-the-field reprogram a FLASH based FPGA using a external
microprocessor connected to Internet as in Xilinx IRL scheme?

Best Regards

Javier Castillo
Click to expand...
yes it is.

the Actel PA3 also allows non volatile secure keys for encrypted bitstream
(I thínk that is not possible for LatticeXP)

Antti
 
Your code looks pretty good.

To answer your first question: If your answer is found in the first
population you just got lucky and you're done! Your correct in the
way you check for if the Error == 0 you stop, or the normalized value
would be infinite.

I have had similar issues with the answer diverging on some iterations.
What you need to do is have a fixed number of iterations like 100, That
way it won't ever be in an infinite loop. Another thing to try would be
use a larger population 6 is pretty small.

Another thing to do is keep track of you populations total error, if it
is not going down, maybe introduce more mutations. There are a bunch of
ways to try and get your population to evolve into the answer faster.

Since your know in this particular problem ax + b can not be greater
than c, you can use this to evaluate each random number in your
population. If you number violates this property, then just throw out
that number and get a new random number. This is kind of cheating,
since the repopulating should naturally weed out these answers. One
other option would be to give numbers that violate the ax+b = c a very
large Error, that way they just won't get repopulated.

One other thing to check is make sure you repopulation function is
running correctly. It is very easy to make a mistake in that function.

Good Luck

Eric
 
Another thing to try is make your fitness function non-linear.

Error = (1-(ax+b)/c)^4

This will make the Error huge on values that are far away from the
answer.

Eric
 
Gabor wrote:
Browsing the Xilinx website documentation I seem to get
no data sheets, user guides, or package drawings. Just:

Sorry...
Technical difficulties with the Xilinx.com web site have been solved.
If you are continuing to have difficulty accessing Xilinx.com, you may
need to exit your browser software and restart it. Please accept our
apologies for any difficulties you have experienced.

I tried Netscape 7.2 and Internet Explorer 6.0 (restarted twice)
with the same results...
Click to expand...
Never mind... Everything seems to be back now...
 
Austin,

Thanks for your reply. I am Jaemin.
Actually, I am not a student and don't want to develop it for an
exercise. :) Today, I tried to contact a Xilinx, but I donot have a
reponse yet. I would like to communicate with you for this thing by
email.

Thanks.
 
sarath schrieb:
Hi all,
Can any one tell me what is RAPID PROTOTYPING and how will this
technology help us in faster designing of products in FPGA.
Can you please tell me some source where I can get basics of RAPID
PROTOTYPING.
Thanks in Advance,
Sarath

Hi Sarath,
Click to expand...
just think a moment: What can be more rapid(faster) than downloading
your generated bitstream into silicon?

There is no Rapid Prototyping technology for FPGAs, because FPGAs
themselves are a rapid prototyping technology. Either to reduce the time
to market (FPGA runs -> sell device immediately) or to test functional
parts of a large ASIC design. In the second case you replace your ASIC
with a number of FPGAs and connect this "breadboard" to the rest of your
device (e.g Input and Output stuff). So you can actually work with the
whole device without having the real ASIC (which takes time and lots of
money to produce).

have a nice synthesis

Eilert
 
Dear Dave,
why not use a FPGA or a CPLD instead of an ASIC?
the Spartan3 and coolrunner (from Xilinx) for example seems reasonable
cheep.
The advantage using FPGA are:
1. reduced risk (if you do a mistake you can fix it even after the
production and distribution)
2. the costs in the design are lower (much lower)
3. the time to market is shorter

If the application is so straight forward maybe a CPLD like coolrunner
is enougth.
Also another advantage iss that now you can download all the SW you
need to program and simulate the CPLD and many FPGA from the Xilinx
Website for free and in my experience the tool ISE7.1 is now very very
stable.

Regards,
Francesco
 
Stefan,

DLL with clock mirroring would eliminate a skew between the clocks, but if I
understand you correctly, you are facing not a simple issue, especially
because you have 100 MHz and you want to use RF connection as a link. That
is, you have to embed certain information in the outgoing data, such as the
information about your local clock.

The common way to do this is to run, for example, 50-bit wide counter with
100 MHz clock in one end and transfer the value of the counter through the
data to another end. In the another end, there is the same counter and this
value is compared with the one embedded in the data traffic. The difference
between the two gives you an estimation about the difference between the two
clocks.

The rest depends on the device that you are using for clock generation and
its crystal pullability or frequency range that you can use.
If your clock would have been much slower, there is a way to do this using
very high-speed clock & phase shift technique.

If you could give a few more details..........

Hope this helps.
Vladislav


"Stefan" <holzi_stefan@hotmaildotcom.nospam> wrote in message
news:ddfm7g$fuf$1@wsc10.lrz-muenchen.de...
Hello,

does anybody know about clock accuracy - I need a very stable clock to
synchronize 2 devices via a RF connection. They must exactly have the same
clock, at this time I'm using a 100 MHz clock generator and a Spartan-3
fpga. But for my intended purpose it's not accurate enough. That means, on
a
scope my generated data bursts of each device with a interval of 3 us are
"running away" (that ones those aren't triggered). The 3 us intervals
differ
perhaps in half a ns or something.
Is there a practicable solution for such a problem? Does a DLL with clock
mirroring eliminate the problem?

Thanks in advance,

Stefan
Click to expand...
 
Hello Vladislav,

the problem is that I cannot transfer data via my RF link. (in the end this
is the aim...) I just transmit bursts of a 200 Mbit signal with a interval
of 3 us. These bursts contain data for a spread spectrum calculation, and
are only used with a analog correlator. To transmit data, I invert the bits
from this burst and after that on the correlator the output is -1 (instead
of 1 before).
And for this purpose, I have to synchronize these 2 bursts. I just tried to
use a DCM for clock generation, with no effect.
Really annoying... I got so far in this project and now this problem...

Any suggestions?

Regards, Stefan





"Vladislav Muravin" <muravinv@advantech.ca> schrieb im Newsbeitrag
news:8wJKe.8472$yH2.405404@news20.bellglobal.com...
Stefan,

DLL with clock mirroring would eliminate a skew between the clocks, but if
I
understand you correctly, you are facing not a simple issue, especially
because you have 100 MHz and you want to use RF connection as a link. That
is, you have to embed certain information in the outgoing data, such as
the
information about your local clock.

The common way to do this is to run, for example, 50-bit wide counter with
100 MHz clock in one end and transfer the value of the counter through the
data to another end. In the another end, there is the same counter and
this
value is compared with the one embedded in the data traffic. The
difference
between the two gives you an estimation about the difference between the
two
clocks.

The rest depends on the device that you are using for clock generation and
its crystal pullability or frequency range that you can use.
If your clock would have been much slower, there is a way to do this using
very high-speed clock & phase shift technique.

If you could give a few more details..........

Hope this helps.
Vladislav


"Stefan" <holzi_stefan@hotmaildotcom.nospam> wrote in message
news:ddfm7g$fuf$1@wsc10.lrz-muenchen.de...
Hello,

does anybody know about clock accuracy - I need a very stable clock to
synchronize 2 devices via a RF connection. They must exactly have the
same
clock, at this time I'm using a 100 MHz clock generator and a Spartan-3
fpga. But for my intended purpose it's not accurate enough. That means,
on
a
scope my generated data bursts of each device with a interval of 3 us
are
"running away" (that ones those aren't triggered). The 3 us intervals
differ
perhaps in half a ns or something.
Is there a practicable solution for such a problem? Does a DLL with
clock
mirroring eliminate the problem?

Thanks in advance,

Stefan
Click to expand...
 
Hi Eric
You can download the .exe file fom the following link:
http://rapidshare.de/files/3899362/EquationSolve.exe.html
I have limited the iterations to 1000 , so that it can solve equations
like 13x + 4 = 615.
It does it successfully.
Once agains thanks
Ankit
 
ravindra28d@rediffmail-dot-com.no-spam.invalid (ravindra kalla) writes:

hi,

i made a architecture,in which i want to run 18 proccessing elements
parrallely.Each processing element is connect with one memory
module.every memory module should store 256 bytes.Is it possible to
implement it in XILINX.If yes , how can i do so.Please help.


What is the maximum size i can store in memory of XILINX.
Click to expand...
You'd be better off on comp.arch.fpga - I've corssposted there and set
the followup there.

The answer to your questions depends on whch of Xilinx's many chips
you are going to use. You can do what you want with 9 Virtex-II
architecture BlockRAMs (assuming each element only needs a single port
access). There's plenty of space in each BRAM (each can hold 2048
bytes), and there are two ports on each BRAM. This will fit in even a
smallish Spartan-3 device. Check the data sheets for precise numbers
of BRAMs.

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt
 
Stefan wrote:
Hello,

does anybody know about clock accuracy - I need a very stable clock to
synchronize 2 devices via a RF connection. They must exactly have the same
clock, at this time I'm using a 100 MHz clock generator and a Spartan-3
fpga. But for my intended purpose it's not accurate enough. That means, on a
scope my generated data bursts of each device with a interval of 3 us are
"running away" (that ones those aren't triggered). The 3 us intervals differ
perhaps in half a ns or something.
Is there a practicable solution for such a problem? Does a DLL with clock
mirroring eliminate the problem?
Click to expand...
I'm aware this is not an analog forum... Squaring the
signal would give 200MHz. You could phaselock your
squared oscillator to the incoming stream.

Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net
 
"dave94024" <david.pariseau@sbcglobal.net> schrieb im Newsbeitrag
news:1123887528.001958.38830@z14g2000cwz.googlegroups.com...
Oh, forgot to mention. That's peak power. We need to be in the tens
of nanoamps during sleep mode which is the bulk of the time.

Dave.
Click to expand...
try contacting

http://www.emmicroelectronic.com

I bet they will do the job for you at your quantities

you can also try melexis, but I bet EM is better choice

Antti
BTW, thank you for your posting, thanks to it I found that EM is now also
offering SO-8 packaged MCU's that new and I did not know that before.
 
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