need a cheap student edition FPGA

[Kevin Neilson]

"John Vinyard" <jvinyard@stanford.edu> wrote in message
news:bfp8ks$q1q$1@news.Stanford.EDU...

I have a memory model in verilog made with an array of registers. I'm
trying to load data into it from a file in simulation, specifically using
MTI's Modelsim 5.7 SE. Trial and error with the $readmemh command is not
working. Any help you could give would be greatly appreciated.

reg [Data_Width-1:0] memory[65535:0];

Right now, I would settle for some way to execute a script from a file,
something like:

memory[0] = 36'hfeedfacea;
memory[1]...

Thanks in advance!

- John

I've used $readmemh with Modelsim with great success. What kind of problems

are you having? Do you get any warnings?
-Kevin

 

[Jim Wu]

"John Vinyard" <jvinyard@stanford.edu> wrote in message
news:bfp8ks$q1q$1@news.Stanford.EDU...

I have a memory model in verilog made with an array of registers. I'm
trying to load data into it from a file in simulation, specifically using
MTI's Modelsim 5.7 SE. Trial and error with the $readmemh command is not
working. Any help you could give would be greatly appreciated.

reg [Data_Width-1:0] memory[65535:0];

Right now, I would settle for some way to execute a script from a file,
something like:

memory[0] = 36'hfeedfacea;
memory[1]...

The data file has to be in the format that readmemh understands if you want
to use the function.

@addr_in_hex data_in_hex

The address part is optional

Jim
jimwu88NOOOSPAM@yahoo.com

 

[Richard Iachetta]

In article <d7b3726c.0307232359.439c31be@posting.google.com>,
yupeng_@hotmail.com says...

Hi,
I'm reading the Synopsys documentations. There are two documents.
One is HDL Compiler for Verilog Reference Manual, the other is HDL
Compiler (Presto Verilog) Reference Manual. Can somebody tell me
what's the difference between them?
Best wishes,
Peng

Synopsys' old verilog reader / synthesizer is the HDL compiler. Presto
is their newer (more supported) verilog reader / synthesizer. The main
difference between the two is that they have different bugs.

--
Rich Iachetta
I do not speak for IBM

 

[Steven Sharp]

"John Vinyard" <jvinyard@stanford.edu> wrote in message news:<bfp8ks$q1q$1@news.Stanford.EDU>...

I have a memory model in verilog made with an array of registers. I'm
trying to load data into it from a file in simulation, specifically using
MTI's Modelsim 5.7 SE. Trial and error with the $readmemh command is not
working. Any help you could give would be greatly appreciated.

I'm not clear whether $readmemh is not working in Modelsim (which seems
unlikely), or whether you just don't have documentation for how to use it.

The syntax for the call is

$readmemh("filename", memory_name);

If you don't want to start at the lowest address and load upward from
there, you can provide an additional optional starting address argument.
You can also provide a finish address argument after that. This is
useful for getting a warning if the file failed to specify all the
elements you expected. It also allows loading in descending address
order if desired.

The syntax for the text file is hexadecimal numbers (or binary for
$readmemb), separated by white space and/or Verilog comments. The
numbers should not have a length or base format specified (which
might be your problem). So, for example, it might contain

feedfacea
deadbeef0
012345678

You can also put explicit addresses into the data file, in case
you want to load specific locations in the memory without having
to specify the contents of the locations between them. This is
done with an entry of the form @1ffa (@ followed by a hex address).
Subsequent data entries will be loaded starting at that address.

 

[Rajesh Bawankule]

The correct syntax is
reg [Data_Width-1:0] my_memory[0:whatever];

memory width and depth numbers have different orders.
When you specify depth the first one is the lower number and then
the higher.

Hope this helps.
Rajesh Bawankule
(Verilog FAQ: http://www.parmita.com/verilogfaq/ )

"John Vinyard" <jvinyard@stanford.edu> wrote in message news:<bfp8ks$q1q$1@news.Stanford.EDU>...

I have a memory model in verilog made with an array of registers. I'm
trying to load data into it from a file in simulation, specifically using
MTI's Modelsim 5.7 SE. Trial and error with the $readmemh command is not
working. Any help you could give would be greatly appreciated.

reg [Data_Width-1:0] memory[65535:0];

Right now, I would settle for some way to execute a script from a file,
something like:

memory[0] = 36'hfeedfacea;
memory[1]...

Thanks in advance!

- John

 

[Avrum]

Most of the wave viewers I have worked with will not allow you to probe a
memory. The only way I have found to work around this is to put some "test"
structures in the code.

wire [3:0] myram_0, myram_1, myram_2,....;

assign myram_0 = myram[0];
assign myram_1 = myram[1];
....

then you can probe myram_0, myram_1, etc...

Obviously, this doesn't work for every location in an arbitrarily large
RAM - but for 16 elements, its not so bad. The definition and assignments to
myram_0, myram_1 are harmless to the rest of the simulation, and if you want
to be paranoid, you can wrap them in

`ifdef DEBUG_MYRAM
`endif

and define the variable only when you want to probe the RAM (add
+define+DEBUG_MYRAM) to the command line for you simulation), or you can put
them in translate_off/translate_on statements.

Avrum

"pradeep" <pradeepg@vlsi1.sastra.edu> wrote in message
news:962c2d3.0307250253.51288934@posting.google.com...

hi,

in my coding i have used memory declaration

reg [3:0] myram[15:0],

during simulation(ncsim, signalscan waveform) i am not able to add
this memory to the waveform viewer,

is there any other way to view the content of the memory

and i also face the same problem with modelsim

with regards
G.Pradeep.

 

[Stephen Williams]

Avrum wrote:

Don't confuse "legal" with "synthesizable".

I know the difference between legal syntax, simulatable constructs
and synthesizeable constructs thankyouverymuch. I'm a compiler writer,
and I was hoping some of the other compiler "geeks" that lurk these
parts would take a stab at this. The standard certainly doesn't.

assign (pull0, pull1) q_int = q_int;

The weak feedback drivers are then overridden by a stronger driver when the
latch enable is enabled (which would be the bufif1).

An implicit driver (bufz in the case of Icarus Verilog) would do
that job. In those terms, this almost makes sense. These sorts
of things are the kind of headaches that really freak out compiler
writers. Users are better at finding the dark corners of a tool
then the most random of monkeys;-)

For reference, a "better" way of describing this module

module dont_shoot_me (Q,D,G)
output Q;
input D,G;
reg Q;

always @(G or D)
begin
if (G)
Q <= D;
end
endmodule

This is certainly better style. Anybody following this thread should
always use this latter form for latches. The previous construct was
from a bug report. But it doesn't matter if it's weird or even stupid.
If it has well defined behavior, I have to get it right.

--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."

 

[Steven Sharp]

Stephen Williams <spamtrap@icarus.com> wrote in message news:<bfqa8l$buk$1@sun-news.laserlink.net>...

Notice the continuous assign of Q_int back to itself. The original
reporter claimed that this sort of thing is legal.

Sure, why wouldn't it be?

but it sure looks weird. What, for example, do the big money
tools do with this?

We do what the Verilog source says to do: We put in a continuous
assignment which reads the value of Q_int and drives it onto its
output (which is Q_int) with the specified strength. If you want
to talk internals, it reads the final resolved value of Q_int and
drive it onto its output (which is one of the drivers that
contributes to the resolved value of Q_int) with the specified
strength. This is just what you should expect: all readers read
the final resolved value, and all drivers drive their individual
contribution to the final resolved value. That doesn't change
just because one continuous assignment is both a reader and a
driver of the same net.

It is certainly legal, and shouldn't even require any special
handling. It is even potentially useful.

I have never seen this done with a continuous assignment. However,
I have seen it done with buf gates with weak strength or the
equivalent built with two cascaded inverters built with rmos
switches. Apparently this is a common way of implementing
a transparent latch in CMOS. When the bufif isn't driving,
the weak buffer provides the feedback loop to hold the value.
When the bufif is driving, it is strong enough to override
the feedback value and put a new value into the feedback
loop.

 

[Stephen Williams]

Steven Sharp wrote:

Stephen Williams <spamtrap@icarus.com> wrote in message news:<bfqa8l$buk$1@sun-news.laserlink.net>...

Notice the continuous assign of Q_int back to itself. The original
reporter claimed that this sort of thing is legal.

Sure, why wouldn't it be?

but it sure looks weird. What, for example, do the big money
tools do with this?

We do what the Verilog source says to do: We put in a continuous
assignment which reads the value of Q_int and drives it onto its
output (which is Q_int) with the specified strength. If you want
to talk internals, it reads the final resolved value of Q_int and
drive it onto its output (which is one of the drivers that
contributes to the resolved value of Q_int) with the specified
strength.

OK, you're taunting me:-(

But it finally got through my thick skull. Icarus Verilog tries
to elide useless buffers and expressions when it can, and may have
gotten carried away here.

--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."

 

[Ajeetha Kumari]

Hi Pradeep,
Within Modelsim you can view memory as waveform, it doesn't get
added by default with add wave -r * command, but instead if you
specify:

add wave /tb/dut/mem

it works. You could also browse through your Structure -> Signals ->
Add wave.

Let me know if that works.

Good Luck,
Ajeetha
http://www.noveldv.com

pradeepg@vlsi1.sastra.edu (pradeep) wrote in message news:<962c2d3.0307250253.51288934@posting.google.com>...

hi,

in my coding i have used memory declaration

reg [3:0] myram[15:0],

during simulation(ncsim, signalscan waveform) i am not able to add
this memory to the waveform viewer,

is there any other way to view the content of the memory

and i also face the same problem with modelsim

with regards
G.Pradeep.

 

[Uma Polisetti]

The negative setup and hold times are an issue with smaller
geometries (especially 0.13um technolog) and the mux-D flops.
It is going to be an even bigger issue with 90nm :-(

The next issue you might face is, where the "tools" not able
to converge when the setuphold "violation" region for rise
and fall edges do not overlap. In that case, typical reaction
from the tool is to "zero out" the negative setup/hold time.
I think most of commercial tools have magic switches
to "extend" the violation region. Unfortunately, this has
penalty on simulation runtimes.

I am sorry that my explanation above "might not make sense" to
most of you. But if you have the simulator manuals, search for
"$setuphold" and "handling negative timing checks".

I can't give more details because it is Cadence's information
under NDA, but later versions of Cadence NC Verilog does very
good job on handling the rise and fall "Data" edges and different
negative setup/hold times on them.





Robert Szczygiel wrote:

pks wrote:
Thank you Robert and Steven for your answers. Now I understand your
solutions.
I will try to use it. The only one problem is that I have different
hold times for rising/falling edge of data/clock_enable signal. I'll
try so manage this situation.

As you may have noticed in the example I have given you there were two
commands, first for the check on falling edge of the data, the second
for the rising edge.

$setuphold (posedge CK,negedge D, 180.0, -1.9,notifier,,,dCK,dD);
$setuphold (posedge CK,posedge D, 218.0, -27.9,notifier,,,dCK,dD);

Note that this two commands use the same dCK and dD wires.

Robert
--
** - Why a bike cannot stand up by itself?
** - Because it is two-tyred!
-- http://2510074626/~szczygie --

--
Agilent Technologies Confidential

Uma Polisetti
Agilent Technologies, Inc
541-738-3335 Tel
541-738-3145 Fax

 

[VhdlCohen]

I'm trying to use Verilog-2001 style module port declarations and have
a parameter defined as well. See my example:


module my_module (
output [WIDTH-1:0] my_output,
input [WIDTH-1:0] my_input
)

parameter WIDTH = 1;

assign my_output = my_input;

endmodule


I can't figure out where to put the parameter declaration to get rid
of the syntax errors that are being reported (using VCS 7.0). Can
parameters be declared when defining ports in this manner?

Thanks,
Mark

Here's how:

module my_module
#(parameter WIDTH = 8) // 0 -> full board, 1 -> 1 mem unit
(
output [WIDTH-1:0] my_output,
input [WIDTH-1:0] my_input
);

assign my_output = my_input;

endmodule // my_module

// For instantiation:
my_module
#(.WIDTH (8))
my_module1
( // output
.my_output (data_out[7:0]),
.my_input (data_in[7:0])
);
----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Using PSL/SUGAR with Verilog and VHDL
Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------

 

[John_H]

From page 7 of the "Verilog HDL Quick Reference Guide" from
www.sutherland-hdl.com, one of the valid declaration forms may be as
follows:

module my_module #( parameter WIDTH = 1 )
( output [WIDTH-1:0] my_output,
input [WIDTH-1:0] my_input
);

assign my_output = my_input;

endmodule

This appears to work fine with the Synplify implementation of Verilog-2001.


"Mark Lancaster" <mark.lancaster@motorola.com> wrote in message
news:3F268E73.F7C73A4D@motorola.com...

I'm trying to use Verilog-2001 style module port declarations and have
a parameter defined as well. See my example:


module my_module (
output [WIDTH-1:0] my_output,
input [WIDTH-1:0] my_input
)

parameter WIDTH = 1;

assign my_output = my_input;

endmodule


I can't figure out where to put the parameter declaration to get rid
of the syntax errors that are being reported (using VCS 7.0). Can
parameters be declared when defining ports in this manner?

Thanks,
Mark

 

[Stephen Williams]

Joe wrote:

Any news about support of EDA tools running on AMD-64 platform?
(Especially backend stuffs which likely to take up more memory).
I only heard that Cadence and VCS (Synopsys) will support it.
Any more? Is it available now or should I wait? Any performance
figures?

Icarus Verilog supports AMD-64.

Also, you can generally run ix86 Linux binaries on Linux/x86-64
without a hitch (and without a performance penalty.)

My 1.8GHz Opteron is nearly twice as fast (Icarus Verilog) as
the 1.8GHz Athon, for the same price. I have seen huge simulations
that take more then 4Gig run to completion. Very nice.

--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."

 

[Larry Doolittle]

In article <bgc7rr$fj3$1$830fa78d@news.demon.co.uk>, Joe wrote:

Not really VHDL/Verilog question but I guess lots of people
here would be interested.

Any news about support of EDA tools running on AMD-64 platform?
(Especially backend stuffs which likely to take up more memory).

Icarus Verilog has supported 64-bit platforms for a long time now.
Linux Journal just reviewed it for AMD-64/Linux. It runs roughly
twice as fast as the fastest Athlon, and breaks the 4 Gig limit
for a design memory footprint easily.

I'm not sure how well AMD-64 does on a throughput/dollar metric,
but if you need more than 4 Gig per-process virtual memory, your
other choices get very expensive very fast.

- Larry

 

[David Jones]

In article <bgcifd$op$1@sun-news.laserlink.net>,
Stephen Williams <spamtrap@icarus.com> wrote:

My 1.8GHz Opteron is nearly twice as fast (Icarus Verilog) as
the 1.8GHz Athon, for the same price. I have seen huge simulations
that take more then 4Gig run to completion. Very nice.

Is this due to Icarus exploting the 64-bit architecture (really, just
the increased registers - nothing else will cut the runtime) or does
the Opteron run all 32-bit code twice as fast as well?

I'd like to get my hands on an Opteron but they ain't selling 'em in
the local stores just yet.

 

[Stephen Williams]

David Jones wrote:

In article <bgcifd$op$1@sun-news.laserlink.net>,
Stephen Williams <spamtrap@icarus.com> wrote:

My 1.8GHz Opteron is nearly twice as fast (Icarus Verilog) as
the 1.8GHz Athon, for the same price. I have seen huge simulations
that take more then 4Gig run to completion. Very nice.


Is this due to Icarus exploting the 64-bit architecture (really, just
the increased registers - nothing else will cut the runtime) or does
the Opteron run all 32-bit code twice as fast as well?

There is some, but not much in Icarus Verilog that takes advantage
of 64bit words, so I have no reason to doubt that I would get the
same if I ran as a 32bit program. Can't say I bothered with the
experiment.

Of course, the 64bit really pays when your designs are so big
the simulations take lots of address space.

I'd like to get my hands on an Opteron but they ain't selling 'em in
the local stores just yet.

Got mine here: www.polywell.com
It's not obvious from their web page, but you can get them in
workstation clothing. Mine cost on the order of $5,000 w/o monitor.

--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."

 

[Ynonymous]

"Joe" <xxxxx@yyyyy.com> wrote in message
news:bgc7rr$fj3$1$830fa78d@news.demon.co.uk...

Hi all,

Not really VHDL/Verilog question but I guess lots of people
here would be interested.

Any news about support of EDA tools running on AMD-64 platform?
(Especially backend stuffs which likely to take up more memory).
I only heard that Cadence and VCS (Synopsys) will support it.
Any more? Is it available now or should I wait? Any performance
figures?

Well, Mentor announced an x86-64 version of Modeltech about
the same time AMD officially announced the Opteron platform.
Problem is, can't seem to download it from the model.com main site!

 

[Prasanna]

"cfk" <cfk_alter_ego@pacbell.net> wrote in message news:<52INa.67$o66.10@newssvr16.news.prodigy.com>...

"Rajesh Bawa" <Rajesh.Bawa@free.fr> wrote in message
news:3f068a10$0$12438$626a54ce@news.free.fr...
I pesonnally think that hardware desining can be outsourced (with
correct spec). Once designed there is a lot of responsibility on people
to ensure that the designed hardwrea meets the specification.

any commnts most welcomed.

Well, the key is communication. It is sometimes difficult to get a consensus
from the next office, much less from a different county, or <uggh> a
different country.

Writing specifications that are meaningful, understandable, unambiguous and
testable will make any project go more smoothly. And that really doesnt have
much to do with whether or not the team is local or not.

However, to be the devils advocate, it is a whole lot easier if it is a
local stroll to the next office or building instead of the next continent.

Charles

My view here is purely technical and not political...

I have found when designs are fed to totally unknown team (contract
team), they ask questions that sometimes you wonder why you ever did a
design like that.
For eg: One of the legacy designs that needed verification was given
to another company whose team was excellent. They asked, "why do you
need 2 embedded processors in there. Cant you modify the design and
utilise one instead of two and eliminate all those complex bridges".
The idea was good and was implemented on next version. I have seen
some architectures are basically flawed and you get to know only when
you present such a design as a black box to good verification
engineers. One of the designs actually could not do continous back to
back packets and had a buffer overflow problem bcoz' of that. This was
found during design review presentation during handover. Anyways the
advantage I mention here is, "your verification team in your company
may not be looking at the design from the angle other company looks at
your design".

Good luck...

 

[TorbaX]

Jim Wu wrote:

);
for (i=1;i<=4;i=i+1) $fdisplay(dstfile,"%c",hdr_size);



$fwrite should be used if you don't want the new line character at the end.

Jim Wu
jimwu88NOOOOSPAM@yahoo.com


Ok in my example I write this new version of code:

for (i=1;i<=4;i=i+1) $fwrite(dstfile,magic,,1);

the problem of newline char is resolved. thanks.
BUT

for example, if I write:

reg [7:0] foo_var [1:4]; //4 locations of 8 bit value -> 8*4 = 32bit
sizeof "foo_var"

and I open an input file with
srcfile = $fopen("my_file.bin","rb");
dstfile = $fopen("my_file.bin","wb");

the foo_var charge the bytes with $fread task.

$fread(srcfile,foo_var);

the dump byte 1..4 of new value of foo_var is: 00 00 00 1C
//!!! 4 bytes in output file

I try to write any element of foo_var to an output file, BUT the
effective value written is not correspondent to original file!!!

for (i=1;i<=4;i=i+1) $fwrite(dstfile,foo_var,,1);

the NEW dump byte 1..4 of foo_var is : 20 20 30 20 20 30 20 20 30 20 32
38.(hex value)
output file are 12bytes of size!!
!?!?!?!?!
I don't know which error I wrote on verilog code.