need a cheap student edition FPGA

[Jonathan Bromley]

On Thu, 26 Jun 2003 16:53:12 -0700, Tze Yi Yeoh
<tzeyi.yeoh@xilinx.com> wrote:

Does anyone out there know if Verilog supports operator overloading like
in VHDL? If so, can someone point me to an example?

No, it doesn't.

SystemVerilog 3.1 will offer classes, but AFAIK still no operator
overloading.

Jonathan Bromley

 

[Ashraf]

asherm@asherm.com (Asher C. Martin) wrote in message news:<3e30b793.0306260956.206290ef@posting.google.com>...

cuteworm@wildmail.com (walter) wrote in message news:<36659e9e.0306180744.1756095@posting.google.com>...
Hi,

Is there is any Verilog model for PLL?
I tried the google search.
But they are not really related to what I need.

Hi,

Altera has a FREE PLL model available when you install the Quaruts II
Web Edition Software.

https://www.altera.com/support/software/download/altera_design/quartus_we/dnl-quartus_we.jsp?xy=qw1_wdl

Go to the /quartus/eda/sim_lib/ dir and type "grep pll *.v"

Take care,
Hi,

There is an article which highlights the approach when I developed this model
while I was working for a Silicon vendor. I can't share you all the details
(company proprietary information), but you can pick up the idea from the
IEEE CICC proceedings 1997 Page 15.6.1-15.6.4.
This is full functional PLL model which mimics the functionality of Lockup
sequence, frequency synthesis and selection of loop filter parameters and their
affect on lock time etc etc.

Good Luck,

Ashraf
> >Asher<

 

[DSLuser]

WJ wrote:

I am tring to do back-annotation by Verilog, and encounter a problem
as following:
since the instance name is too long, up to 25 characters for a single
instance name, PrimeTime generated the sdf base on the those long
instance names, but looks Verilog-XL can take only up to 24 charaters
as instance names, the last charater is automatically truncted in this
case. I dumped the waveform to confirm this Verilog-XL instance name
trunction, and also double confirm this problem by modify the sdf
file.
Anybody know how to solve this problem? Is there any option in
Verilog-XL for taking long instance name? Thanks in advance!

I think Verilog-XL is nearing 'end-of-life' development status.
Although Cadence officially still provides support for the Verilog-XL
product, I don't think they are not updating it anymore. For example,
Verilog-XL supports very few IEEE 1364 Verilog-2001 syntax.

Since you can't change Verilog-XL's behavior, you have two choices:

1) use a different verilog simulator (Cadence NC-verilog,
Mentor Modeltech VSIM, Synopsys VCS are all good choices)
2) modify your netlist (like you did), to limit the length
of instance names. If you're really good with PERL, you
could handwrite a script to do something like this.

Finally, why are your instance names so long? Are you using
parameterized instances? If so, you may want to give your
RTL-synthesis 'hints' before elaboration. I think there is a
way to do this in Synopsys Design Compiler (if that's what you're
using.) You tell Design Compiler specific instances to build
(you tell it to build different versions of the parameterized
instance...you manually specify the parameter values.) Then,
when the parameterized instances are later used in other
modules, Design_Compiler automatically looks in its 'library',
and pulls your hand-specified version. I think this will
shorten the instance names, but I never tried it.

 

[Ajeetha Kumari]

Hi tze,
NO, as such Verilog doesn't have user defined data types and hence
I guess this was not thought about either. Can you elaborate more on
which scenario would you need this? Perhaps there is an alternate
solution (I remember reading something similar in Deepchip.com's
archive, but related to $finish and specific to VCS).

HTH,
Aji
http://www.noveldv.com

Tze Yi Yeoh <tzeyi.yeoh@xilinx.com> wrote in message news:<3EFB8768.B636CD0D@xilinx.com>...

Does anyone out there know if Verilog supports operator overloading like
in VHDL? If so, can someone point me to an example?

thanks!

tze

 

[Anil Dalwani]

I would recommend you to start reading the book by Samir Palnitkar.
That is the best I have seen for beginners.

-Anil


yupeng_@hotmail.com (Peng Yu) wrote in message news:<d7b3726c.0306281807.14b6400f@posting.google.com>...

Hi,
I'm studying verilog and Synopsys DC. There are a lot of materials
on the WEB. Could somebody introduce the best materials to a beginner?
Best wishes,
Peng

 

[Bebick]

Verilog Primer by Jayaram Baskar is a good book for beginners.

adalwani@binghamton.edu (Anil Dalwani) wrote in message news:<c4ecc514.0307020658.e58fa95@posting.google.com>...

I would recommend you to start reading the book by Samir Palnitkar.
That is the best I have seen for beginners.

-Anil


yupeng_@hotmail.com (Peng Yu) wrote in message news:<d7b3726c.0306281807.14b6400f@posting.google.com>...
Hi,
I'm studying verilog and Synopsys DC. There are a lot of materials
on the WEB. Could somebody introduce the best materials to a beginner?
Best wishes,
Peng

 

[Jon]

yupeng_@hotmail.com (Peng Yu) wrote in message news:<d7b3726c.0306281807.14b6400f@posting.google.com>...

Hi,
I'm studying verilog and Synopsys DC. There are a lot of materials
on the WEB. Could somebody introduce the best materials to a beginner?
Best wishes,
Peng

You might want to also try the books by bhasker they are decent for a
beginner. For Synopsys DC read the tutorial and the documentation
that's probably a good start. For an overview of DC + other synopsys
tools you can get the book called "Advanced Asic Chip Synthesis" it
gives you a basic flow of how to use DC and the other tools to
generate an asic.

jon

 

[Rajesh Bawa]

Hello,

I pesonnally think that hardware desining can be outsourced (with
correct spec). Once designed there is a lot of responsibility on people
to ensure that the designed hardwrea meets the specification.

any commnts most welcomed.

Rajesh

Morris Dovey wrote:

ben cohen wrote:

And in some cases, it is better that the verification team be an
automonous entity. I've done a bunch of reasearch on verification,
and there's good things about 'pure' verification environments. (And
frankly, most designers write terrible test benches! I'm sure Ben
will back me up on this one.


(I think I lost some attribution somewhere)

It would seem that autonomy is an almost necessary condition for
verification. All of my verification work has been done on (what was
intended to be) production silicon/boards; with nothing to guide me but
a product spec document. My job was, of course, to determine if the
implementation behavior matched the spec; and to communicate mismatching
behaviors to the client. Once a problem was detected I met with members
of the design team to discuss the problem. Sometimes it was a matter of
intending one thing but saying another in the spec, sometimes a
misunderstanding of the spec on my part, and sometimes it was a genuine
bug.

The designers seemed to be afflicted with an automatic denial response
("No bugs in /my/ design!") I can confirm that people with real genius
for logic design frequently display a real lack of talent for writing
test code - especially test code that really stresses their design. I
just love being told that my test programs are /too/ fast for the
hardware

On the other hand, I've been fortunate in working with designers who
were unbelievably cooperative and helpful. These qualities are major
cost reducers and time savers in the verification process.

Note that my niche has not been in hardware design; but is rather in
testing embedded [whatever]. If you'd like a glimpse into my most recent
such project, there's a thumbnail sketch at:
http://www/iedu.com/mrd/philips.txt

 

[Ajeetha Kumari]

Hi,
As far as I know you can use VHDL-AMS for analog digital simulation.
Please visit this website www.hamster.com and there you can get
evaluation version.

HTH,
Ajeetha

http://www.noveldv.com



"Riccardo" <riccardo@bronzini.org> wrote in message news:<be6150$1cm7$1@newsreader2.mclink.it>...

Hi to all,

someone could suggest me a PC tool able to do an Analog-Digital simulation?
Let me say a mixed HDL-PSpice sim?

Thanks

Riccardo

 

[Bob Perlman]

Hi -

On 03 Jul 2003 13:54:21 GMT, enrique.laserna@web.de wrote:

You guys should also look into Innoveda's Visual hdl (Now bought by
Mentor, I think). It translates State Machines, Flow Diagrams, FSM into
Verilog, vhdl and SystemC. All ready for synthesys.

Well, maybe. But I've felt for years that my chances of getting a
design to work are inversely proportional to the number of tools
between me and the target device.

Bob Perlman
Cambrian Design Works

 

[cfk]

"Rajesh Bawa" <Rajesh.Bawa@free.fr> wrote in message
news:3f068a10$0$12438$626a54ce@news.free.fr...

I pesonnally think that hardware desining can be outsourced (with
correct spec). Once designed there is a lot of responsibility on people
to ensure that the designed hardwrea meets the specification.

any commnts most welcomed.

Well, the key is communication. It is sometimes difficult to get a consensus

from the next office, much less from a different county, or <uggh> a
different country.

Writing specifications that are meaningful, understandable, unambiguous and
testable will make any project go more smoothly. And that really doesnt have
much to do with whether or not the team is local or not.

However, to be the devils advocate, it is a whole lot easier if it is a
local stroll to the next office or building instead of the next continent.

Charles

 

[Brian Drummond]

On 03 Jul 2003 13:54:21 GMT, enrique.laserna@web.de wrote:

You guys should also look into Innoveda's Visual hdl (Now bought by
Mentor, I think).
Hmmm, Mentor, who created Renoir (now HDL Designer). I suspect one of

these tools may not be supported much longer...

- Brian

 

[Sajan]

The transition to 000 might be due to a glitch.
The case statement used is not a full-case and the
state will not go to RESET unless u get a RST.
The way to avoid it is to use a default condition in the
case so that even if any undefined state is reached due to glitch ,
it can immediately transition to a known state (RESET) on the next clock.

default:
input_state = RESET;

I think this should help.


"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:<sd6Ja.624$jk1.61638848@newssvr15.news.prodigy.com>...

The FSM below has been waking-up in an illegal state and I can't figure out
why. This is in actual hardware (XC2V1000). I must be missing something
fundamental.

parameter RESET = 3'b001;
parameter CTL_HIGH = 3'b010;
parameter GO = 3'b100;

reg [2:0] input_state = RESET;

always @ (posedge CLK_IN) begin
if(RST_IN) begin
input_state <= RESET;
end
else
case (input_state) //synthesis parallel_case full_case
RESET: begin // Monitoring for control signal to go high
FIFO_WRITE_ENABLE <= 1'b0;
if(CONTROL_IN) input_state <= CTL_HIGH;
end

CTL_HIGH: begin // Now wait for it to go low
if(!CONTROL_IN) begin
FIFO_WRITE_ENABLE <= 1'b1;
input_state <= GO;
end
end

GO: begin // Stay here unless reset
FIFO_WRITE_ENABLE <= 1'b1;
input_state <= GO;
end
endcase
end

The FSM simply waits for a pulse to go high and then low again before
permanently enabling an external (to the module) FIFO to go. I know there
are other ways to do this ... but humor me here, I'm trying to figure out
why this is broken.

I use upper case variable names to denote module I/O. Lower case variables
are internal to a module.

For debugging purposes I brought out "input_state" to three pins on the
device. A scope clearly shows that sometimes this FSM will wake-up with
input_state = 3'b000. Can anyone tell me how this is possible? The problem
is particularly frustrating because it comes and goes as work is done in
other modules. Maybe some sort of placement/timing issue? The clock is
about 100MHz.

Thanks,

 

[Avrum]

What is it you are trying to do, prevent VCS from "re-compiling" or
maintaining two different versions of the source code.

If you are trying not to modify the source code, then you can use your
`ifdef, and change the behaviour of the simulation from the command line;
you define the USE_TRIREG_BUS macro from the command line by adding

+define+USE_TRIREG_BUS

to the command line when you compile the source code.

However, changing this macro (even from the command line), DOES result in an
effective change to the code (from the VCS compiler's point of view), and
hence will result in the recompilation of the code, and a new executable.

You can also probable model the behaviour of the trireg without an actual
trireg. The trireg is the equivalent to a keeper cell. If all the "other"
drivers of the net are strong drivers, then you can do something like this
(I haven't tested this...)

reg [15:0] fake_driver;

assign (weak1, weak0) my_bus = fake_driver;

initial fake_driver = 16'bzzzz_zzzz_zzzz_zzzz;

always @(my_bus)
fake_driver = my_bus;

I THINK this might work. Then you could modify this to be conditional

always @(my_bus or use_trireg_bus)
if (use_trireg_bus)
fake_driver=my_bus;
else
fake_driver = 16'bzzzz_zzzz_zzzz_zzzz; // to avoid startup problems...

(and use the testplusargs you described below)

Avrum

"Dale Bertrand" <dale_bertrand@yahoo.com> wrote in message
news:672495a6.0307070745.41e25c70@posting.google.com...

I need to model a bus in my system as a "trireg" or "wire" depending
on the test that is running.

The trireg bus models a capacitive bus that holds its previous value
when not driven.

My current solution is to use a `define to choose the type of bus:

`ifdef USE_TRIREG_BUS
trireg [15:0] my_bus;
`else
wire [15:0] my_bus;
`endif

Unfortunately, this solution requires me to compile multiple versions
of the simulator (using VCS7.0). I need to choose a trireg or wire
bus at runtime. The type of bus will not change during the
simulation. I would like to compile one simlator and pass a plusarg
(like +use_trireg_bus) instead of a `define to determine the type of
bus to use.

This is the best that I could come up with. Unfortunately, this
solution generates bus contflicts on my_bus.

reg use_trireg_bus;

initial begin
if ($test$plusargs("use_trireg_bus"))
use_trireg_bus = 1;
else
use_trireg_bus = 0;
end

wire [15:0] my_bus;
trireg [15:0] my_bus_stub;
tranif1 my_bus_trans[15:0] (my_bus_stub[15:0], my_bus[15:0],
use_trireg_bus);

Does anyone know how to implement this properly in Verilog?

- Dale

 

[Ajeetha Kumari]

Hi,
Typically UDPs are used in Cell library models and NOT for
synthesis.
In UDP all possible combinations of inputs,where the o/p produces a
known value must be explicitly specified. For other unspecified
inputs, the output is x. Z is not allowed in UDP. It is treated as x.
For more info. about UDP rules, refer some good book. (May be Samir
Panitkar).
In case, for unspecified values you have to include default state.
In order to treat x, z you have to use casex and casez.

HTH,
Ajeetha

http://www.noveldv.com




yupeng_@hotmail.com (Peng Yu) wrote in message news:<d7b3726c.0307111900.72f9f85f@posting.google.com>...

Hi,
Are UDP and case statement same for some combinational logic? What's
the difference between the following two implementation of MUX? Under
what condition should we use UDP? Under what condition should we use
case statement?
Peng

primitive prim_mux4to1 (DOUT, DIN3, DIN2, DIN1, DIN0, SEL1, SEL0);
output DOUT;
input DIN3, DIN2, DIN1, DIN0, SEL1, SEL0;

table
???0 00 : 0;
???1 00 : 1;
??0? 01 : 0;
??1? 01 : 1;
?0?? 10 : 0;
?1?? 10 : 1;
0??? 11 : 0;
1??? 11 : 1;
endtable
endprimitive

module mux16to1 (DIN, SEL, DOUT);
input [15:0] DIN;
input [3:0] SEL;
output DOUT;
reg DOUT;

always@(SEL or DIN)
begin: blk1
case (SEL) // synopsys infer_mux
4'b0000: DOUT <= DIN[0];
4'b0001: DOUT <= DIN[1];
4'b0010: DOUT <= DIN[2];
4'b0011: DOUT <= DIN[3];
4'b0100: DOUT <= DIN[4];
4'b0101: DOUT <= DIN[5];
4'b0110: DOUT <= DIN[6];
4'b0111: DOUT <= DIN[7];
4'b1000: DOUT <= DIN[8];
4'b1001: DOUT <= DIN[9];
4'b1010: DOUT <= DIN[10];
4'b1011: DOUT <= DIN[11];
4'b1100: DOUT <= DIN[12];
4'b1101: DOUT <= DIN[13];
4'b1110: DOUT <= DIN[14];
4'b1111: DOUT <= DIN[15];
endcase
end
endmodule

 

[Peter Mash]

Answer found:

It's because the schematic symbol generator doesn't support Verilog 2001

Regards

PETER MASH


"Peter Mash" <pwtm2@cam.ac.uk> wrote in message
news:bf3sug$2sa$1@pegasus.csx.cam.ac.uk...

Dear people,

I create a module, for example, a simple adder in Verilog. It synthesises
fine. I then create a schematic symbol from it, but the ".sym" file
contains
very little information, and when I place it in to a schematic module in
the
project, no symbol appears.

Has anybody else had the same problem? I am using the latest ISE (5.2 with
SP 3) as part of the WebPack.

Regards to all

PETE MASH

 

[Peter Mash]

Yes,
e.g.

module Adder(in1,in2,out);

input wire [7:0] in1;
input wire [7:0] in2;
output wire [8:0] out;

assign out = in1 + in2;


endmodule


"Steven Sharp" <sharp@cadence.com> wrote in message
news:3a8e124e.0307161605.344d52fb@posting.google.com...

"Peter Mash" <pwtm2@cam.ac.uk> wrote in message
news:<bf3up7$4a2$1@pegasus.csx.cam.ac.uk>...
Answer found:

It's because the schematic symbol generator doesn't support Verilog 2001

Out of curiosity, what Verilog-2001 feature were you using?

Since you said it was a simple module, I am guessing ANSI-C-style
module declarations.

 

[Andrew Paule]

Hi Srini:

I'd look on either systemc.org or opencores.org - systemc is only
really starting, and if you get one done, maybe drop it up there too.
Opencores is a group that's been around a while, and some of the other
people may have knowledge of this stuff.

Andrew

srini wrote:

Hi,

I am looking for SystemC IP cores for some video/SoC applications
(like MPEG4, mp3 decoder, etc.).

Is it possible to get such SystemC cores for free from somewhere?

thanks

-srini

 

[Andrew Paule]

ADS (agilent toolkit) can do this quite well - expensive though

Riccardo wrote:

Hi to all,

someone could suggest me a PC tool able to do an Analog-Digital simulation?
Let me say a mixed HDL-PSpice sim?

Thanks

Riccardo

 

[Mark Curry]

kevin arnold wrote:

Hello,
I would like to download the IEEE 1364.1 LRM that deals with the
synthesizable subset of
verilog. Can anyone in the group provide me with pointers from where i
can get this done?
Also any documents pertaining to the internals of the sis package from
berkeley would be of
great help. Thanks in advance for any help.

http://shop.ieee.org/store/default.asp?tabtype=stand

Type 1364 into the search box.

Regards,

Mark

--
Mark Curry
mcurry@ti.cat.com.invalid Remove the animal from the domain to reply.