need a cheap student edition FPGA

[Steven Sharp]

TorbaX <heroshimo@tiscali.it> wrote in message news:<bgu634$fbm$1@lacerta.tiscalinet.it>...

Where is the problem? Simply I view (with an hex editor) the characters
written to output file which don't correctly written... and after any
bytes is written "\n"(0x0A) char (but I write ONE char!!!!);

Are you using $fwrite or $fdisplay? $fdisplay will always put a newline
at the end of whatever it prints, because that is how it is defined to
work. If this is happening with $fwrite, then you are seeing a bug.

The reg variables are read correctly!!!!
but when I see the destination files, the characters are differents.
The char "0x00" for example is not possible to write to a output file..
I have read the Verilog IEEE 1364 specification, but I don't find the
related function to resolve the problem for writing all 256 characters
to file....

It is not surprising that a zero byte is not working. If the simulator's
I/O routines are written in C and are writing the output values into a
C string buffer before writing that out, then the zero byte will look
like an early end of the string, not something to be written out.

We had a similar problem with printing the zero byte with "%c" in
NC-Verilog, but we have fixed it. It was not trivial to do.

With the I/O extensions in Verilog-2001, users can now do very general
file I/O instead of just printing out messages to be read by humans. It
is reasonable to expect to be able to print out any byte value now, to
create arbitrary binary files. I would suggest reporting this to your
simulator vendor and asking them to fix it.

Note that the "%u" format descriptor writes raw binary data, and might
work even if "%c" does not. However, it writes data in units of 32 bits,
so it cannot write one byte.

 

[Steven Sharp]

TorbaX <heroshimo@tiscali.it> wrote in message news:<bgunua$mom$1@lacerta.tiscalinet.it>...

for (i=1;i<=4;i=i+1) $fwrite(dstfile,foo_var,,1);

the NEW dump byte 1..4 of foo_var is : 20 20 30 20 20 30 20 20 30 20 32
38.(hex value)
output file are 12bytes of size!!
!?!?!?!?!
I don't know which error I wrote on verilog code.

You need to read the documentation on these system tasks before
trying to use them. You are trying to use $fwrite like it was
the inverse of $fread, and would do a raw binary write. It isn't.
It is a formatted write like $display, just without the newline
at the end of the line.

Since you left off the format, it is assuming %d decimal format, and
writing out the string that represents the value in decimal. The
value it printed was the string " 0 0 0 28". It really should
have printed the constant 1 that you gave it as an argument also,
but perhaps your simulator has a bug when there is a null argument
to be printed.

 

[Eliot Franklin]

It seems that the ANSI C port definition can't handle when all the
parameters are defined in an include file. For example:

module mymod (mybus);
`include "def.v" // defines BUS_WIDTH
input [BUS_WIDTH:0] mybus;
....

You can't use the ANSI C ports, because the include file doesn't get
included until after the portlist.

This seems like a big limitation of ANSI C style ports.

Eliot


"John_H" <johnhandwork@mail.com> wrote in message news:<YFAVa.26$tC.3643@news-west.eli.net>...

From page 7 of the "Verilog HDL Quick Reference Guide" from
www.sutherland-hdl.com, one of the valid declaration forms may be as
follows:

module my_module #( parameter WIDTH = 1 )
( output [WIDTH-1:0] my_output,
input [WIDTH-1:0] my_input
);

assign my_output = my_input;

endmodule

This appears to work fine with the Synplify implementation of Verilog-2001.


"Mark Lancaster" <mark.lancaster@motorola.com> wrote in message
news:3F268E73.F7C73A4D@motorola.com...
I'm trying to use Verilog-2001 style module port declarations and have
a parameter defined as well. See my example:


module my_module (
output [WIDTH-1:0] my_output,
input [WIDTH-1:0] my_input
)

parameter WIDTH = 1;

assign my_output = my_input;

endmodule


I can't figure out where to put the parameter declaration to get rid
of the syntax errors that are being reported (using VCS 7.0). Can
parameters be declared when defining ports in this manner?

Thanks,
Mark

 

[VhdlCohen]

It seems that the ANSI C port definition can't handle when all the
parameters are defined in an include file. For example:

module mymod (mybus);
`include "def.v" // defines BUS_WIDTH
input [BUS_WIDTH:0] mybus;
...

You can't use the ANSI C ports, because the include file doesn't get
included until after the portlist.

This seems like a big limitation of ANSI C style ports.

Eliot

Not true. Below is a cutout of a modeld that worked:
Notice a mixture of parameters + `include.
module mem_slave
#(parameter number_idtmem = 0,
`include "ahb_param.v"
) // 0 -> full board, 1 -> 1 mem unit
(
output [31:0] hrdata, // Slave Read data bus
....
-------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Using PSL/SUGAR with Verilog and VHDL
Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------

 

[Steven Sharp]

eliot.franklin@conexant.com (Eliot Franklin) wrote in message news:<22e263df.0308201215.15cfef96@posting.google.com>...

It seems that the ANSI C port definition can't handle when all the
parameters are defined in an include file. For example:

module mymod (mybus);
`include "def.v" // defines BUS_WIDTH
input [BUS_WIDTH:0] mybus;
...

You can't use the ANSI C ports, because the include file doesn't get
included until after the portlist.

This seems like a big limitation of ANSI C style ports.

There is nothing preventing you from putting the contents of an ANSI-C
style parameter list in an include file, and including them at the
appropriate place in the declaration:

module mymod #(
`include "def.v" // defines BUS_WIDTH
) (input [BUS_WIDTH:0] my_bus);

This is a little ugly because of the requirement for `include to be
on its own line, but it is perfectly legal syntax.

You would have to make the contents of the file match the syntax of an
ANSI-C style parameter list instead of old-style parameter declarations,
but that should be fine if you are using ANSI-C style everywhere.

 

[VhdlCohen]

This would work great, however it looks like VCS 7.0 +v2k can't
compile the parameter syntax "module modname #(parameter_list)". So
I'll have to wait until it gets supported by VCS.

Eliot

Tha's what "NICE" about a "supported" standard!
Checkout "The IEEE Verilog-2001 Simulation Tool Scoreboard" at
http://www.sunburst-design.com/papers/

Ben

 

[a2zasics]

Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:<3f499ae5@dnews.tpgi.com.au>...

a2zasics wrote:
Hi,

I have added a free Verilog code editor (with color coding) for the
tcl users. Its freeware and allows addition of more languages to the
Verilog, Tcl set. User can define and add more functions libraries to
the existing onces through pref.rc file. For more details read the
README. I have included a windows document file .chm. HTML help is
there for other users.

I thank B. Oakley for supertext utility.

Links:

http://tcl4dummies.tripod.com [look for polaris editor]
or
http://tcl4dummies.tripod.com/scripts/Rel1.0.zip

Here is its list of keywords:


set keyw [list "ENDMODULE" MODULE ALWAYS INITIAL BEGIN END IF ELSE \
PARAMETER CASE ENDCASE CASEX CASEZ POSEDGE NEGEDGE ASSIGN \
`DEFINE `TIMESCALE `INCLUDE TASK ENDTASK FOR INTEGER DEFAULT "@" OR
"&&" "&" "||"]


Do you intend expanding this to include *all* Verilog keywords?

Allan.

Sure, thanks Allan for pointing out. I will look at expanding keywords
as soon as i get the time. Although i dont have access to new verilog
2000 standard. If anyone has a list of those keywords, i will add
those too.

Shardendu

 

[a2zasics]

shardendu@tenesix.com (a2zasics) wrote in message news:<863c0525.0308250549.11404d0e@posting.google.com>...

Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:<3f499ae5@dnews.tpgi.com.au>...
a2zasics wrote:
Hi,

I have added a free Verilog code editor (with color coding) for the
tcl users. Its freeware and allows addition of more languages to the
Verilog, Tcl set. User can define and add more functions libraries to
the existing onces through pref.rc file. For more details read the
README. I have included a windows document file .chm. HTML help is
there for other users.

I thank B. Oakley for supertext utility.

Links:

http://tcl4dummies.tripod.com [look for polaris editor]
or
http://tcl4dummies.tripod.com/scripts/Rel1.0.zip

Here is its list of keywords:


set keyw [list "ENDMODULE" MODULE ALWAYS INITIAL BEGIN END IF ELSE \
PARAMETER CASE ENDCASE CASEX CASEZ POSEDGE NEGEDGE ASSIGN \
`DEFINE `TIMESCALE `INCLUDE TASK ENDTASK FOR INTEGER DEFAULT "@" OR
"&&" "&" "||"]


Do you intend expanding this to include *all* Verilog keywords?

Allan.


Sure, thanks Allan for pointing out. I will look at expanding keywords
as soon as i get the time. Although i dont have access to new verilog
2000 standard. If anyone has a list of those keywords, i will add
those too.

Shardendu

I have posted an update rev1.1 with mostly keywords that i could find.
Please let me know if there is something you would like to be added.

Shardendu

 

[a2zasics]

shardendu@tenesix.com (a2zasics) wrote in message news:<863c0525.0308251644.64282e63@posting.google.com>...

shardendu@tenesix.com (a2zasics) wrote in message news:<863c0525.0308250549.11404d0e@posting.google.com>...
Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:<3f499ae5@dnews.tpgi.com.au>...
a2zasics wrote:
Hi,

I have added a free Verilog code editor (with color coding) for the
tcl users. Its freeware and allows addition of more languages to the
Verilog, Tcl set. User can define and add more functions libraries to
the existing onces through pref.rc file. For more details read the
README. I have included a windows document file .chm. HTML help is
there for other users.

I thank B. Oakley for supertext utility.

Links:

http://tcl4dummies.tripod.com [look for polaris editor]
or
http://tcl4dummies.tripod.com/scripts/Rel1.0.zip

Here is its list of keywords:


set keyw [list "ENDMODULE" MODULE ALWAYS INITIAL BEGIN END IF ELSE \
PARAMETER CASE ENDCASE CASEX CASEZ POSEDGE NEGEDGE ASSIGN \
`DEFINE `TIMESCALE `INCLUDE TASK ENDTASK FOR INTEGER DEFAULT "@" OR
"&&" "&" "||"]


Do you intend expanding this to include *all* Verilog keywords?

Allan.


Sure, thanks Allan for pointing out. I will look at expanding keywords
as soon as i get the time. Although i dont have access to new verilog
2000 standard. If anyone has a list of those keywords, i will add
those too.

Shardendu


I have posted an update rev1.1 with mostly keywords that i could find.
Please let me know if there is something you would like to be added.

Shardendu

H i,

I have posted a new revision with much faster color coding. So
instead of taking minutes it takes just seconds to load heavy files.
Thanks to all the people with suggestions.

http://tcl4dummies.tripod.com [look for polaris editor]
o r
http://tcl4dummies.tripod.com/scripts/Rel1.2.zip

- S h a r d e n d u

 

[Uwe Bonnes]

James Fitzsimons <jamesfit@nospam.paradise.net.nz> wrote:
: Hi all,
: I am just starting out with verilog, and am trying to get my first
: design into a device. I am using icarus verilog for the initial testing
: and simulation, and then the Xilinx tools under wine on linux for the
: programming of the device. I am targeting an XC9536 xilnx CPLD.

: My problem is getting icarus to generate the XNF file for me. I am
: getting the following error:

: bash-2.05a$ iverilog -txnf -ocounter.xnf counter.v
: counter.v:36: error: target (10target_xnf): Unhandled event <test.c1._
: s5>.
....

: always @reset
: if (reset)
: assign out = 0;
: else
: deassign out;

How should "assign" and "deassign" be reallized in hardware? I guess they
wotk only in simulation and not in synthesis.

Bye

--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

 

[Stephen Williams]

James Fitzsimons wrote:

Hi all,
I am just starting out with verilog, and am trying to get my first
design into a device. I am using icarus verilog for the initial testing
and simulation, and then the Xilinx tools under wine on linux for the
programming of the device. I am targeting an XC9536 xilnx CPLD.

A couple things.

First, you don't mention the version if Icarus Verilog you are using
for synthesis, but if you are using the 0.7 stable release, you likely
should upgrade to the latest snapshot to get a bunch of synthesis fixes.

Second, the -txnf target is obsolete.

Third, the -tfpga code generator does not specifically support the
XC9000 series (coolrunner?) yet, if you want it to support these
parts, a little bit of C coding in the tgt-fpga directory will be
required. You may decide instead to use xst for synthesis, and just
use Icarus Verilog for simulation, unless you or someone on this
list wishes to add the bits needed to suppport that part type.

(NOTE: Adding xc9000 support should not be exceedingly hard.)

Now on to the Verilog code:

module counter(out, clk, reset);

parameter WIDTH = 8;

output [WIDTH-1 : 0] out;
input clk, reset;

reg [3 : 0] count;
reg [WIDTH-1 : 0] out;
wire clk, reset;

always @(posedge clk)
begin
if (count < 9)
count <= count + 1;
else
count <= 0;

Your reset never resets your counter? You should probably do
that like so:

always @(posedge clk or posedge reset) begin
if (reset) // Asynchronous reseet
count <= 0;
else if (count >= 9)
count <= 0;
else
count <= count + 1;

// now that we have a value for count, we need to convert
// that to a real 8 bit output to drive the display
case (count)
0 : out = 8'b00111111;
1 : out = 8'b00110000;
2 : out = 8'b01101101;
3 : out = 8'b01111001;
4 : out = 8'b01110010;
5 : out = 8'b01011011;
6 : out = 8'b01011110;
7 : out = 8'b00110001;
8 : out = 8'b01111111;
9 : out = 8'b01111011;
endcase
end


always @reset
if (reset)
assign out = 0;
else
deassign out;

Synthesizers may have trouble with this here. out is a
combinational output, so what does it mean to reset it?

endmodule // counter

--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."

 

[Andrey Likholit]

How should "assign" and "deassign" be reallized in hardware? I guess they
wotk only in simulation and not in synthesis.

Bye

Uwe,

'assign' works in synthesized code but 'deassign' does not.

Example:

module test(a,b,c);
input [7:0] a;
input [7:0] b;
output [7:0] c;
assign c = a & b;
endmodule

8 2-input AND-gates will be synthesized.

Regards,
Andrey

 

[James Fitzsimons]

Hi all,
first thanks to all that responded to my original posting, I am learning
lots already ;-)

First, you don't mention the version if Icarus Verilog you are using
for synthesis, but if you are using the 0.7 stable release, you likely
should upgrade to the latest snapshot to get a bunch of synthesis fixes.

Cheers, I'll do that.

Second, the -txnf target is obsolete.
Ok

Third, the -tfpga code generator does not specifically support the
XC9000 series (coolrunner?) yet, if you want it to support these
parts, a little bit of C coding in the tgt-fpga directory will be
required.
I may look into that in the future, I just want to get something running

first!

You may decide instead to use xst for synthesis, and just
use Icarus Verilog for simulation, unless you or someone on this
list wishes to add the bits needed to suppport that part type.

Sounds like a plan (at least to begin with).

Thanks for the verilog tips. I'll modify my code and try again using xst for
synthesis.

Cheers,
James Fitzsimons

 

[Shalom Bresticker]

Not a regular continuous assignment, but this is a procedural continuous
assignment.
Similar, but not exactly the same.

Shalom


Andrey Likholit wrote:

Hi James,

It seems to me that the problem is here:
always @reset
if (reset)
assign out = 0;
else
deassign out;

It is not clear to me what this code is intended for but regardless my
understanding you may not use variable of register data type in
continuous assignment. In the code above 'out' is defined as reg.
Only net data type could be assigned with 'assign' keyword. Eligible
types are wire, tri and so on.

Also you may not use 'assign' keyword within 'always' and 'initial'
blocks.

Andrey

--
Shalom Bresticker Shalom.Bresticker@motorola.com
Design & Reuse Methodology Tel: +972 9 9522268
Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890
POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478

 

[Andrey Likholit]

Ok, thank you! I'll fix it in my mind
Andrey

Shalom Bresticker <Shalom.Bresticker@motorola.com> wrote in message news:<3F534A0A.C4E7F96E@motorola.com>...

Not a regular continuous assignment, but this is a procedural continuous
assignment.
Similar, but not exactly the same.

Shalom

 

[K.Orthner]

qOn 8 Sep 2003 18:00:52 -0700, a2zasics <shardendu@tenesix.com> wrote:





--
Using M2, Opera's revolutionary e-mail client: hqttp://www.opera.com/m2/

 

[Andy Peters]

Chris Carlen <crcarle@BOGUS.sandia.gov> wrote in message news:<bsa1a102rfm@enews3.newsguy.com>...

The Verilog they provided is (just counter section within an always @
(posedge clk) begin procedural construct):

//Counter section:
if(run) begin
if(dir) begin
q[3:1] = q[2:0]; //Shift lower bits (Left Shift)
q[0] = !q[3]; //Circulate inverted MSB to LSB
end
else begin
q[2:0] = q[3:1]; //Shift upper bits (Right Shift)
q[3] = !q[0]; //Circulate inverted LSB to MSB
end
end

Jeez. More blocking assignments in clocked always blocks! Further
proof of my assertion that models and examples are built by a
company's most junior engineers, and that the companies involved don't
bother checking anything before throwing it up on the web. The only
possible explanation is that they just don't care.

If we can't trust the examples, how can we trust the post-P&R
simulation models?

--a

 

[Chris Carlen]

Andy Peters wrote:

Chris Carlen <crcarle@BOGUS.sandia.gov> wrote in message news:<bsa1a102rfm@enews3.newsguy.com>...

The Verilog they provided is (just counter section within an always @
(posedge clk) begin procedural construct):

//Counter section:
if(run) begin
if(dir) begin
q[3:1] = q[2:0]; //Shift lower bits (Left Shift)
q[0] = !q[3]; //Circulate inverted MSB to LSB
end
else begin
q[2:0] = q[3:1]; //Shift upper bits (Right Shift)
q[3] = !q[0]; //Circulate inverted LSB to MSB
end
end


Jeez. More blocking assignments in clocked always blocks! Further
proof of my assertion that models and examples are built by a
company's most junior engineers, and that the companies involved don't
bother checking anything before throwing it up on the web. The only
possible explanation is that they just don't care.

If we can't trust the examples, how can we trust the post-P&R
simulation models?

--a

Good points. I guess I will be cautious about using the examples for
coding style.

I will be diving in to the text seriously starting Monday when I'm back
to work. Hopefully the text will learn me the right way.

Good day and thanks for the input.


--
_____________________
Christopher R. Carlen
crobc@earthlink.net
Suse 8.1 Linux 2.4.19

 

[Andy Peters]

filippdavid@yahoo.com (filippo) wrote in message news:<18add487.0402060204.340e7b39@posting.google.com>...

I' m having great troubles making a small project on FPGA in Verilog.
I have to do it for an exam at university, it shoul be simple but it's
becoming hell.

problem:

all simulations with modelsim are good, but it just doesn' t work on
the real FPGA and i don't know where to find a solution (or where is
the real problem).

Did you perform both pre- and post-route simulations? What does your
test bench actually do? Is it a real bus-functional model of your
microcontroller? Or are you just setting and clearing signals in some
arbitrary fashion? I would imagine that this is the root of your
problem -- your simulation is bogus. As they say: garbage in, garbage
out?

What about your timing constraints?

of the 10+ modules one seems to be the most troublesome, our
IO_control, here is the code ,please help.

---------------------------------------------------------------------------------
module IO_control(ALE,NWR,NRD,DIR,DA,MIN,MAX,SEL,TYPEFIL,AMPLIF,DIVFRQ,clk);
input ALE;
input NWR;
input clk;
input NRD;
input DIR;
input [7:0] MIN;
input [7:0] MAX;
inout [7:0] DA;
output [7:0] SEL;
output [7:0] TYPEFIL;
output [7:0] AMPLIF;
output [7:0] DIVFRQ;

parameter uno = 8'b0000_0001;

reg [7:0] ADDR_REG;
reg [7:0] DO_REG;
reg [7:0] SEL_REG=uno;
reg [7:0] TYPEFIL_REG=uno;
reg [7:0] AMPLIF_REG=uno;
reg [7:0] DIVFRQ_REG=uno;
^^^^^^^^^^^

This initialization is illegal, or at least ignored by a synthesis
tool.
Use an external reset to actually initialize these registers.

assign SEL = SEL_REG;
assign TYPEFIL = TYPEFIL_REG;
assign AMPLIF = AMPLIF_REG;
assign DIVFRQ = DIVFRQ_REG;

Ummmmm...why not declare the SEL, TYPEFIL, AMPLIF and DIVFRQ outputs
as regs and not bother with this silly assign? Also: explicitly
declare whether your module outputs are wires or regs. It's a good
style habit.

assign DA = (DIR) ? 8'bzzzz_zzzz : DO_REG;

always @ (posedge clk)
begin
if (ALE) ADDR_REG <= DA;

if (~NWR)
case (ADDR_REG)
8'b0000_0001 : SEL_REG <= DA;
8'b0000_0010 : TYPEFIL_REG <= DA;
8'b0000_0100 : AMPLIF_REG <= DA;
8'b0000_1000 : DIVFRQ_REG <=DA;
default DO_REG <= 8'b1111_1111;
endcase

if (~NRD)
case (ADDR_REG)
8'b0000_0001 : DO_REG <= SEL_REG;
8'b0000_0010 : DO_REG <= TYPEFIL_REG;
8'b0000_0100 : DO_REG <= AMPLIF_REG;
8'b0000_1000 : DO_REG <= DIVFRQ_REG;
8'b0001_0000 : DO_REG <= MIN;
8'b0010_0000 : DO_REG <= MAX;
default DO_REG <= 8'b1111_1111;
endcase
end

Umm, another style issue. Use more than one always statement for the
above. You have three separate registers; put 'em in their own always
blocks.

Also: are ALE, NRD, NWR, DA all synchronous to your clock?

Remember that ALE is a latch enable -- are you sure that your address
is actually valid when the latch enable is active and goes away?

--a

 

[pini]

reg [7:0] TYPEFIL_REG=uno;
You can initialize when targeting to synthesis (only for
verification). Use reset instead.
if(posedge clock or negedge reset_n) begin
if(~reset_n) ....
else ..

Bassman59a@yahoo.com (Andy Peters) wrote in message news:<9a2c3a75.0402061216.7206d4cf@posting.google.com>...

filippdavid@yahoo.com (filippo) wrote in message news:<18add487.0402060204.340e7b39@posting.google.com>...
I' m having great troubles making a small project on FPGA in Verilog.
I have to do it for an exam at university, it shoul be simple but it's
becoming hell.

problem:

all simulations with modelsim are good, but it just doesn' t work on
the real FPGA and i don't know where to find a solution (or where is
the real problem).

Did you perform both pre- and post-route simulations? What does your
test bench actually do? Is it a real bus-functional model of your
microcontroller? Or are you just setting and clearing signals in some
arbitrary fashion? I would imagine that this is the root of your
problem -- your simulation is bogus. As they say: garbage in, garbage
out?

What about your timing constraints?

of the 10+ modules one seems to be the most troublesome, our
IO_control, here is the code ,please help.

---------------------------------------------------------------------------------
module IO_control(ALE,NWR,NRD,DIR,DA,MIN,MAX,SEL,TYPEFIL,AMPLIF,DIVFRQ,clk);
input ALE;
input NWR;
input clk;
input NRD;
input DIR;
input [7:0] MIN;
input [7:0] MAX;
inout [7:0] DA;
output [7:0] SEL;
output [7:0] TYPEFIL;
output [7:0] AMPLIF;
output [7:0] DIVFRQ;

parameter uno = 8'b0000_0001;

reg [7:0] ADDR_REG;
reg [7:0] DO_REG;
reg [7:0] SEL_REG=uno;
reg [7:0] TYPEFIL_REG=uno;
reg [7:0] AMPLIF_REG=uno;
reg [7:0] DIVFRQ_REG=uno;
^^^^^^^^^^^
This initialization is illegal, or at least ignored by a synthesis
tool.
Use an external reset to actually initialize these registers.

assign SEL = SEL_REG;
assign TYPEFIL = TYPEFIL_REG;
assign AMPLIF = AMPLIF_REG;
assign DIVFRQ = DIVFRQ_REG;

Ummmmm...why not declare the SEL, TYPEFIL, AMPLIF and DIVFRQ outputs
as regs and not bother with this silly assign? Also: explicitly
declare whether your module outputs are wires or regs. It's a good
style habit.

assign DA = (DIR) ? 8'bzzzz_zzzz : DO_REG;

always @ (posedge clk)
begin
if (ALE) ADDR_REG <= DA;

if (~NWR)
case (ADDR_REG)
8'b0000_0001 : SEL_REG <= DA;
8'b0000_0010 : TYPEFIL_REG <= DA;
8'b0000_0100 : AMPLIF_REG <= DA;
8'b0000_1000 : DIVFRQ_REG <=DA;
default DO_REG <= 8'b1111_1111;
endcase

if (~NRD)
case (ADDR_REG)
8'b0000_0001 : DO_REG <= SEL_REG;
8'b0000_0010 : DO_REG <= TYPEFIL_REG;
8'b0000_0100 : DO_REG <= AMPLIF_REG;
8'b0000_1000 : DO_REG <= DIVFRQ_REG;
8'b0001_0000 : DO_REG <= MIN;
8'b0010_0000 : DO_REG <= MAX;
default DO_REG <= 8'b1111_1111;
endcase
end

Umm, another style issue. Use more than one always statement for the
above. You have three separate registers; put 'em in their own always
blocks.

Also: are ALE, NRD, NWR, DA all synchronous to your clock?

Remember that ALE is a latch enable -- are you sure that your address
is actually valid when the latch enable is active and goes away?

--a