need a cheap student edition FPGA

[Jason Zheng]

Your delay task doesn't do its job. Consider this: call delay(1) 1ps
before the next rising edge of clock. You will end up with just 1ps
delay instead of a whole clock cycle. Here's a better and more efficient
way to implement delay:

`define CLK_CYCLE 30

....
task delay:
input [31:0] index;
begin
#(`CLK_CYCLE*index);
end

Pearls Harbour wrote:

Hi, there:

I need the "delay" to allow run empty for index cycles, then
in each dat_en window, dat is incremented.

Thanks.




module tasks;
reg clk;
reg rst;

reg [7:0] dat;
reg dat_clk;
reg dat_en;

initial
begin
delay(100);
data_in(100);
delay(100);
data_in(100);
delay(100);
data_in(100);
delay(100);
$finish;
end

initial
begin
clk <= 1'b0;
forever begin
#5 clk <= 1'b1;
#5 clk <= 1'b0;
end
end

task delay;
input [31:0] index;
integer i;
begin
for(i = 0; i <= index; i = i + 1) @(posedge clk);
end
endtask



task data_in;
input [31:0] index;
integer i, j;
begin

rst <= 1'b0;
dat <= 8'd01;
dat_en <= 1'b1;
dat_clk <= 1'b1;
@(posedge clk);
rst <= 1'b1;
for(j = 0; j <= index; j = j + 1) begin
for(i = 0; i <= 5; i = i + 1) begin
@(posedge clk);
dat <= dat + 8'd1;
dat_clk <= 1'b1;
@(posedge clk);
dat <= dat + 8'd1;
dat_clk <= 1'b0;
end
end
dat_en <= 1'b0;
@(posedge clk);
rst <= 1'b0;
end
endtask


endmodule

 

[John_H]

"Ken" <camel207@yahoo.com.tw> wrote in message
news:1142963264.145374.110920@g10g2000cwb.googlegroups.com...

Hi guys:

I am doing a LCD display module to simulate the real LCD.

I have faced 2 interesting problems. Can someone body help me ?

1.When we use two display statements in a code the values in the
display
statement will be printed into two different lines.Is there any way to
display
the values side by side.

Eg: $display("xxxxx")
$display("yyyyy")
we will get the output as xxxxx
yyyyy
Can we display the output as xxxxxyyyyy using the display?

Eg: $write("xxxxx");
$display("yyyyy");

2.One more question is that can we change the output printed in the
Console.
I mean if we first get the ABC as an output in the Console.Is there any
way to
delete the character C so that we can change the output in the Console
like
the real LCD. if we get the output as ABC and if we press backspace the
ouput will change to
AB in a real LCD.Can we do the similar way in the Console?

I am very grateful for your answer.

Ken

If there are control characters for your terminal, you may be able to use
those.
The write and a backspace character *might* give you what you need but I
don't know for sure and I haven't tried it.

 

$display automatically puts a newline at the end of the output. If you
don't want the newline, you should call $write instead. It works
exactly the same way as $display except that it doesn't put a newline
at the end.

Overwriting text is a bigger problem. You can print backspaces to move
the cursor back, so that you can then write characters over what was
there. However, unless your output to standard out is unbuffered, you
won't see any of the characters until you print a newline. And once
you print a newline, you can't go back to overwrite the line. If your
tool has a way of making standard out unbuffered, you still have
issues. Anything else written by the simulator (such as interactive
command line prompts for debugging, or echoing of your keyboard input)
will also mess up your display.

 

[Jarkko Kajander]

Nettimaailma on siitä lystikäs kiulu, että jostain kumman syystä sinne
kirjoitelleille muodostuu illuusio siitä,että ikäänkuin identtiteetti olisi
täällä jollain mystisellä tasvalla suojassa. Väärä luulo. Linjojen
pitäjillä/SUPO:lla kun on lakimääre tunnistaa KAIKKI kirjoittajanimet, koska
netti rinnastetaan juridiesti lehtikirjoituksiin. Yhtä kaikki tuli tuosta
nimimerkki kampamaneeti alias Ilkka Karailan, eli tutummin IK:n
kirjoituksista mieleeni esitellä ihan vaan lystänä pintaraapaisuna joitain
täällä kirjoittavia aavistuksen syvemmältä. Huomaa en tässä nyt keskity
tyhjänpäiväisiin elektroniikkanettinsinööristön mitä lie "FK" tyyppisiin
ketään kiinnostamattomiin. Vaan ihan lihaa ja verta oleviin inehmoihin.
Aivan siis hiillostavan hempeä pintaraapaisu toki.

Nimimerkki Nano ihmetteli, että miksi netti oli muuttunut
rekrytointi-ilmoitussetiksi hänen poissa ollessaan? Oikein hyvä kysymys,
mutta tutkaillan ine. Esimerkiksi tosiaan tämä kampamaneetti = IK.=Ilkka
Karaila oli siis töissä firmassa, joka alkoi selkeästi miten sanoisin
"ekologistaa" toimenkuvaansa. Mikä oli tietysti ydinvetoiselle
vihamieliselle kaverille paikka lentäytyä ulos etsimään elämälleen uutta
paukkumustempaa suuntaa. No selvä se tietysti, että ydinkiimainen kolo jäi
vaivaamaan loppuelämäkseen, oi ja voi. Sitten esim. mielenkiintoinen tapaus
Untamo. Kaveri oli intomielellä hakenut töihin oliko se nyt STUK:n ydinalaan
liittyviin hommeleihin. Ihan kivasti aukesi jobit. Ja sai riemukseen jopa
koeaikaa valtiomonopolisessa firmassa. Vaan ah ja voi mokasi ja tiputus
tuli. No sen perään kun tällaiset kavertit lukee kaltaisistani ydintöihin
"päässeistä" ja sielä vuosikymmenet pyyteettä ahkeroineitten aitoja tuntoja
ja faktoja. .. Ja ennenkaikkea murskaavista ydinilluusioiden
totaaliromahteluista, niin menee se toki Untamaloilla& kump. ydinmaselle,
menee. Katkeruus on kova pala illuusioromahteluissaan, kun heitä viisaammat
osaa.

Toki voisin keskustella tähän taustoiksi vaikka tapaus mm. Anssi H.
katkeroituneen, petetyn ydinalainsun nettiruppanan maksetuista
myyräntöistään TVO:n toimenkuvana täällä, mutta (haukotus), ketä oikeesti
kiinostaa tuollaiset paskan vertaa?) .. No sitten vaikka klassikko
Uudenkaupungin Matti Lehtiniemi. Eläkkeelle lahoamaan jätetty (OL-3
projekteista poislemppauksista) katkeroitunut kaveri joka on koko sakista
muuten ainoa joka on saanut ihan OIKEASTI myös näyttävyyttä aikaan! Siitä
hänelle rehti lippisnosto toki. Sai SUPO:n listoillaan suorastaan hyppimään
seinille, kun kaatoi nimissäni puolet nettiverkostoa. Komennettiin
hermolepoon Battajalle ja toivottiin ettei ihan heti palaisi sikailemaan.
Vaan näyttää se taas hän täällä nimenvaihdoin skrivaavaan kiivaasti.

Jottei menisi ihan pelkkään mömmöilyyn niin sitten valtavasta arkistostani
vielä eräs esimerkki. Pauli Keinänen. Otan hänet tähän lopuksi enempi
verrokisksi kaikille yllämainitsemiini. Eli Pauli on töissä VTT:n
tuulihuulihommissa. Käy milloin Tanskassa ja vastaavilla alansa
komennuksillaan. Tietäisi sielä rakentuvista jopa 10MW ja 80-90%
tuulipysyvyyslaitteista paljon. Mutta koska Suomen ydinala sensuroi, ja
sabotoi tuulialaa kylmästi kaveri ei uskalla kertoa sanan sanaa näistä yli
300m korkeista näkemistään energiatulevaisuuden komistuksista. Ja toki se
katkeroittaa myös nettinärään, ettei uskalla puhua elämäntyöstään mitään
nyky-ydinterron alla. En ihmettele yhtään. No tässä näitä ja lisää tietysti
tykittää jahka "HALUATTE" tietää lisää.)

 

[Jonathan Bromley]

On Sat, 4 Apr 2009 08:54:19 -0700 (PDT), unfrostedpoptart wrote:

This has been giving me headaches as I start using SV Interfaces.
Here's the issue. The spec, and VCS, say it's illegal to have
unconnected ports of type interface. Normally, this isn't a problem.
I'd either have a higher-level RTL module that connects the ports, or
a testbench above the module that connects them. The problem is when I
want to do a quick compile on just that module while developing it to
check syntax, etc. I can't do this because VCS, and presumably other
compilers, error out on the unconnected interface ports.

Does anyone have an easy solution to this?

By default, VCS does compilation and elaboration in a
single step (the "vcs" command). In Cadence and Mentor
simulators, you can run an independent compilation step
(ncvlog, vlog) that syntax-checks the module(s) but does
not attempt to do elaboration. I believe the same thing
can be done in VCS, and I *think* the command is "vlogan",
but you'll need to check the docs yourself.

Beware that this sort of single-module compilation doesn't
buy you a lot in Verilog or SV (unlike VHDL, where compiling
a module successfully is pretty much a guarantee that it can
be elaborated correctly). If your module has an interface-
type port and you compile it, there is no check that the
interface has the form that your code expects. See my recent
rant-paper at DVCon for further evidence of how this stuff
rather easily raises my blood pressure.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

On Apr 18, 5:05 am, Uwe Bonnes <b...@elektron.ikp.physik.tu-
darmstadt.de> wrote:

uraniumore...@gmail.com wrote:
Hello All,
I have a question regarding programming the Spartan 3AN. I have a bit
file that I would like to program on my board, and would like to run
every time I turn on the FPGA. I know it can be easily done, but I
just don't know the process.

Start impact with a jtag dongle connected to your board, and when the 3AN is
recognized in your jtag chain. click right on the device. There is an option
(in recent impact versions) to program the on-chip flash.
Be sure the FPGA Mode pins are connected right. Check UG332.

Bye
--
Uwe Bonnes                b...@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

I cannot get the pin connected right. Which pins do I need to connect
to get the SPANTAN 3AN to program my internal flash? Note that I am
trying to configure the board so that whenever I restart the board
the .bit fill gets loaded automatically.

 

On Apr 26, 12:37 pm, uraniumore...@gmail.com wrote:

On Apr 18, 5:05 am, Uwe Bonnes <b...@elektron.ikp.physik.tu-





darmstadt.de> wrote:
uraniumore...@gmail.com wrote:
Hello All,
I have a question regarding programming the Spartan 3AN. I have a bit
file that I would like to program on my board, and would like to run
every time I turn on the FPGA. I know it can be easily done, but I
just don't know the process.

Start impact with a jtag dongle connected to your board, and when the 3AN is
recognized in your jtag chain. click right on the device. There is an option
(in recent impact versions) to program the on-chip flash.
Be sure the FPGA Mode pins are connected right. Check UG332.

Bye
--
Uwe Bonnes                b...@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

I cannot get the pin connected right. Which pins do I need to connect
to get the SPANTAN 3AN to program my internal flash? Note that I am
trying to configure the board so that whenever I restart the board
the .bit fill gets loaded automatically.- Hide quoted text -

- Show quoted text -

Okay, I have figured it out.

I read http://www.xilinx.com/support/documentation/boards_and_kits/ug334.pdf,
and I found out that after you program the flash memory, disconnect
the power adapter and remove the jumpers from J23, J25, and J16, and
then re-connect the power adapter.

Bingo!

Thanks,

 

[Jeremy Bennett]

On Thu, 23 Jul 2009 07:31:31 -0700, Kenneth Brun Nielsen wrote:

Can I save the state of a simulation using Icarus Verilog simulator?

I found the $save command in Google, but it doen't seem to work in
Icarus (vvp).
"
$save1: This task not defined by any modules. I cannot compile it.
ta_test: Program not runnable, 1 errors. "

Any alternatives in Icarus?

Hi Kenneth,

$save is an optional part of Verilog (at least Verilog 2001). It's in
Annex C of the standard (IEEE 1364-2001). I can't find explicit reference
to it in the Icarus Verilog documentation.

You might find it useful to ask the Icarus Verilog developer's mailing
list about this issue: https://lists.sourceforge.net/lists/listinfo/
iverilog-devel. If the feature isn't there, it's open source, so you
could always add it yourself .

HTH,

Jeremy

 

[Stephen Williams]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Kenneth Brun Nielsen wrote:

Can I save the state of a simulation using Icarus Verilog simulator?

I found the $save command in Google, but it doen't seem to work in
Icarus (vvp).

$save1: This task not defined by any modules. I cannot compile it.
ta_test: Program not runnable, 1 errors.

It's not implemented in Icarus Verliog (it's an optional part of
the standard) and implementing it would be pretty involved. If you
would like to see it in the future, discuss it in the iverilog-devel
mailing list, and/or add a feature request tracker item.

- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.4-svn0 (GNU/Linux)
Comment: Using GnuPG with SUSE - http://enigmail.mozdev.org

iD8DBQFKba33rPt1Sc2b3ikRAs6BAJ9On+Q705x3r632MW0iNpQmh+YIWQCgytHB
Mk2dXT5yorEjjk7eXYdqt6I=
=a9yR
-----END PGP SIGNATURE-----

 

[Allan Herriman]

On Sun, 26 Jul 2009 10:28:03 -0700, Muzaffer Kal wrote:

On 26 Jul 2009 16:23:16 GMT, General Schvantzkoph
schvantzkoph@yahoo.com> wrote:

Has anyone benchmarked Core7 vs Core2 on NCverilog, Questa, Xilinx and
Altera FPGA tools?

I'd also be very interested in Core7 vs Phenom II performance too (45nm
AMD ie Phenom II 955 etc.)

We just got a new i7 machine for FPGA builds. It tested at just over
twice as fast as our high-end AMD box that was 2-3 years old.

I will publish the results in this ng within a week or two, assuming I
can ever get the licensing for ISE 11.2 running on it. (Thanks Xilinx,
flexlm was a really good move.)

Regards,
Allan

 

[General Schvantzkoph]

On Tue, 28 Jul 2009 15:22:25 +0000, Allan Herriman wrote:

On Sun, 26 Jul 2009 10:28:03 -0700, Muzaffer Kal wrote:

On 26 Jul 2009 16:23:16 GMT, General Schvantzkoph
schvantzkoph@yahoo.com> wrote:

Has anyone benchmarked Core7 vs Core2 on NCverilog, Questa, Xilinx and
Altera FPGA tools?

I'd also be very interested in Core7 vs Phenom II performance too (45nm
AMD ie Phenom II 955 etc.)


We just got a new i7 machine for FPGA builds. It tested at just over
twice as fast as our high-end AMD box that was 2-3 years old.

I will publish the results in this ng within a week or two, assuming I
can ever get the licensing for ISE 11.2 running on it. (Thanks Xilinx,
flexlm was a really good move.)

Regards,
Allan

What's the clock rate on each machine? iCore7 motherboards and processors
are twice as expensive as Core2 motherboards and processors, and
mainstream Core2s have a higher clock rate than iCore7s, so the clock
rate normalized performance is what's important.

 

[Jason Zheng]

On 28 Jul 2009 16:04:32 GMT
General Schvantzkoph <schvantzkoph@yahoo.com> wrote:

On Tue, 28 Jul 2009 15:22:25 +0000, Allan Herriman wrote:

On Sun, 26 Jul 2009 10:28:03 -0700, Muzaffer Kal wrote:

On 26 Jul 2009 16:23:16 GMT, General Schvantzkoph
schvantzkoph@yahoo.com> wrote:

Has anyone benchmarked Core7 vs Core2 on NCverilog, Questa, Xilinx
and Altera FPGA tools?

I'd also be very interested in Core7 vs Phenom II performance too
(45nm AMD ie Phenom II 955 etc.)


We just got a new i7 machine for FPGA builds. It tested at just
over twice as fast as our high-end AMD box that was 2-3 years old.

I will publish the results in this ng within a week or two,
assuming I can ever get the licensing for ISE 11.2 running on it.
(Thanks Xilinx, flexlm was a really good move.)

Regards,
Allan

What's the clock rate on each machine? iCore7 motherboards and
processors are twice as expensive as Core2 motherboards and
processors, and mainstream Core2s have a higher clock rate than
iCore7s, so the clock rate normalized performance is what's important.

Clock rates is just an artificial number; I'd be more interested in
performance normalized to non-recurring cost (purchase price) and
operating cost (power consumption).

 

[General Schvantzkoph]

On Tue, 28 Jul 2009 09:42:08 -0700, Jason Zheng wrote:

On 28 Jul 2009 16:04:32 GMT
General Schvantzkoph <schvantzkoph@yahoo.com> wrote:

On Tue, 28 Jul 2009 15:22:25 +0000, Allan Herriman wrote:

On Sun, 26 Jul 2009 10:28:03 -0700, Muzaffer Kal wrote:

On 26 Jul 2009 16:23:16 GMT, General Schvantzkoph
schvantzkoph@yahoo.com> wrote:

Has anyone benchmarked Core7 vs Core2 on NCverilog, Questa, Xilinx
and Altera FPGA tools?

I'd also be very interested in Core7 vs Phenom II performance too
(45nm AMD ie Phenom II 955 etc.)


We just got a new i7 machine for FPGA builds. It tested at just over
twice as fast as our high-end AMD box that was 2-3 years old.

I will publish the results in this ng within a week or two, assuming
I can ever get the licensing for ISE 11.2 running on it. (Thanks
Xilinx, flexlm was a really good move.)

Regards,
Allan

What's the clock rate on each machine? iCore7 motherboards and
processors are twice as expensive as Core2 motherboards and processors,
and mainstream Core2s have a higher clock rate than iCore7s, so the
clock rate normalized performance is what's important.

Clock rates is just an artificial number; I'd be more interested in
performance normalized to non-recurring cost (purchase price) and
operating cost (power consumption).

Within an architecture CPU clock rate is the one thing that's directly
proportional to performance. Memory performance has a small effect on
performance, but in the age of multi-megabyte caches it's a distinctly
second order effect. Price is something that you worry about at the time
of purchase, the price that someone else paid for their system is
completely irrelevant. What I want to know is the relative performance of
Core2 vs iCore7 on a few important applications specifically NCverilog,
which is where I spend 98% of my time, and the Xilinx and Altera FPGA
tools. My current fastest machine is a 3GHz Core2 overclocked to 4GHz
(I'm using a heatsink the size of Volkswagen). The motherboard for that
system is $115 these days and the CPU is $168. A 2.66Ghz iCore7 is $280,
a 3GHz iCore7 is $569 and an iCore7 motherboard is in the neighborhood of
$250. If the clock for clock NCVerilog performance of an iCore7 is really
2X a Core2 then it makes sense to buy one assuming that I can get a
similar overclock on the iCore7. If it's only 30% then it doesn't make
sense because it's unlikely that a 2.66GHz iCore7 can be overclocked to
the same clock as a 3GHz Core2.

 

[Rob Dekker]

Hi Wando,

We (Verific) provide a Verilog-AMS parser, which is free in evaluation form
(a binary that reads AMS, and elaborates and writes out elaborated tree).

But you cannot do much with it unless you want to license the (C++) sources
and build your own EDA tool with it.

What do you want to do after you parse ?

Rob



"wanbo" <wanbo@u.washington.edu> wrote in message
news:bd84ik$28g6$1@nntp6.u.washington.edu...

Hi,

Anybody knows if there is a free Verilog-A parser? I do check the faq, but
there is only info about Verilog parser...

Thanks,
Bo

 

[oiwo]

"don" <don@nowhere.net> wrote in message
news:gN%Ia.558$x7.59613245@newssvr21.news.prodigy.com...
warning, whining complaint follows...

My company is starting a new ASIC project where I'd like
to use Verilog-2001 (instead of Verilog-1995.) I bought
Palitknar's Verilog-HDL 2nd edition (ISBN 0130449113)
which covers the IEEE 1364-2001 Verilog.


I'd like to dissuade others from buying Palnitkar's book. I checked out
the
new edition briefly and it appeared that the originally inadequate book
had
been barely modified for the 2nd edition, with the exception that the
cover
now states that it covers Verilog-2001. The new file i/o commands are
covered by a footnote that only acknowledges their existence. I'm not
even
sure the book was reprinted. Wait for something better.

I must admit, the 2nd edition adds very little to the first edition.
But I still consider Palitknar's an excellent *starter* (tutorial) book. I
found the discussion of major topics (RTL, gate, behavioral) easy to follow
and the examples really help. After reading this book, I felt ready to
tackle more advanced (and practical) books which require Verilog background.

 

[Marcin]

dew814@aol.com (Dave Ardrey) wrote in message news:<20de6cd6.0306201125.15ed413c@posting.google.com>...

I'm trying to set a path delay in my verilog module like so:

(posedge CLK => Q[15])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);


However, when I try to simulate with VerilogXL I get the following
error:

Error! Outputs for edge-sensitive paths have to be

associated with data source
[Verilog-OESDS]

"RA1SD.new", 544: (posedge CLK=>Q[15]) = 1, 1,

0.5, 1, 0.5, 1;
1 error

I've seen a line exactly like the one I have in the VerilogXL
reference guide. Any ideas what's going on here?

Thanks!

Hello Dave,

You have to choose.
simple path...

(CLK => Q[15])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);

or edge-sensitive path :
(posedge CLK => (Q[15] +: I))=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
where I is your input.
VerilogXL expected the second one.

Marcin

 

[y_p_w]

rickman <spamgoeshere4@yahoo.com> wrote in message news:<3EF7744D.1CF9F6D@yahoo.com>...

Tauno Voipio wrote:

"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3EF744FB.AF2FB36E@yahoo.com...
Tauno Voipio wrote:

"y_p_w" <y_p_w@hotmail.com> wrote in message
news:591da479.0306230937.42883d68@posting.google.com...
Hi-

I'm currently in the process of creating a synthesizable Verilog
F/S I2C slave, but have little experience with I2C in the real
world.

I'm reading the specs, and I feel I'm getting a pretty good
understanding. If I'm getting this right, the SDA line will only
change when the SCL line is low - except when the master is
indicating a START or STOP command.

So the question I have for those who have really done this is -
in the real world, could a master (or series of masters) issue
a STOP command followed by a START command - all on the same
SCL high period. The latest I2C spec doesn't explain whether
or not this could happen.

This is key to me, since I'm trying to create an I2C slave that
runs solely off the SDA and SCL signals. Whether or not I have
to deal with START and STOP on the same SCL high period will
impact the design choice I make.


AFAIK, that's normal when the bus is idle in the meantime.

The idle bus has all drivers loose and both lines up. When the master
ends a
transmission, the last thing is the STOP condition: SCL up, then SDA up.
When the next transmission starts, the first thing is the START
condition:
SCL still up, SDA down.

I think he means the other way around, a START followed by a STOP with
no clock transitions inbetween. In essence, this would be an "empty"
frame.

I have not worked with I2C before, so I don't know the answer. But I am
interested since I will be making one as well.

I have not checked opencores.org, but it seems likely that they would
have a core for this. It might be a bit larger than you would want to
use however.


An empty frame is expressely forbidden in the specs. However, the logic must
still not hang up if such a condition should happen.

Tauno Voipio
tauno voipio @ iki fi

I guess that is the answer then. The condition should not occur, but if
it does due to a defect in one component, it should not cause a problem
in another component.


To the OP,

How does this change your design? I would think an empty frame would be
handled like one that is not addressed to your device, no?

Well - here's my concerns and thinking:

1) It seems that the preferred method is to have a STOP condition
(SDA rising when SCL=1) on the same SCL high period as a START
period (SDA falling when SCL=1). This would look like this:
_________________________
SCL ___| |_____
_________________
SDA _______| |_________

2) As far as I can tell the spec says nothing about SCL changing
between a STOP and START. I wouldn't see any advantage to it,
but I couldn't sense it was illegal. I would suppose any
clock toggling before a START should just be ignored until a
START is detected.

3) I was worried about whether a master could "change its mind"
after issuing a start if it was suddenly occupied with something
considered more important. Fortunately, this doesn't seem to
be a problem.

4) Most of what I'm planning is a straightforward FSM clocked on
the negedge of SCL. The START and STOP logic I'm planning on
using isn't as straightforward. This was the part that would
have been messed up if I had to account for multiple START or
STOP methods. I wanted to create a START detected signal, and
use that to tell the FSM when to start monitoring SDA.

5) I could possibly use a high-speed internal clock. However -
the goal is a low-power design, and I was told that just
toggling the clock tree would create unnecessary power
consumption.

 

[y_p_w]

rickman <spamgoeshere4@yahoo.com> wrote in message news:<3EF86106.BCB1DCB@yahoo.com>...

y_p_w wrote:

Well - here's my concerns and thinking:

1) It seems that the preferred method is to have a STOP condition
(SDA rising when SCL=1) on the same SCL high period as a START
period (SDA falling when SCL=1). This would look like this:
_________________________
SCL ___| |_____
_________________
SDA _______| |_________

2) As far as I can tell the spec says nothing about SCL changing
between a STOP and START. I wouldn't see any advantage to it,
but I couldn't sense it was illegal. I would suppose any
clock toggling before a START should just be ignored until a
START is detected.

3) I was worried about whether a master could "change its mind"
after issuing a start if it was suddenly occupied with something
considered more important. Fortunately, this doesn't seem to
be a problem.

4) Most of what I'm planning is a straightforward FSM clocked on
the negedge of SCL. The START and STOP logic I'm planning on
using isn't as straightforward. This was the part that would
have been messed up if I had to account for multiple START or
STOP methods. I wanted to create a START detected signal, and
use that to tell the FSM when to start monitoring SDA.

5) I could possibly use a high-speed internal clock. However -
the goal is a low-power design, and I was told that just
toggling the clock tree would create unnecessary power
consumption.

I have not given this a lot of thought, but I believe you can use two
FFs (with resets) to detect the start/stop conditions and maintain a
state of disabled/enabled.

The start FF is clocked on the falling edge of SDA with SCL on the D
input. This FF will be set on a start condition. The stop FF will be
clocked on the rising edge of SDA with SCL on the D input. This FF will
be set on the stop condition. The start FF being off will hold the stop
FF in reset. The stop FF being set will reset the start FF. So the
sequence will be;

1) both FFs clear
2) on start, the start FF is set and the rest of the circuit is enabled
3) on stop, the stop FF is set which clears the start FF
4) the start FF being cleared also clears the stop FF

I had something a little different, but not far off from your suggestion.
Think masking off one signal with the other.

The only issue I can see with this design is that the stop FF will
generate a reset pulse determined by the time it takes to reset both FFs
plus the routing. Some people would object to this saying it may
violate the timing requirements of your logic. If so, you may want to
use the LUT or the OR array with the FF to add some extra delay. In
general this should work ok since it is basically self timed logic.

On the other hand, using a synchronous design should not consume much
power. Unless you are going for power below 100 uA, a low power CPLD
(like the coolrunner) should be able to run at 1 MHz (fast enough for
most I2C chips at 400 kb/s) with power at that level.

I won't go into the proprietary details, but I'm doing this work for an
SoC design that might be battery powered in some applications. My boss
is keen on reducing power consumption during a standby mode.

I also apologize if I don't get into specifics about my planned design
that might explain my problems. As with many in these NG's, I work at
a large company that considers the product I produce confidential. If
this works well, I (personally) wouldn't be averse to submitting this
as an open source Verilog block. However - I'd have to make sure this
is OK with my employer.

Yu-Ping Wang
Berkeley, California

 

[Uwe Bonnes]

srinivas turaga <srinivas_turaga@indiatimes.com> wrote:
: Hi all,


: can any tell what could be its equivalent in verilog.
: i want to know what is exact verilog equivalent to weak high 'H' in vhdl.


: entity pullup is

: port (.........
: ..........
: x: out std_logic
: ............
: ...............

: begin

: ...........

: if y ='1' then
: x<='1'
: else
: x<='z';

: end if

: ...........................
: ........................


Try
wire x;
pullup(x);

or
tri1 x;

Hope this helps
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

 

[Asher C. Martin]

cuteworm@wildmail.com (walter) wrote in message news:<36659e9e.0306180744.1756095@posting.google.com>...

Hi,

Is there is any Verilog model for PLL?
I tried the google search.
But they are not really related to what I need.

Hi,

Altera has a FREE PLL model available when you install the Quaruts II
Web Edition Software.

https://www.altera.com/support/software/download/altera_design/quartus_we/dnl-quartus_we.jsp?xy=qw1_wdl

Go to the /quartus/eda/sim_lib/ dir and type "grep pll *.v"

Take care,
>Asher<