need a cheap student edition FPGA

[Ralf Hildebrandt]

sirisha wrote:

can u give some more ideas of this project.difference between ripple
and carry look ahead adders.

This is teached in every course about basic digital circuit techniques.
If you missed lecture, search the internet. It took me 5 Seconds to find
some helpful pictures and a text about this topic. I took
http://images.google.com with search string "Carry Ripple Adder" and
found
http://images.google.com/imgres?imgurl=http://www.seas.upenn.edu/~ee201/lab/CarryLookAhead/lab4b_fig4.gif&imgrefurl=http://www.seas.upenn.edu/~ee201/lab/CarryLookAhead/CarryLookAheadF01.html&h=390&w=475&sz=8&tbnid=qPy3DD_nI0EJ:&tbnh=102&tbnw=125&start=14&prev=/images%3Fq%3DCarry%2BRipple%2BAdder%26hl%3Dde%26lr%3D%26sa%3DN


Ralf

 

[Brian Drummond]

On 2 Nov 2004 09:46:23 -0800, kiranmandava@gmail.com (sirisha) wrote:

Prasanth Kumar <lunix@comcast.net> wrote in message news:<1099375654.3608.3.camel@localhost.localdomain>...
On Mon, 2004-11-01 at 19:54 -0800, sirisha wrote:
Arithmetic operations are among the most basic instructions in
microprocessors and many other ASICs.
In this class project, we design 2 32-bit addition/subtraction units,
one uses straight simple ripple-carry algorithm and the other uses
carry-looked-ahead algorithm.

can u give some more ideas of this project.difference between ripple
and carry look ahead adders.

Best online introduction I have found was some course notes from
Reto Zimmermann at ETH Zurich, downloadable from this page.

http://www.iis.ee.ethz.ch/~zimmi/arith_lib.html

- Brian

 

[Petter Gustad]

whizkid@gamebox.net (whizkid) writes:

Hi all,
after syntheising with design Compiler , I manually changed a cell
from the netlist(changed the gate strength)... How can get an SDF file
for this new netlist...using DC

You get and SDF file from your place and route tool.

Petter
--
________________________________________________________________________
Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.com

 

[Joe]

whizkid wrote:

Hi all,
after syntheising with design Compiler , I manually changed a cell
from the netlist(changed the gate strength)... How can get an SDF file
for this new netlist...using DC
thanks
whizkid

Start DC, setup your libraries, read in the verilog netlist file,
setup your wireload models (or even the original constraints you used),
then you should be able to write out a SDF file. But then, as Petter
mentioned, it is better to get SDF output from layout extraction.
Output from DC is not very accurate (since wire delay is modeled
by wire load model).

Joe

 

[Tom Verbeure]

Your answer is not correct. How could the synthesizer magically create
a clock that's 8 times faster than the original clock?

The synthesizer will unroll the loop and basically create 8 conditional
incrementors and then start optimiziming away whatever it can.

always @(posedge clock) begin
count_zeros = count_zeros+1;
if (array[0] = 0) begin
count_zeros = count_zeros+1;
end
if (array[1] = 0) begin
count_zeros = count_zeros+1;
end
.....
end


The end result is that you will use rougly 8 times the amount of logic
compared to the case where you calculate the number of zero bits in 8
cycles.

Tom

 

[glen herrmannsfeldt]

Neeraj wrote:

First, a little context. A friend of mine wanted to design a
synthesizable circuit which would count the number of consecutive zeros
in a byte in ONE clock cycle (the byte in question being known
beforehand). His solution used a for loop in the following manner:

(snip)

Now, the question he asked me was: If the for loop gets synthesized to
a counter, what clock does it work on? In other words, what signal does
the counter use as a reference to increment its value?

The name of this circuit is a priority encoder, given a binary
number it will find the first '1' bit. The loop will be
expanded as combinatorial logic, proportional to the maximum
number of iterations. About half the logic goes away in the
synthesizer as redundant, though.

For larger than eight bits you can combine multiple levels
of encoders. Well, you should also generate a valid signal,
that there were any ones at all in the input. Then you
can nest them, using the valid inputs for the next level and
select the outputs of the appropriate one for the lower bits.
A little less logic and a lot faster.

-- glen

 

[Jahagirdar Vijayvithal S]

* Neeraj <neeraj.venkat@wipro.com>:

Hi everyone,
First, a little context. A friend of mine wanted to design a
synthesizable circuit which would count the number of consecutive zeros
in a byte in ONE clock cycle (the byte in question being known
beforehand). His solution used a for loop in the following manner:
Personally I wont recommend using for loop because some synthesis tools

generate logic with an order of magnitude higher gatecount for a
forloop based implementation compared to using the equivalent case
statement based implementation.

SNIP

Now, the question he asked me was: If the for loop gets synthesized to
a counter, what clock does it work on? In other words, what signal does
the counter use as a reference to increment its value?
My answer was that the logic synthesizer would be smart enough to
create a signal that basically would be 8 times the clock frequency
How? A general thumbrule for predicting the behaviour of any tool is to

ask "If I were to do it based on the inputs given to the tool how can I do it?"
The answer to this question may not differ significantly from what the
tool does.

(since it needed to increment eight times in one clock).
What I'm wondering is, is my answer correct? Would the logic
synthesizer actually be astute enough to generate the required clock?
Thanks for any help/ comments,
Ciao.

Regards

Jahagirdar Vijayvithal S

 

[glen herrmannsfeldt]

Jahagirdar Vijayvithal S wrote:

(snip regarding for loop in a priority encoder)

Personally I wont recommend using for loop because some synthesis tools
generate logic with an order of magnitude higher gatecount for a
forloop based implementation compared to using the equivalent case
statement based implementation.

I suppose a priority encoder could be done with verilog's
case statements, but I don't think it would look very good.

But I do agree that many things that might be done with
a for loop probably should not be. If one really wants a loop,
as opposed to the expansion of unrolling the loop, it should be
done differently.

If the different cases are all exclusive, then I might believe
that switch/case is better than for/if.

-- glen

 

[glen herrmannsfeldt]

Adnan Aziz wrote:
(snip)

- Q2. shouldn't DRAM writes be faster than reads? (the logic being
that in reads, the bitline is driven by the trench capacitor, but in
writes the bitlinehas an active driver. perhaps the reason has
something to do with senseamp logic compensating for the slow read.)

Since read is destructive, and it has to write it back anyway, yes,
it would seem that writes should be faster. For a synchronous system,
though (did you say SDRAM?) it may not matter.

-- glen

 

[Srinivas]

Hi,
I'm using a ModelSim 5.8 Xilinx Edition.Earler i was using a ModelSim
5.8 PE edition also.
I will check up on the V2001 documentation.
Rgds,
Ram

 

[Marcus Schaemann]

Adnan Aziz schrieb:

i teach a vlsi design class at UT austin, and there were a couple of
questions in my last lecture on DRAMs that i couldn't answer.

- Q1. why is the bitline pre-charged to V_DD/2 (instead of V_DD). i
thought this would be for performance, i.e., get a larger swing
quicker, but at least from a simple model, the opposite seems to be
true. perhaps it's related to power or noise?

Hello,

I think the bitline has to be pre-charged to V_DD/2 because of the
Read/Write-Amplifier (operates like a SRAM-cell).

The bitline (and another, not used bitline) is both precharged to V_DD/2
and these two are the inputs to an SRAM-cell. If now the selected DRAM
cell changes the voltage of the bitline (this change is very small
because of the small capacity of the DRAM cell compared to the capacity
of the bitline) the SRAM cell will switch to the correct maximum
voltages and thus writes back the information to the DRAM cell.

Regards,

Marcus

 

[sirisha]

Hi
Vick,
I don't want any solution of this project.Just i posted about my
project so that i can get an idea from group.Thats it.I am not
struggling with GPA and project.
Such rude affected me.Don't be like that.

Thanks for rest of them who gave ideas about this project.

Thanks
sirisha.





iamyourengineer2004@hotmail.com (Vick) wrote in message news:<c373aa10.0411090119.597553f7@posting.google.com>...

Sorry , if i sound rude, but this is just another posting where you
have cut and paste the entire Project details and asking for
solutions.

If I am not wrong this is probably another "indian female" posting it
who has taken this Computer Architecture course thinking it mite bost
her GPA but now struggling with it...

PLease do not post ur homeworks,

Thanx

 

[m]

On 11 Nov 2004 21:10:02 -0800, whizkid@gamebox.net (whizkid) wrote:

Hi Friends,
I am doing a module design in which I wanted to implement
module/block level clock gating.
If there is an enable I want the clock to reach DFFs otherwise not. I
have been coding the RTL like

always@(posedge CLK or negedge RST) begin
if(!RST) begin
MUX_IN_COUNTER <= 5'b00000;
end
else if(ENB) begin
MUX_IN_COUNTER<= n_MUX_IN_COUNTER;
end
end

All the registers are gated with ENB pin. and I am using DC & power
compiler to synthesis this RTL .
Power compiler infers a Integrated clock gate cell , as I have
specified using the set_clock_gating_style command.
Power compiler infers one clock gate cell for each verilog sub_module
(though all the flops are gated by same enable).The problem is there
are around 6000 flops in my design. and some modules contain upto 800
flops. Due to fanout load on these highly loaded ICGs(Integrated clock
gate cells) the gated clock output is getting delayed to upto 30-35%.
Due to this I am getting lot of violations in netlist simulations
though Design compiler says My timing is easily Met..

Can anyone please suggest a solution ??

One solution I am thinking about is to force DC to take more clock
gate cells(say one CG cell for 40 flops) instead of one to load 800
flops. but i dont know how to do it.. does anyone know it ??

You need to stop DC buffering the clock nets and run clock tree
synthesis after logic synthesis and power compiler. DC is not the
right tool for clock tree management.

 

[m]

On Fri, 12 Nov 2004 18:14:45 +0800, "Kelvin" <thefatcat28@hotmail.com>
wrote:

Why my NCVerilog fail to annotate these three timing checks?
Annotating SDF timing data:
Compiled SDF file: sdm_wlan_worst_max.sdf.X
ncelab: *W,SDFNET: Failed Attempt to annotate to non-existent timing check
(RECOVERY (posedge CL) (posedge CK) (64.11)) of instance

Check your verilog models and you'll see that the check is from CL to
posedge CK so there is really no (posedge CL) check. You need to
replace
(RECOVERY (posedge CL) (posedge CK) (64.11)) of instance
with
(RECOVERY CL (posedge CK) (64.11)) of instance

 

[whizkid]

mk<kal@delete.dspia.com> wrote in message

You need to stop DC buffering the clock nets and run clock tree
synthesis after logic synthesis and power compiler. DC is not the
right tool for clock tree management.

Hi,
Thanks for the reply. But I think DC is not buffering the Clock tree.
I use
constraint "set_dont_touch_network CLK" in my design. Is this what you
are reffering to ???

thanks
Whizkid

 

[Raghavendra]

srinivaserj@gmail.com (Srinivas) wrote in message news:<18bc100b.0411010045.15cec289@posting.google.com>...

Bassman59a@yahoo.com (Andy Peters) wrote in message news:<9a2c3a75.0410291311.1120a768@posting.google.com>...
srinivaserj@gmail.com (Srinivas) wrote in message news:<18bc100b.0410281919.3340e97@posting.google.com>...
Hi,
i'm declaring a register with signed values.
after processing the data,i want to display the signed values on the screen
Any suggestions on how to do this?

reg signed [FOOMSB:0];

$display("Foo is %d", foo);

-a

HI andy,
thanks for the suggestion.But this doesn't work.
I, guess , am looking for a more roundabout way of printing negative
numbers using display or any other print command.

Rgds,
Srinivas

HI,
U can.U have ur results which are signed vector.Write a function to
convert signed bit vector to integer.Then display.

Regards,
raghavendra.Sortur

 

[Mark]

Have you run the command :

set_clock_gating_style

if not, do a "man set_clock_gating_style" within dc and in particular
look at the max_fanout switch.

an example clock gating setup would be would be:

set power_preserve_rtl)hier_names true
set hdlin_no_group_register true

set_clock_gating_style -sequential_cell latch -minimum_bitwidth 4
-positive_edge_logic {integrated} -max_fanout 64 -control_point none

whizkid@gamebox.net (whizkid) wrote in message news:<edfc084c.0411112110.2db9a4fc@posting.google.com>...

Hi Friends,
I am doing a module design in which I wanted to implement
module/block level clock gating.
If there is an enable I want the clock to reach DFFs otherwise not. I
have been coding the RTL like

always@(posedge CLK or negedge RST) begin
if(!RST) begin
MUX_IN_COUNTER <= 5'b00000;
end
else if(ENB) begin
MUX_IN_COUNTER<= n_MUX_IN_COUNTER;
end
end

All the registers are gated with ENB pin. and I am using DC & power
compiler to synthesis this RTL .
Power compiler infers a Integrated clock gate cell , as I have
specified using the set_clock_gating_style command.
Power compiler infers one clock gate cell for each verilog sub_module
(though all the flops are gated by same enable).The problem is there
are around 6000 flops in my design. and some modules contain upto 800
flops. Due to fanout load on these highly loaded ICGs(Integrated clock
gate cells) the gated clock output is getting delayed to upto 30-35%.
Due to this I am getting lot of violations in netlist simulations
though Design compiler says My timing is easily Met..

Can anyone please suggest a solution ??

One solution I am thinking about is to force DC to take more clock
gate cells(say one CG cell for 40 flops) instead of one to load 800
flops. but i dont know how to do it.. does anyone know it ??


thanks
Whizkid

 

[Kelvin]

Thank you mk for your reply.

I pasted here the failed annotations, SDF file and verilog model.
What shall I do now with this kind of failures?

Thank you.





Here are the failed annotations.
---------------
ncverilog: v03.40.(s004): (c) Copyright 1995 - 2002 Cadence Design Systems,
Inc.
ncverilog: v03.40.(s004): Started on Nov 12, 2004 at 17:59:04
ncverilog
+access+r
-f sim
../../synthesis/netlist/sdm_wlan_net.v
./sdm_top_tbg.v
./include_lib.v
...............................<cut>
ncelab: *W,SDFNET: Failed Attempt to annotate to non-existent timing check
(RECOVERY (posedge CL) (posedge CK) (64.11)) of instance
tsdg.sdm_wlan.\r_sumout4_reg[2] of module SCJFD21S20.
ncelab: *W,SDFNET: Failed Attempt to annotate to non-existent timing check
(SETUP (posedge D) (posedge CK) (188.037)) of instance
tsdg.sdm_wlan.\r_sumout4_reg[2] of module SCJFD21S20.
ncelab: *W,SDFNET: Failed Attempt to annotate to non-existent timing check
(SETUP (negedge D) (posedge CK) (187.369)) of instance
tsdg.sdm_wlan.\r_sumout4_reg[2] of module SCJFD21S20.
ncelab: *W,SDFNET: Failed Attempt to annotate to non-existent timing check
(HOLD (posedge D) (posedge CK) (114.384)) of instance
tsdg.sdm_wlan.\r_sumout4_reg[2] of module SCJFD21S20.
ncelab: *W,SDFNET: Failed Attempt to annotate to non-existent timing check
(HOLD (negedge D) (posedge CK) (114.766)) of instance
tsdg.sdm_wlan.\r_sumout4_reg[2] of module SCJFD21S20.


Here is the SDF segment.
---------------
(DELAYFILE
(SDFVERSION "OVI 2.1")
(DESIGN "sdm_wlan")
(DATE "Fri Nov 12 14:28:19 2004")
(VENDOR "cs91sn_uc_core_worst_max")
(PROGRAM "Synopsys Design Compiler cmos")
(VERSION "2001.08")
(DIVIDER /)
(VOLTAGE 1.10:1.10:1.10)
(PROCESS "DEFAULT")
(TEMPERATURE 125.00:125.00:125.00)
(TIMESCALE 1ps)
.........<cut>
(CELL
(CELLTYPE "SCJFD21S20")
(INSTANCE r_sumout4_reg\[2\])
(DELAY
(ABSOLUTE
(IOPATH CK Q (364.590:364.590:364.590) (349.149:349.149:349.149))
(IOPATH CL Q (0.000:0.000:0.000) (132.917:132.917:132.917))
)
)
(TIMINGCHECK
(WIDTH (posedge CK) (231.800:231.800:231.800))
(WIDTH (negedge CK) (269.800:269.800:269.800))
(RECOVERY (posedge CL) (posedge CK) (64.110:64.110:64.110))
(HOLD (posedge CL) (posedge CK) (233.606:233.606:233.606))
(SETUP (posedge D) (posedge CK) (188.036:188.037:188.037))
(SETUP (negedge D) (posedge CK) (187.369:187.369:187.369))
(HOLD (posedge D) (posedge CK) (114.385:114.384:114.384))
(HOLD (negedge D) (posedge CK) (114.766:114.766:114.766))
(WIDTH (negedge CL) (212.800:212.800:212.800))
)
)

And here is the cell verilog mode.
------------------
`resetall
`timescale 1ps/1ps
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
`ifdef FAST_FUNC
`delay_mode_unit
`else
`delay_mode_path
`endif
module SCJFD21S10( Q, CL, D, CK );
input CL, D, CK;
output Q;
reg notifier ;
supply1 clip_1 ;
`ifdef FAST_FUNC
`ifdef cwave
UDP_DFFQ I_00p01( N_00, CK_fjcw, D_fjcw, CL_fjcw, clip_1, notifier);
buf #1 ( Q, N_00);
buf ( CL_fjcw, CL);
buf ( D_fjcw, D);
buf ( CK_fjcw, CK);
`else
UDP_DFFQ I_00p01( N_00, CK, D, CL, clip_1, notifier);
buf #1 ( Q, N_00);
`endif

`else
`ifdef cwave
UDP_DFFQ I_00p01( N_00, CK_fjcw, D_fjcw, CL_fjcw, clip_1, notifier);
buf ( Q, N_00);
buf ( CL_fjcw, CL);
buf ( D_fjcw, D);
buf ( CK_fjcw, CK);
`else
UDP_DFFQ I_00p01( N_00, CK, D, CL, clip_1, notifier);
buf ( Q, N_00);
`endif

// TIMING CHECK NETLIST
// SDF format V2.1
UDP_EE1 ( CLe1, CL, clip_1);
UDP_EE0 ( CKe0, CK, clip_1);
and ( CLe1andDn0, CLe1, Dn0);
UDP_NE0 ( Dn0, D, clip_1);

specify
// PATH DELAY
(CL +=> Q) = (0 : 0 : 0 , 36.8 : 61.4 : 101.3);
(CK => Q) = (107.0 : 178.4 : 294.4 , 106.8 : 178.1 : 293.8);
`ifdef no_ifnone
`else
`endif

`ifdef bus_con_float_check
`ifdef dcmos
specparam BUSCHECK$ = 0;
`else
specparam BUSCHECK$ = 0;
`endif
`else
`ifdef dcmos
specparam BUSCHECK$ = 0;
`endif
`endif
`ifdef finfo
specparam
AREA$ = 198.000000,
BC$ = 7.000000,
ILF$CL = 0.00364,
ILF$D = 0.00166,
ILF$CK = 0.00228;
`endif
// Timing Checks
specparam
TCLW1_CL_CL = 67.20 : 112.00 : 184.80 ,
TCKWH2_CK_CK = 65.40 : 109.00 : 179.85 ,
TCKWL3_CK_CK = 85.80 : 143.00 : 235.95 ,
TSCL4_CL_CK = 262.35 : 437.26 : 721.47 ,
THCL5_CK_CL = 221.11 : 368.52 : 608.05 ,
TSD6_D_CK = 117.13 : 195.22 : 322.11 ,
THD7_CK_D = 86.10 : 143.50 : 236.77 ;
$width( negedge CL , TCLW1_CL_CL , 0 , notifier );
$width( posedge CK &&& CLe1 , TCKWH2_CK_CK , 0 , notifier );
$width( negedge CK &&& CLe1 , TCKWL3_CK_CK , 0 , notifier );
// SDF format V2.1
`ifdef sigstm
$setup( posedge CL &&& CKe0 , posedge CK &&& CLe1andDn0 ,
TSCL4_CL_CK , notifier );
$hold( posedge CK &&& Dn0 , posedge CL , THCL5_CK_CL ,
notifier );
$setup( posedge D &&& CKe0 , posedge CK &&& CLe1 , TSD6_D_CK
, notifier );
$setup( negedge D &&& CKe0 , posedge CK &&& CLe1 , TSD6_D_CK
, notifier );
$hold( posedge CK &&& CLe1 , posedge D &&& CLe1 , THD7_CK_D
, notifier );
$hold( posedge CK &&& CLe1 , negedge D &&& CLe1 , THD7_CK_D
, notifier );
`else
`ifdef pre_sdf
$recovery( posedge CL &&& CKe0 , posedge CK &&& CLe1andDn0 ,
TSCL4_CL_CK , notifier );
$hold( posedge CK &&& Dn0 , posedge CL , THCL5_CK_CL ,
notifier );
$setup( posedge D &&& CKe0 , posedge CK &&& CLe1 , TSD6_D_CK
, notifier );
$setup( negedge D &&& CKe0 , posedge CK &&& CLe1 , TSD6_D_CK
, notifier );
$hold( posedge CK &&& CLe1 , posedge D &&& CLe1 , THD7_CK_D
, notifier );
$hold( posedge CK &&& CLe1 , negedge D &&& CLe1 , THD7_CK_D
, notifier );
`else
$setup( posedge CL &&& CKe0 , posedge CK &&& CLe1andDn0 ,
TSCL4_CL_CK , notifier );
$hold( posedge CK &&& Dn0 , posedge CL , THCL5_CK_CL ,
notifier );
$setup( D &&& CKe0 , posedge CK &&& CLe1 , TSD6_D_CK ,
notifier );
$hold( posedge CK &&& CLe1 , D &&& CLe1 , THD7_CK_D ,
notifier );
`endif

`endif
endspecify
`endif // end of FAST_FUNC
endmodule





"mk" <kal@delete.dspia.com> wrote in message
news:mdl9p0tcocvg0jpukn2etofcsm65kfhc4i@4ax.com...

On Fri, 12 Nov 2004 18:14:45 +0800, "Kelvin" <thefatcat28@hotmail.com
wrote:

Why my NCVerilog fail to annotate these three timing checks?
Annotating SDF timing data:
Compiled SDF file: sdm_wlan_worst_max.sdf.X
ncelab: *W,SDFNET: Failed Attempt to annotate to non-existent timing
check
(RECOVERY (posedge CL) (posedge CK) (64.11)) of instance

Check your verilog models and you'll see that the check is from CL to
posedge CK so there is really no (posedge CL) check. You need to
replace
(RECOVERY (posedge CL) (posedge CK) (64.11)) of instance
with
(RECOVERY CL (posedge CK) (64.11)) of instance

 

[john jakson]

johnjakson@yahoo.com (john jakson) wrote in message news:<adb3971c.0411130833.54f3b07@posting.google.com>...

adnan_aziz@hotmail.com (Adnan Aziz) wrote in message news:<dbf9db48.0411091450.2ce50019@posting.google.com>...
i teach a vlsi design class at UT austin, and there were a couple of
questions in my last lecture on DRAMs that i couldn't answer.

snipping

Forgot to add that charging to VDD/2 uses half the power v VDD
precharging, ie in any driven block, all the bitlines will cycle
through VDD/2 to VDD or VSS and back to VDD/2. But in the VDD full
precharge designs, half the bitlines must cycle the full supply. 2/4
<< 1. I'm not even sure if it needs to be exactly VDD/2 either, as
long as paired bitline lines have same V and are near to the mid
level.

Also after the data is fully amplified, the bitlines need to be
reequilibrated to the ref VDD/2, which is trivial, just short the 2
bitlines after wordline is low and let charge sharing do the work, no
current needed from the supplies. This can be very quick as a large
nmos switch can be packed between the 2 lines and doesn't need fat
metal VDD supply. The sense amp is where the heavy I tracking would
be. In the older VDD ref designs, there would be a large I spike as
the '0' bitlines had to be recharged to VDD with no internal C to draw
I from, ie a large VDD I spike and also fatter supplies around the
chip to meet the migration limit.

I also suspect that if all the bitlines are typically near VDD/2 most
of the time except during the brief bank selected cycles, then the
stress on the unselected row line devices is minimized and also less
subthreshold leakage.

Absolutely no thanks needed

Hope that helps,

John Jakson
johnjakson_usa_com

(unemployed old time VLSI circuit designer that sometimes wouldn't
mind being asked to design chips again)

 

[Jim Wu]

Hi,

Well, let me know if you figure this one out. I had
a similar issue -- I wanted a Verilog simulation to
write out a TIFF file. I couldn't find a way to write
out a binary file, so wrote out ASCII data values to
text file and then post-processed it into a binary
TIFF file using a small program I wrote in C.

The attached code is kind of kludge, but it works, with modelsim 5.8e
anyway.

HTH,
Jim
jimwu88NOOOSPAM@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips



module wr_bin ();

reg [7:0] data;

integer fd;
integer i;

initial begin
fd = $fopen("test.bin", "wb");

for (i = 0; i < 256; i = i + 1) begin
data = i;

if (data == 0) begin
$fwriteb(fd, "%u", data);
$fseek(fd, 1, 0);
end
else
$fwriteb(fd, "%c", data);
end

$fclose(fd);
$display("Done");
$finish;
end

endmodule