need a cheap student edition FPGA

[glen herrmannsfeldt]

Essen wrote:

I'm confusing about wire and reg type in verilog.
In case statement, if i replace output "reg" with "wire",
is there different between the result?

The way I remember it is that reg's keep their value
when they are not being assigned, but wires must be
continuously driven. Use wires with continuous
assignment statements, and to connect between modules.

I think that anything assigned in an always block
should be a reg. That is, that behavioral model is
being used.

In most cases, it won't compile if you use the wrong one.

-- glen

 

[Steve]

Srinivas wrote:

Hi,
I'm looking to integrate a FPGA based program into a PC based
application.
I understand i need to write a serial interfacing code on the FPGA
side and an API on the PC side,considering i intend to use a RS 232
serial interface bet'n the PC and the FPGA board.
I need help regarding the PC side API programming.I'll be using a 'C'
program and would like to call the FPGA based functions.
Can anyone suggest how i go about this?any references?

TIA.
Srinivas

Srinivas,

Are you referring to programming the serial port under windows? Then see

http://msdn.microsoft.com/library/default.asp?url=/library/en-us/dnfiles/html/msdn_serial.asp
Oh, and try the big web secret >>www.google.com<<

If you are asking this question, then do you have a Windows toolset?
MicroShaft does have a free compiler available
http://msdn.microsoft.com/visualc/vctoolkit2003/

However, I think the debugging facilities are not there.

Here's an open sourced project that has a debugger included.
http://www.openwatcom.org/product/features_content.html
There are others, like cygwin.

Or are you referring to distributed computing, e.g. RPC (Remote Procedure
Call). In which case, I can't find references specific to FPGAs. Nor have
I heard of formal RPC implementations WRT FPGAs. Hopefully, someone
else has and thus give you a better answer if this is your question.

If your application is simple enough, you should be able to derive some
simple message passing on the serial line to call your FPGA C routines.
Done that one many a time myself.

HTH, Steve

 

[Nils Strandberg]

Srinivas wrote:

Hi,
I'm looking to integrate a FPGA based program into a PC based
application.
I understand i need to write a serial interfacing code on the FPGA
side and an API on the PC side,considering i intend to use a RS 232
serial interface bet'n the PC and the FPGA board.
I need help regarding the PC side API programming.I'll be using a 'C'
program and would like to call the FPGA based functions.
Can anyone suggest how i go about this?any references?

TIA.
Srinivas
Depends on what OS you are running on the PC. If Linux look for ioperm

(just google), if windows look for inpout32.dll. There are probably a
lot of other choices, but these worked for me.
The downside is that a Linux program using ioperm has to be run as root
or setuid root, which of couse is a security risc.
/NS

 

[Joe]

Srinivas wrote:

Hi,
I'm looking to integrate a FPGA based program into a PC based
application.
I understand i need to write a serial interfacing code on the FPGA
side and an API on the PC side,considering i intend to use a RS 232
serial interface bet'n the PC and the FPGA board.
I need help regarding the PC side API programming.I'll be using a 'C'
program and would like to call the FPGA based functions.
Can anyone suggest how i go about this?any references?

TIA.
Srinivas

Goto LCC for Windows web page:
http://www.cs.virginia.edu/~lcc-win32/

In Free download section you can find the Windows API Documentation.
I havn't check if this document have the API descriptions for serial
port but I guess it should be in it. Even if it doesn't it is still a
good reference for Windows programming.
Note: Not suitable for .NET environment.

Joe

 

[glen herrmannsfeldt]

Steven Sharp wrote:

(snip)

A reg is written to in procedural code, like a variable
in a programming language. It holds its value between
writes. It may be written in many places, and just holds
the last value written.

(snip)

Originally, regs were intended to represent register
elements in the design. However, it is quite possible to
use coding styles where they are only written by one
always block, and the always block is coded so that it
behaves much like a continuous assignment. In this case,
a synthesis tool will synthesize them into wires, instead
of registers. But that doesn't make them wires; it just
makes them regs being used in a way that mimics wires.

(snip)

As the OP asked about CASE, consider:

reg out;
always case(select)
0: out=in0;
1: out=in1;
2: out=in2;
3: out=in3;
endcase

As far as verilog is concerned, this statement changes
the value of out when select, in0, in1, in2, or in3 change,
and otherwise out keeps its value due to it being reg.

Note also that with some variables in the sensitivity
list,

reg out;
always @(select) case(select)
0: out=in0;
1: out=in1;
2: out=in2;
3: out=in3;
endcase

in simulation out will only change when
select changes, but as synthesized logic it
will generate an ordinary multiplexer. This
can be confusing when the simulation performs
differently than the real hardware.

-- glen

 

[Peter Seng]

Hi,
I'm looking to integrate a FPGA based program into a PC based
application.
....

....

Hello,

is serial communication a must?
If not you could use the PC parallel port (parport macro and associated
software) and transfer data at 500KBytes/sec, no special semiconductors
needed.
Free sources available.
see:

http://www.xilinx.com/publications/xcellonline/xcell_45/xc_pdf/xc_seng45.pdf

http://www.seng.de/dlk_interface_.html

http://www.seng.de/dlk_.html



with best regards,

Peter Seng


#############################
SENG digitale Systeme GmbH
Im Bruckwasen 35
D 73037 Goeppingen
Germany
tel +7161-75245
fax +7161-72965
eMail p.seng@seng.de
net http://www.seng.de
#############################

 

[John_H]

"John_H" <johnhandwork@mail.com> wrote in message
news:_Gaed.18$OL5.2086@news-west.eli.net...

Another neat benefit in this long-division style form is that rounding can
be included by shifting half the numerator into the division a bit at a
time
in the LSbit of the add/subtract stage.

Ooops... Make that "shifting half the denominator"

N/D + 0.5 = (N+D/2)/D

 

[John_H]

"weizbox" <mwiesbock@gmail.com> wrote in message
news:335c6753.0410221116.76714a70@posting.google.com...

Hello,

Im trying to get my 50MHz clock down to 20MHz and am having some
problems getting what I want done. Basicly I want to run a loop on
every clock edge of my 50MHz clock, posedge and negedge. Is there a
way to do this?


The reason why I want to run on every edge is for the timing of it to
get a 20MHz clock out of it. The pulses I will be making on the 20MHz
clock output will not have a 50% duty cycle. Rather, I plan to make
the pulses 40ns high instead of the normal 50ns, and the low state
last for 60ns since this will sync up with my 50MHz clock nicley
having 20ns pulses. Im going to be triggering on the rising edge of
the 20MHz output clock so the falling edge does not matter as much is
its 10ns short.

Perhaps it would be better to enable every 2 or 3 clocks (50% mix) then have
the interface that runs at 20 MHz rearrange the data appropriately. You end
up with a single clock design with multi-cycle paths that only need to
achieve 25 MHz and you maintain the 20 MHz interfaces you appear to so
keenly desire.

If you want to run on "both edges" you'd need to either double up to 100 MHz
and use one edge direction or use a device that supports dual-edge
operation. Not too many out there.

 

[Martin Schoeberl]

Hi,
I'm looking to integrate a FPGA based program into a PC based
application.
I understand i need to write a serial interfacing code on the FPGA
side and an API on the PC side,considering i intend to use a RS 232
serial interface bet'n the PC and the FPGA board.
I need help regarding the PC side API programming.I'll be using a 'C'
program and would like to call the FPGA based functions.
Can anyone suggest how i go about this?any references?

perhaps this few lines of C can get you started (if you're using Windows):

DCB dcb;
HANDLE hCom;
DWORD dwError;
BOOL fSuccess;

//
// open serial line
//
hCom = CreateFile(argv[argc-1],
GENERIC_READ | GENERIC_WRITE,
0, /* comm devices must be opened w/exclusive-access */
NULL, /* no security attrs */
OPEN_EXISTING, /* comm devices must use OPEN_EXISTING */
0, /* not overlapped I/O */
NULL /* hTemplate must be NULL for comm devices */
);

if (hCom == INVALID_HANDLE_VALUE) {
dwError = GetLastError();
printf("error\n");
exit(-1);
}


fSuccess = GetCommState(hCom, &dcb);

if (!fSuccess) {
printf("error\n");
exit(-1);
}

//
// set properties
//
dcb.BaudRate = 115200;
dcb.ByteSize = 8;
dcb.Parity = NOPARITY;
dcb.StopBits = ONESTOPBIT;

/* use RTS/CTS handshake */
dcb.fOutxCtsFlow = TRUE;
dcb.fRtsControl = RTS_CONTROL_ENABLE;

dcb.fOutxDsrFlow = FALSE;
dcb.fDtrControl = DTR_CONTROL_DISABLE;
dcb.fDsrSensitivity = FALSE;

fSuccess = SetCommState(hCom, &dcb);

if (!fSuccess) {
printf("error in SetCommState\n");
exit(-1);
}

// write a single byte
WriteFile(hCom, &data, 1, &cnt, NULL);
// read a single byte
ReadFile(hCom, &c, 1, &cnt, NULL);

Martin
----------------------------------------------
JOP - a Java Processor core for FPGAs:
http://www.jopdesign.com/

 

[Prasanth Kumar]

On Thu, 2004-10-21 at 04:01 -0700, Srinivas wrote:

Hi,
I'm looking to integrate a FPGA based program into a PC based
application.
I understand i need to write a serial interfacing code on the FPGA
side and an API on the PC side,considering i intend to use a RS 232
serial interface bet'n the PC and the FPGA board.
I need help regarding the PC side API programming.I'll be using a 'C'
program and would like to call the FPGA based functions.
Can anyone suggest how i go about this?any references?

TIA.
Srinivas

It would depend on your operating system. If it is Windows, then there
are a couple helpful documents in Microsoft's MDSN site. Search for
"Serial Communications C" or something like that. It will probably take
2 to 3 pages of code to setup the serial channel.

 

[Eyck Jentzsch]

HI Andy,
interactively you can do 'Edit text' (available in the context menu in
the signal pane). Internally an expression gets created and shown:

set expression simulator:::top:bla
if {[condition find -match exact -name Test] == {}} {
condition new -name Test -expr $expression
} else {
condition set -using Test -expr $expression
}
HTH

-Eyck

 

[Nils Strandberg]

Ensoul Chee wrote:

In my design, I have two clocks through a MUX connect to a DFF/CLK

I hope to know does it have any disadvantages on this kind of design?

Thanks in advance.

If you plan to switch between the two clocks during operation and not
just statically select one at power up than it gets tricky. During the
switch over you can get a clock pulse that is too short for the DFF, You
need a state machine that makes sure you never shorten the pulse, just
stretch the pulse at switch over. I have seen both PLDs and FPGAs just
fail at switch over when only a mux was used. Had to be powered of to
get back to working.

/NS

 

[Allan Herriman]

On 26 Oct 2004 21:23:32 -0700, raghurash@rediffmail.com (Raghavendra)
wrote:

Hi all,
I wanted to know the difference between Blocking and Non-blocking
assignments.Is it similar to signal and variable assignments in VHDL?

The other way around.

Verilog VHDL
= := blocking, assignment happens immediately
<= <= non-blocking, assignment happens later

In Verilog, both types of assignments can be applied to the same reg
(although your synthesiser may reject it), whereas in VHDL := can only
be applied to variables and <= can only be applied to signals.
This can lead to interesting bugs (that will trap someone familiar
with VHDL).

Regards,
Allan

 

[Waseem]

Srinivas wrote:

Hi,
i've declared a register to hold signed integers (negative values are
present too)
I want to display these negative values on screen.am using ModelSim to
simulate my program.
any help's appreciated.

Srinivas

Hi,
Change your radix to decimal i.e. in the Modelsim wave window select
the signal , do a right mouse click and select radix and then decimal.


cheers

Waseem.

 

[pnguyen]

hi,
I am having the same problem.
Did anyone get an answer for this ?
Thank you very much,
Phil

 

[rickman]

HDL Book Seller wrote:

*** VHDL Coding Styles and Methodologies, 2nd ed -- 66% off!
Comprehensive VHDL reference text by Ben Cohen, noted VHDL guru
Sale price: $52.00 (save $99.50 off the regular Amazon price!)
http://s1.amazon.com/exec/varzea/ts/exchange-glance/Y03Y5393346Y4012685/002-2864309-3424823

Anyone have this book? How do you like it? I think the "regular" price
is a bit absurd, but the $52 price seems typical for a VHDL book. I
know that Ben Cohen is an expert at VHDL and helped write the standard.
But I don't know if his books are good.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[B. Joshua Rosen]

On Sat, 30 Oct 2004 09:06:49 -0700, Bob S. wrote:

Hello. Does anyone know were I can find the old BYTE magazine GPIB to
centronics printer interface article. (circa 1979 +/- 4 years)

Regards, Bob S.

Try a library, remember those. That's what we all used before Google.

 

[Peter A Forbes]

On Sun, 31 Oct 2004 07:33:26 -0500, "B. Joshua Rosen" <bjrosen@polybus.com>
wrote:

On Sat, 30 Oct 2004 09:06:49 -0700, Bob S. wrote:

Hello. Does anyone know were I can find the old BYTE magazine GPIB to
centronics printer interface article. (circa 1979 +/- 4 years)

Regards, Bob S.

Try a library, remember those. That's what we all used before Google.

I remember going to the University in Phoenix Az in 1984 while on a trip over to
the US, they had an excellent facility which outsiders could use after a simple
registration.

They had microfilmed archives, you could 'hire' the reader and printer for $10
or something similar.

Peter

 

[Stephen Williams]

John_H wrote:

Declarations are always outside of procedural blocks.

Actually, that's not true.

initial begin :name_block
reg [11:0] MyReg = 12'head;
... other stuff...;
end

The distinction is that the block is *named*, as that creates a
scope that can contain these things. Whether that is a good idea
or not is in the eyes of the beholder.

You can put localparams, parameters and named events there too.


--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."

 

[Kai Harrekilde-Petersen]

whizkid@gamebox.net (whizkid) writes:

Hi all,
what is the max frequency you have achieved with TSMC 18um library.
I an trying to synthesise a design at 528Mhz(1.8ns). Design Compier
results shows that the synthesis timing constraints were met. But when
I do netlist simulations I am getting 1000's of timing violations...I
checked the verilog simulaton model for the library and found that the
setup and hold checks are done in the library for 1ns ... ie for a
clock edge I need 1+1 ns for just satisying the setup hold
constraints... well my doubt is why the DC tool says the timing
constraints are met.. do you have any idea.

Sounds like you haven't backannotated the netlist with SDF.


Kai
--
Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>