need a cheap student edition FPGA

Hi,
I have the same problem of Ted in the AMS simulation with
Cadence(F*,BADOPT: unknown or ambiguous options (-ams)). Can you send me
your tutorial? Thanks
 
Hi,
I have the same problems when running ncvlog. have you find a possible
solution? (sorry for my english)
Besides when i write a module in verilogams from icfb library manager , I
have another error a window say to me to find another ncvlog executable
command. thanks
 
pini wrote:
Can someone who uses pcisim post a simple example of its usage. A
simple c file and a compilation script.
Click to expand...
Turns out I *do* have a simple example lying around. Try here:

<ftp://ftp.icarus.com/pub/eda/pcisim/examples/test_mem.tar.gz>

Other examples (or patches to that one) are welcome.

--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
 
This problem is generally known as (static) elaboration.
It's not an easy problem to solve, but it happens in a variety of tools (even though they might not output the 'flattened' form).
One thing to consider is that in order to 'flatten' the Verilog design, you need to unroll generate-loops, and that means that you
need to propagate the values of parameters all the way down from top level to bottom. That also means you need to know the top-level
design, which means that the design must be complete.

Any way, I'm pretty sure that most simulators build a statically elaborated form of the Verilog design, so I would ask VCS and
ModelSim if they can output such a flattened description.
You might be out of luck though, since 'static' elaboration is not the only way (and not an efficient way either) to build a
uniquified model of any HDL design.
Design Compiler does RTL elaboration, which has different objectives, and likely does not build a static model first. But it does
not hurt to ask Synopsys..

Good luck

Rob



"Varun Jindal" <varunjindal@yahoo.com> wrote in message news:a132b4b3.0409140117.2e3a0824@posting.google.com...
hello,
i am looking for a tool, which can flatten my verilog design,

i dont require the various heiarchies in the design and want to
flatten it into single top module design.


is anybody aware of such options in any available tool !?

thanks in advance,
regards
Varun.
Click to expand...
 
If you want to use 'storage' of constant values (like a ROM), why not use parameters or even `define's of the constants.
The two-dimensional array 'reg' will be initialized as a variable in a synthesis tool (and also in a simulator),
which most certainly requires more memory/cpu-time than constants (parameters/`defines).

Rob

"weizbox" <mwiesbock@gmail.com> wrote in message news:335c6753.0410130851.49e2dd1a@posting.google.com...
Hello,

Im trying to set up a program to do basic storage of data on my fpga.
I want to be able to flip my switches in a certain way in order to see
the LEDs in the same way, but by getting the LED values from the
registers that i initialy set them to.
So far this is what I have and for some reason when I run PACE it only
gives me the LEDs to assign, but not the clock or the switches.

module main(clk, switch, led);

input clk;
input [7:0] switch;
output reg [7:0] led;

reg [7:0] array [7:0]; //--my array 8x8

initial //--Set defualt values in my array
begin
array[0] = 8'b00000001 ;
array[1] = 8'b00000011 ;
array[2] = 8'b00000111 ;
array[3] = 8'b00001111 ;
array[4] = 8'b00011111 ;
array[5] = 8'b00111111 ;
array[6] = 8'b01111111 ;
array[7] = 8'b11111111 ;
end

always @(posedge clk)
begin
case (switch) //--Reads Switch status and applys led value from array
8'b00000001 : led = array[0];
8'b00000011 : led = array[1];
8'b00000111 : led = array[2];
8'b00001111 : led = array[3];
8'b00011111 : led = array[4];
8'b00111111 : led = array[5];
8'b01111111 : led = array[6];
8'b11111111 : led = array[7];
default : led = 8'b00000000;
endcase
end

endmodule


Besides the array situation, why isnt this accepting the clk and
switch values as inputs in PACE when they are clearly used in the
program?

Thanks as always!
-Mark
Click to expand...
 
Essen wrote:
Hi All,

Can anyone give me some adive about following code ?

reg A;
reg B;
wire en;

assign C = en && (A != B); // (1) logical AND
assign D = en & (A != B); // (2) bitwise AND

which one is better ? (1) or (2) ?

Thanks for any suggestion!
Hi
Click to expand...

In this case both are correct. Because A, B and en are considered as
boolean that is., single bit.

If you go with multiple bit operands, then you will find a difference.

Thanks and regards
karthikeyan
TooMuch Semiconductor Solutions, Bangalore.
 
Thanks for your answer,I have 3.4 version of ncvLog I think that it's
impossible to compile a VerilogAMS module.
It's also possible to make modules in verilogA with analog input and
digital output(to interface with verilog HDL module)? THANKS A LOT!!!!
 
Maybe you have your bits/row mixed up.
The "reg [7:0] array [3:0];" is 4 rows of 8 bits each. Verilog2001 allows
complete access to all bits so a read for bits [5:2] of row 2 would
reference array[2][5:2]. Note that the 5:2 range corresponds to the bit
width [7:0].

Verilog2001 is slow to have full compliance. One tool vendor has
multi-dimensional bit select supported (array[2][5]) but not part select
(array[2][5:2]). The original Verilog (1995) doesn't allow either a bit
select or a part select requiring the indirect reference that "Verilog Man"
mentioned. Verilog2001 should.

"weizbox" <mwiesbock@gmail.com> wrote in message
news:335c6753.0410131149.183377e9@posting.google.com...
Hello,

Ive been looking around online and thus far havent found a good
reference for this, how would I read/write to different parts of an
array in verliog?

Example: I have "reg [7:0] array [3:0]", how would I read/write to
bits [3:0] in row 4? If I could get my program up and running I could
easily test this out easier, but for some reason it isnt taking my
inputs, but thats another issue.

Thanks,

-Mark
Click to expand...
 
If you want "pulses per second" and you can discern the pulses, I don't know
what else you're trying to achieve.

If you need a period measurement and not pulses per second straight division
may be needed, implemented manually or as a core.
If you want a reciprocal, a lookup can provide a very good starting point.
If the lookup value isn't resolute enough, you can do some math to start
from the lookup value and get superb resolution.

It's a question of balancing the resolution and readout time with the pulse
repetition or period. It's not a simple question to answer.

If you have FPGA space and need real division, check out the vendor website
for IP math cores or look at Opencores.org.

Just some thoughts.

"weizbox" <mwiesbock@gmail.com> wrote in message
news:335c6753.0410150624.57bb8de@posting.google.com...
Have a counter that counts the pulses.
Have a second counter that counts through 1 second.
When the second counter hits 1 second, transfer the pulse count to a
holding
register and clear the count.

For the second counter, a countdown is easier; when the registered value
goes negative, load the counter with clk_speed-2.

Beware the timing problems crossing between two clock domains. A clean
way
to work is to detect the rising pulse edge in the 50MHz clock domain and
use
this edge as the pulse counter increment.


John,

This, I have already done, but what Im working with now is multiple
signals coming into one line and need to seperate them. All that I am
getting in the end is the time between one certain pulse and one that
matches the relativly same amplitude and pulse width. The counter
works well with one, but I cant set it up for multiple signals. Any
ideas?

-Mark
Click to expand...
 
You have first to get to the line
and then to the position
so you declare the variable twice:

ex:
reg [2:0] memy [5:1]
Rr = memy [3]
Wr=Rr[1]


see what i mean ?
you cant access directly

--
Sorouche Mirmiran
http://sorouche.no-ip.org
"weizbox" <mwiesbock@gmail.com> wrote in message
news:335c6753.0410131149.183377e9@posting.google.com...
Hello,

Ive been looking around online and thus far havent found a good
reference for this, how would I read/write to different parts of an
array in verliog?

Example: I have "reg [7:0] array [3:0]", how would I read/write to
bits [3:0] in row 4? If I could get my program up and running I could
easily test this out easier, but for some reason it isnt taking my
inputs, but thats another issue.

Thanks,

-Mark
Click to expand...
 
"generate" statement is supported in verilog-2001. Google it and you should
be able to find plenty of examples.

HTH,
Jim
jimwu88NOOOSPAM@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips


"Sunita Jain" <sunitajain@gmail.com> wrote in message
news:9bfc40d7.0410170125.2c6d082f@posting.google.com...
Hello,
I have a small Q regarding Verilog.
Since we can't use structural and behavioral styles of modelling
together, is there any method to instantiate a component in behavioral
code. In VHDL we have what are called for-generate schemes so that
makes it easy. is there anything like this in Verilog.
Actually I wanted to create a generic shift register using D flip flop
in structural style, but that doesn't work when I give component
instantiation inside for loop...
Any reply in this regard would be of great help.
Regards,
Sunita.
Click to expand...
 
Sunita Jain wrote:

Since we can't use structural and behavioral styles of modelling
together, is there any method to instantiate a component in behavioral
code. In VHDL we have what are called for-generate schemes so that
makes it easy. is there anything like this in Verilog.
Actually I wanted to create a generic shift register using D flip flop
in structural style, but that doesn't work when I give component
instantiation inside for loop...
Click to expand...
As far as I know, there is no problem mixing structural
and behavioral styles. Well, in the same module, anyway.

I only know how to do FF's in behavioral model.

But I would like to have something similar to the PL/I %DO
preprocessor statement. %DO is executed at compile time, such
that no loop is seen by the compiler.

DO I=1 TO 10;
A(I)=B(I)+C(I);
END;

in PL/I is a real loop,

%DO I=1 TO 10;
A(I)=B(I)+C(I);
%END;

is ten assignment statements, an unrolled loop.

-- glen
 
Hi

It is possible to generate multiple module instantiations with in a
module using generate....endgenerate statements in Verilog 2001.

The complete description is available on Verilog 2001 IEEE reference guide

Example:

genvar i;

generate
for(i=0; i<SIZE; i=i+1) begin:bit
xor g1 ( t[1], a, b);
xor g2 ( sum, t[1], c);
end
endgenerate

Refer IEEE reference guide.

Thanks and regards
S.Karthikeyan
TooMuch Semiconductor Solutions,
Bangalore.
 
Karthikeyan wrote:

It is possible to generate multiple module instantiations with in a
module using generate....endgenerate statements in Verilog 2001.

The complete description is available on Verilog 2001 IEEE reference guide

genvar i;

generate
for(i=0; i<SIZE; i=i+1) begin:bit
xor g1 ( t[1], a, b);
xor g2 ( sum, t[1], c);
end
endgenerate
Click to expand...

I still only have old verilog books, but I will see if
the tools support generate.

It does look much like the PL/I %DO, as I presume the
genvar i; declares a compile time variable.

One thing, though. Won't the g1 and g2 be duplicated?
I am not sure what depends on them being unique, other than
messages, but sometimes it is nice that they be unique.

-- glen
 
On Mon, 18 Oct 2004 09:35:19 GMT, glen herrmannsfeldt
<gah@ugcs.caltech.edu> wrote:

Karthikeyan wrote:

It is possible to generate multiple module instantiations with in a
module using generate....endgenerate statements in Verilog 2001.

The complete description is available on Verilog 2001 IEEE reference guide

genvar i;

generate
for(i=0; i<SIZE; i=i+1) begin:bit
xor g1 ( t[1], a, b);
xor g2 ( sum, t[1], c);
end
endgenerate

I still only have old verilog books, but I will see if
the tools support generate.
Click to expand...

If they don't, try instance arrays. They've been in the language
longer, but aren't terribly well supported either.

It does look much like the PL/I %DO, as I presume the
genvar i; declares a compile time variable.
Click to expand...
Yes.

One thing, though. Won't the g1 and g2 be duplicated?
I am not sure what depends on them being unique, other than
messages, but sometimes it is nice that they be unique.
Click to expand...
They have instance names like:

bit[0].g1
bit[1].g1

etc.

Note that it won't compile if you don't have a label after the
'begin'.

Regards,
Allan
 
On 18 Oct 2004 07:47:27 -0700, whizkid@gamebox.net (whizkid) wrote:

HI friends,
I want to assign a random value either +5 or -5 to a port . How do i
do that?
I tried $random function but it allows to assgin values between -5 and
+5 or 0 to 5 . But what i want is exactly +5 or else -5. Anyone know
how to do it ..
Click to expand...
you can say
reg r;
r = $random;
if (r) out = 5;
else out = -5;

hopefully the LSB of $random is as random as the rest :)
 
Hi,
I have a little problem with the verilog-mixed simulation, is it possible
to modify the logic level in verilogHDL with some declaration in the code?
I have seen
that in the SpectreVerilog simulation the logic level of the gates are
5V,
Is it possible to modify this value? thanks I'm waiting an answer!!thanks
a lot!
 
"Srinivas" <srinivaserj@gmail.com> wrote in message
news:18bc100b.0410210301.265232ef@posting.google.com...
Hi,
I'm looking to integrate a FPGA based program into a PC based
application.
I understand i need to write a serial interfacing code on the FPGA
side and an API on the PC side,considering i intend to use a RS 232
serial interface bet'n the PC and the FPGA board.
I need help regarding the PC side API programming.I'll be using a 'C'
program and would like to call the FPGA based functions.
Can anyone suggest how i go about this?any references?

TIA.
Srinivas
Click to expand...
As I understand you need help writing a program in C to communicate with the
serial port?! Then you'd better ask this question on a newsgroup related to
the software programming not a FPGA or Verilog news group! Also you will
need to provide some more information; at least the OS under which you are
going to run your program.

Regards
Arash
 
Srinivas wrote:
Hi,
I'm looking to integrate a FPGA based program into a PC based
application.
I understand i need to write a serial interfacing code on the FPGA
side and an API on the PC side,considering i intend to use a RS 232
serial interface bet'n the PC and the FPGA board.
I need help regarding the PC side API programming.I'll be using a 'C'
program and would like to call the FPGA based functions.
Can anyone suggest how i go about this?any references?
Click to expand...
You may want to find a good terminal emulator program rather than trying
to write your own. The last time I write code for a serial port (under
windows) it was a real PITA. But then you may be using a decent OS.
But under any OS, you will be talking to the driver, not the serial
port.

If you have to write a program, try searching on the web for source code
for a terminal emulator or similar project. There are lots of open
source projects out there.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
Srinivas wrote:
Hi,
I'm looking to integrate a FPGA based program into a PC based
application.
I understand i need to write a serial interfacing code on the FPGA
side and an API on the PC side,considering i intend to use a RS 232
serial interface bet'n the PC and the FPGA board.
I need help regarding the PC side API programming.I'll be using a 'C'
program and would like to call the FPGA based functions.
Can anyone suggest how i go about this?any references?
Click to expand...
Is serial interface a must? There are relatively cheap development
boards available with either Ethernet or USB interface. Might be easier
to start with and lot more bandwidth, too! Depends of course on your
requirements, hobby project?

Just my $0.02, HTH

J.S.

TIA.
Srinivas
Click to expand...
 
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