need a cheap student edition FPGA

[Weng Tianxiang]

On Sep 19, 9:05 pm, John_H <newsgr...@johnhandwork.com> wrote:

Weng Tianxiang wrote:
Hi Hal,
8b/10b is perfect for scrambling function. PCI-e uses 8b/10b
technology.

Scramble technology still uses randomized serial and XOR now? After 8b/
10b technology, I think other randomized XOR scramble technology is
dying out, is it right?

IBM got one patent for 8b/10b technology in 1981, Xilinx filed for 23
patents on 8b/10b implementation in FPGA on one day in 2004.

I think that IBM is really a technology leader in almost all respects
in computer industry. Xilinx is the leader of FPGA.

Weng

80B/10B is not a scrambler. It's a coding mechanism used to balance the
DC offset of the encoded stream. It's a straight encode/decode.

Don't be disappointed and frustrated for what you don't know.- Hide quoted text -

- Show quoted text -
Hi John_H,

8b/10b does the same thing as a scambler does: to balance DC offset,
but does a better job than scambler with 20% bandwidth cost.

For higher data rare, 8b/10b is the only choice. It guarantees that DC
offset is balanced between +- 1 during transmission.

Historically, currently satellite communication stations use scambler
not because scambler saves 20% bandwidth, but when satellite station
standard was established, IBM had the patent on 8b/10b that would
expire in 2001, that is the reason why PCI-e uses 8b/10b technology.

I expect 8b/10b technology will be incooperated in any new data
communication standard, but it cannot replace old standards.

Hi Hal,
Scrambler cannot be counted as a state machine in any sense.

The most important factor for a circuit counted as a state machine is
that its states are mutually exclusive and only one state is active in
any cycle.

Scrambler cannot meet the requirements. If it were, every circuit
would be counted as a state machine.

Shift registers can be counted as a state machine only when only one
bit is set or reset among all its bits. Otherwise it cannot be counted
as a state machine.

Weng

 

[Weng Tianxiang]

Hi JTW,
Your response is suggestive and I would like to see your coding to
determine if they are state machines.

I don't exclude RAM used as state machines.

If you can do it, it is better. Xilinx has an application note devoted
to the BRAM used as state machine and I read the note carefully. But I
never use their ideas to use BRAM . I don't have any idea to use the
BRAM as a tool for 10k state machines.

There are 10 millions bits of BRAM, you must also have a legitimate
reason to use so many state machines in a design. There is seldom a
design in FPGA world that would need 100k state machines for a reason.

My answer to my quiz is much larger than 100k state machines in a
finished design that is open to use for any one in the topic groups.

Weng

 

[glen herrmannsfeldt]

John_H wrote:
(snip)

80B/10B is not a scrambler. It's a coding mechanism used to balance the
DC offset of the encoded stream. It's a straight encode/decode.

You could say it that way, but if you need a modulation method
for clock recovery it can be used in place of a scrambler and
simpler modulation method.

Modulation is used for different reasons:

1) Clock recovery
2a) Band limited channel
2b) AC coupled system

Considering those, 8B/10B is not so different from a scrambler.

-- glen

 

[Shannon]

On Sep 20, 12:12 pm, Weng Tianxiang <wtx...@gmail.com> wrote:

Hi JTW,
Your response is suggestive and I would like to see your coding to
determine if they are state machines.

I don't exclude RAM used as state machines.

If you can do it, it is better. Xilinx has an application note devoted
to the BRAM used as state machine and I read the note carefully. But I
never use their ideas to use BRAM . I don't have any idea to use the
BRAM as a tool for 10k state machines.

There are 10 millions bits of BRAM, you must also have a legitimate
reason to use so many state machines in a design. There is seldom a
design in FPGA world that would need 100k state machines for a reason.

My answer to my quiz is much larger than 100k state machines in a
finished design that is open to use for any one in the topic groups.

Weng

Thanks Weng. I can sleep better now.

Shannon

 

[Hal Murray]

Hi Hal,
Scrambler cannot be counted as a state machine in any sense.

Why not? It has inputs, outputs, and internal state.
Sure looks like a state machine to me.

The most important factor for a circuit counted as a state machine is
that its states are mutually exclusive and only one state is active in
any cycle.

Which part of that does a scrambler not meet? Remember, I'm
talking about a LFSR type scrambler running in bit serial mode,
not a n 8b/10b encoder.

Shift registers can be counted as a state machine only when only one
bit is set or reset among all its bits. Otherwise it cannot be counted
as a state machine.

Huh? A shift register seems like an even simpler example of
a state machine that doesn't need a reset to do useful work.

I'm thinking of a simple serial-in, serial-out shift register,
a delay line. It's "state" is the last N bits shifted in.


If I was explaining a shift register or scrambler to somebody,
I probably wouldn't start by calling it a state machine and drawing
the classic picture of states and transitions, but it might be
handy to use tricks from state machine theory, like if it has
N bits of internal state (aka FFs) it can only have 2^N distinct
states.

--
These are my opinions, not necessarily my employer's. I hate spam.

 

[John_H]

"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message
news:8qydnY9KVevHXW_bnZ2dnUVZ_gednZ2d@comcast.com...

John_H wrote:
(snip)

80B/10B is not a scrambler. It's a coding mechanism used to balance the
DC offset of the encoded stream. It's a straight encode/decode.

You could say it that way, but if you need a modulation method
for clock recovery it can be used in place of a scrambler and
simpler modulation method.

Modulation is used for different reasons:

1) Clock recovery
2a) Band limited channel
2b) AC coupled system

Considering those, 8B/10B is not so different from a scrambler.

-- glen

It's not "so" different, but the advantages of each are different. The
items that strike me the most are that 8B/10B provides better DC balance and
scramblers provide a smoother spread of power across a wider bandwidth.

 

[Amir]

On Sep 19, 3:55 am, "comp.arch.fpga" <ksuli...@googlemail.com> wrote:

On 18 Sep., 19:17, Weng Tianxiang <wtx...@gmail.com> wrote:> Hi,
1. I am talking about GUESSING the largest number of state machines a
current finished design may have. Not ceiling.

But you do not react if someone answers your question. Can you beat
the
10k+ state machines of a smith-waterman DNA matcher?

3. A synchronous or an asynchronous reset signal is vital, either with
clear routing or a hidden within other procedures.

Again, you did not read my post. Many state machines have no reset
signal.
For example the reset signal of a JTAG controller is optional. This is
a state machine that is implemented in virtually every complex piece
of silicon out there.

Kolja Sulimma

Hi Weng and all fellow engineers,

I more or less agree with all of you on ur guesses and responses...

I dont quite understand what Weng is up to? If you wanna twist ur
question in any way to mislead us, u could do so forever, and no
answer would SATISFY u, cus there is no real question..

Are u really trying to have an answer/discussion that benefit us all,
OR u r just playing with ur words cus u probably finished clicking as
to test the modules that design engineers handed u in....?

For the sake of every one else, my share of the answer would be:

I would subdivide the question as: 1. How many FSM can fit current
chips? 2. How many FSM is appropriate for a given design? 3. How many
states within each FSM should there be?

My guess/answers:
A.1: twice as much available Registers in the chip (after considering
registers needed for other modules)
A.2: Depending on the complexity of the design, as many as required,
provided that each FSM do not exceed more than 15 states or so...(more
than 15, becomes harder to debug, and follow..)
A.3. Embedded in A.2, hence, max 15-20 states per FSM would be a best
suit based on my experience...Larger than 20, the FSM should be broken
down into 2 FSMs...

But again, as others pointed out, the whole number of FSMs can be
considered as one large FSM, cus they interact with each other through
handshake signals anyways....

Amir,

that it depends on design complexity, however,

 

[glen herrmannsfeldt]

Weng Tianxiang wrote:

(snip)

Scrambler cannot meet the requirements. If it were, every circuit
would be counted as a state machine.

There is a class of circuits call combinatorial logic. Generally
that means no state, no memory, and so no state machine.

With combinatorial logic the outputs will come to a value that
only depends on the inputs after the appropriate propagation delay.

Otherwise, yes, every circuit that has a state memory counts
as a state machine.

Shift registers can be counted as a state machine only when only one
bit is set or reset among all its bits. Otherwise it cannot be counted
as a state machine.

I don't understand this restriction at all.

-- glen

 

[Hal Murray]

A.2: Depending on the complexity of the design, as many as required,
provided that each FSM do not exceed more than 15 states or so...(more
than 15, becomes harder to debug, and follow..)
A.3. Embedded in A.2, hence, max 15-20 states per FSM would be a best
suit based on my experience...Larger than 20, the FSM should be broken
down into 2 FSMs...

It's perfectly reasonable to build FSMs with hundreds or even
thousands of states. The trick is to think of it as software
and build yourself an assembler so you can really implement it
that way.

People have been using ROMs for this type of state machine for
a long time. 256x8 ROMs were common back in the old TTL/DIP days.

That style of FSMs usually has clumps of states that don't branch.
If you draw the typical circles and arrows state diagram, you might
want to include each clump in one circle. It just takes several
cycles/states to do the "action" associated with a state transition.

--
These are my opinions, not necessarily my employer's. I hate spam.

 

[Weng Tianxiang]

"Shift registers can be counted as a state machine only when only one
bit is set or reset among all its bits. Otherwise it cannot be counted
as a state machine."

"I don't understand this restriction at all.

-- glen"

Hi Glen,
For a 4-bit shift register to be counted as a state machine, it must
have data:
"0001", "0010", "0100" and "1000" for an active high state machine, or
"1110", "1101", "1011" and "0111" for an active low state machine.

It must meet state machine requirements:
A state machine can be defined in such a scientific way:
1. All states in a state machine have their own names;
2. All states in a state machine are mutually exclusive;
3. Only one state is active in any cycle;
4. The number of states in a state machine must be 2 or more;
5. There must be clear asynchronous or a synchronous reset signal, or
hidden
procedure for the state machine. After their assertion or
initialization
the state machine must be in known initial state.

For a 4-bit shift register that has data "1100" cannot be counted as
a state machine. Even though they may be used for state machine
functions.
In such cases, they are called shift registers, not state machines.

Roughly speaking, in VHDL, it is used to be declared in the following
way:
type xxx (...);
signal StateMachine, NextState : xxx;

If you use above format to declare a state machine, the statistics
would be shown in Xilinx compilation result. And the declared state
machine would meet all above 5 requirements.

Xilinx compiler does the right thing.

Hi Amir,
My question is very clear:
"What is the largest number of state machines in a current chip
design:
1k, 10k or ... "

If you know, please give the answer and why. If you don't know and are
interested in it, please be quiet and patient, or don't join the
topics discussion if you think it is wasting your time. I will
disclose my answer at appropriate time. It is not a trivial quiz. You
may hear it before, but forget to remember to connect it with the
question.

My question is not how to design a state machine, or how many states a
state machine may have, or how many state machines a FPGA/IC can
construct. Those questions are beyond interest of my topics.

Weng

 

[Hal Murray]

For a 4-bit shift register to be counted as a state machine, it must
have data:
"0001", "0010", "0100" and "1000" for an active high state machine, or
"1110", "1101", "1011" and "0111" for an active low state machine.

That's total nonsense.

Your pattern describes a one-hot state machine. That simplifies
decoding states, but there is nothing in the rules of state
machines that says I have to use that encoding. It's common
to encode states in kludgy ways that make decoding convenient.

--
These are my opinions, not necessarily my employer's. I hate spam.

 

[glen herrmannsfeldt]

Weng Tianxiang wrote:
(snip)

For a 4-bit shift register to be counted as a state machine, it must
have data:
"0001", "0010", "0100" and "1000" for an active high state machine, or
"1110", "1101", "1011" and "0111" for an active low state machine.

It must meet state machine requirements:
A state machine can be defined in such a scientific way:
1. All states in a state machine have their own names;
2. All states in a state machine are mutually exclusive;
3. Only one state is active in any cycle;
4. The number of states in a state machine must be 2 or more;
5. There must be clear asynchronous or a synchronous reset signal, or
hidden
procedure for the state machine. After their assertion or
initialization
the state machine must be in known initial state.

There are many restricted types of state machines, usually named
after the first person to publish the description.

I would say that you have now defined the weng machine, which
is fine. That doesn't have anything to do with the state
machines that others may define and use.

You requirement on naming states reminds me of an old saying:
"If a tree falls in the forest and nobody is around to
hear it does it make any noise?"

Whether the states are named or not has no effect on
the logic. That states are mutually exclusive and
only one state active in each cycle are sort of obvious
requirements. (That doesn't restrict it to one hot
state machines, an active state is any specific
combination of the state variables.)

Also that there must be more than one state is
a reasonable restriction. Many state machines
are self synchronizing so don't need a reset signal.
Others do need one. There are some that can start
in an illegal state and never reach a legal state
without a reset. Most try not to design that way
if it is reasonable not to do so.

-- glen

 

[Weng Tianxiang]

On Sep 21, 7:07 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:

Weng Tianxiang wrote:

(snip)

For a 4-bit shift register to be counted as a state machine, it must
have data:
"0001", "0010", "0100" and "1000" for an active high state machine, or
"1110", "1101", "1011" and "0111" for an active low state machine.
It must meet state machine requirements:
A state machine can be defined in such a scientific way:
1. All states in a state machine have their own names;
2. All states in a state machine are mutually exclusive;
3. Only one state is active in any cycle;
4. The number of states in a state machine must be 2 or more;
5. There must be clear asynchronous or a synchronous reset signal, or
hidden
procedure for the state machine. After their assertion or
initialization
the state machine must be in known initial state.

There are many restricted types of state machines, usually named
after the first person to publish the description.

I would say that you have now defined the weng machine, which
is fine. That doesn't have anything to do with the state
machines that others may define and use.

You requirement on naming states reminds me of an old saying:
"If a tree falls in the forest and nobody is around to
hear it does it make any noise?"

Whether the states are named or not has no effect on
the logic. That states are mutually exclusive and
only one state active in each cycle are sort of obvious
requirements. (That doesn't restrict it to one hot
state machines, an active state is any specific
combination of the state variables.)

Also that there must be more than one state is
a reasonable restriction. Many state machines
are self synchronizing so don't need a reset signal.
Others do need one. There are some that can start
in an illegal state and never reach a legal state
without a reset. Most try not to design that way
if it is reasonable not to do so.

-- glen

Hi Glen,
"That doesn't restrict it to one hot
state machines, an active state is any specific
combination of the state variables"

I agree with your opinion.

Weng

 

[Weng Tianxiang]

On Sep 21, 9:01 pm, Weng Tianxiang <wtx...@gmail.com> wrote:
On Sep 19, 9:54 am, Shannon <sgo...@sbcglobal.net> wrote:

I gave my guess. Why haven't you responded? You told me you would
tell me the answer after I guessed. Now tell me.

Shannon

Hi Sannon,
1. It is L2 cache that uses a lot of state machines;http://
en.wikipedia.org/wiki/Cache_coherence

2. IBM/Intel uses MESI protocol (Modified, Eclusive, Shared and
Invalid);http://en.wikipedia.org/wiki/MESI_protocol

3. Please visit Intel product website to get the latest news:http://
download.intel.com/products/processor/xeon/7300_prodbrief.pdf

4. "with up to 8 MB of L2 cache per processor" and 4 cores.
It means 4*8MB = 32MB L2 cache;

5. Each 32Bytes is a cache line;

6. 32MB/32 = 1M cache lines and 1M state machines.

The final answer is:
There is at least 1M state machines in Intel chip.

a. It is available to every users in the topics groups;
b. They are written in Verilog, not in VHDL;
c. FPGA has never had a design using L2 cache.

Any more questions?

Weng

 

[MYH]

--------------------------------------------------
From: "gabor" <gabor@alacron.com>
Sent: Tuesday, February 19, 2008 9:57 PM
Newsgroups: comp.lang.verilog
Subject: Re: How to define the size of number with a macro experssion?

On Feb 17, 2:54 am, "MYH" <93501...@cc.ncu.edu.tw> wrote:
Hi.

How to specify the size of a number by a define macro expression?
For example:
---------------------------------------------------------------------
`define m 1
`define n (`m+1)

// The following line will get a compilation error in ModelSim.
// Because (1+1)'b10 is a error syntax.
reg [1:0] p = `n'b10;
---------------------------------------------------------------------

But if you change the n to `m+1, that is:
---------------------------------------------------------------------
`define m 1
`define n `m+1
---------------------------------------------------------------------
Then `n'b10 will expand to `m+1'b10.
And `m+1'b10 will expand to 1+1'b10 (This is a 32bit 1 plus a 1bit 0!)
But I really want this number: 2'b10

How do I solve this problem?

Thanks.

Is there a good reason to size the constant? Normally the assignment

Yes. If you don't assign a size to a number, and compare the number to a
variable, for example:
---------------------------------------------------------------------
module test( c, a );

output c;
input [1:0] a;

assign c = ( a == 2 );

endmodule
---------------------------------------------------------------------
then Quartus II will synthesize out a 32 bit comparator (in RTL Viewer).
This wastes the hardware resources. I only need a 2 bit comparator.

will just take the appropriate number of LS bits from the constant
anyway. So:

reg [1:0] p = 'b10;
or :
reg [1:0] p = 2;

would only take the 2 LSB's of the constant as required by the 2-bit
reg "p". But perhaps you have another case where the size of the
constant affects the expression?

Regards,
Gabor

 

...If you don't assign a size to a number, and compare the number to a
variable, for example...then Quartus II will synthesize out a 32 bit
comparator (in RTL Viewer).

This wastes the hardware resources. I only need a 2 bit comparator.

The 32-bit comparator may show up in the RTL viewer, but you can be
sure that it will be gone in the implementation. (In Quartus, select
View / Technology Map Viewer).

The RTL viewer reflects closely what you wrote. For example, if in
your HDL you add one to a register, the RTL will show that register
fed from an adder whose inputs are the same register and a constant
field of the same length with value 1. Despite this, the
implementation is a counter.

Mike

 

[Ray Andraka]

Weng Tianxiang wrote:

"Shift registers can be counted as a state machine only when only one
bit is set or reset among all its bits. Otherwise it cannot be counted
as a state machine."

"I don't understand this restriction at all.

B.S. For example, a shift register can be used in a bargraph manner so
that the states are

000001
000011
000111
001111
011111
111111

This has an advantage over the one-hot shift register state machine you
described in that it has fewer terms feeding each register. That can
make a big difference in the maximum clock rate of the state machine.

 

[Weng Tianxiang]

On Sep 25, 5:06 pm, Ray Andraka <r...@andraka.com> wrote:

Weng Tianxiang wrote:
"Shift registers can be counted as a state machine only when only one
bit is set or reset among all its bits. Otherwise it cannot be counted
as a state machine."

"I don't understand this restriction at all.

B.S. For example, a shift register can be used in a bargraph manner so
that the states are

000001
000011
000111
001111
011111
111111

This has an advantage over the one-hot shift register state machine you
described in that it has fewer terms feeding each register. That can
make a big difference in the maximum clock rate of the state machine.

Hi Ray,
OK, thank you for your example.

Your shift register is a state machine if we define different bit
patterns appeared in your example as individual states.

I have changed my mind to accept non one-hot encoding for shift
registers based on glen's suggestion.

My state machine definition is still right without any violations with
your example.

Weng

 

[comp.arch.fpga]

Weng,

you are free to invent as many technical and mathematical constructs
as you like.
BUT: It is utterly stupid to use the same name for it as a well
established construct.

Finite State Machines are extremely well understood since decades.
http://en.wikipedia.org/wiki/Finite_state_machine

And I can assure you:
In digital electronics anything that has state is a state machine.

In general:
- State machines do not need to have a reset. There are machines that
return to the reset state
if a certain input sequence is applied. I posted links to papers about
that, which you apperently ignored.
Any FPGA around has a state machine that works without reset: The JTAG-
controller.
- Names in state machine do not need to have names.
- State machines can be combined to larger machines. These are still
state machines, but the
states are not mutual exclusive anymore.
- In complexity therory an important class of state machines are non
deterministic state machines.
These can be in mutliple states at the same time. Quantum computing
provides a real world implementation for
another type of state machines that are in multiple states at the same
time.
- While state machines with a single state are not very useful, theory
becomes a lot simpler if you still allow them to be state machines.

This means that for the well establish name "State Machine" ALL OF
YOUR ASSUMPTIONS ARE FALSE!

Please find a new name for the strange thing that you are talking
about.
And please: Listen to people, and believe them. Most of this has been
posted before and you ignored it.
You are extraordinarily stubborn.

As far as your original question goes:
A set of state memories (flip-flops, memory cells) can be more or less
arbitrarily partitiones into state machines.
The extremes beeing one machine per state bit, or one big machine for
the whole chip. Both extremes often are not useful.
What you described is a central controller updating a set of state
machines in memory. It is valid to call that a set of state
machines. But if you allow for that construct, a software
implementation of Conways game of live easily beats your example
by orders of magnitude. You have two state bits for each pixel and a
central controller updating the states of the machines.

Kolja Sulimma



On 21 Sep., 21:26, Weng Tianxiang <wtx...@gmail.com> wrote:

It must meet state machine requirements:
A state machine can be defined in such a scientific way:
1. All states in a state machine have their own names;
2. All states in a state machine are mutually exclusive;
3. Only one state is active in any cycle;
4. The number of states in a state machine must be 2 or more;
5. There must be clear asynchronous or a synchronous reset signal, or
hidden procedure for the state machine. After their assertion or initialization
the state machine must be in known initial state.

 

[Weng Tianxiang]

Hi KS,
Good comments and I think it is based on good and reasonable
judgement.

I really appreciate the following comment:
You are extraordinarily stubborn. It is one of my personal
characteristics.

I really throw away all trashes into my backyard garbage bin in the
topics.

I will think a few days to give you a satisfactory answer.

Weng