need a cheap student edition FPGA

[KJ]

On Mar 18, 11:26 am, Patrick Dubois <prdub...@gmail.com> wrote:

On 18 mar, 01:36, Peter Alfke <al...@sbcglobal.net> wrote:

If for some (strange) reason you want to roll your own, [...]

One reason would be to permit the use of generics. I often use fifos
and I try to use generics whenever possible in the rest of my designs
but unfortunately, coregen fifos are not compatible with generics.

Google for lpm_fifo_dc and then ask Xilinx why they don't support EIA
standard LPM 220 components.

KJ

 

[glen herrmannsfeldt]

John_H wrote:

(snip)

Would it be valid to say that if the user doesn't need a(n almost)
full flag on the read side or an (almost) empty flag on the write side
that a FIFO design would be pretty relaxed?

I would think that if you had almost full and almost empty
delayed by a cycle or two that would work well. With
full and empty you tend to want them without delay.

-- glen

 

[Peter Alfke]

On Mar 18, 2:11 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:

John_H wrote:

(snip)

Would it be valid to say that if the user doesn't need a(n almost)
full flag on the read side or an (almost) empty flag on the write side
that a FIFO design would be pretty relaxed?

I would think that if you had almost full and almost empty
delayed by a cycle or two that would work well.  With
full and empty you tend to want them without delay.

-- glen

More precisely: FULL and EMPTY must go active "without delay", but the
process of going inactive crosses between the clock domains, and
usually involves an extra clock delay to protect against metastable
confusion.
Peter Alfke

 

[Patrick Dubois]

On 18 mar, 12:41, KJ <kkjenni...@sbcglobal.net> wrote:

Google for lpm_fifo_dc and then ask Xilinx why they don't support EIA
standard LPM 220 components.

KJ

Very interesting, thank you. My understanding is that source code was
available a while ago (edif.org) but this doesn't seem to be the case
anymore. Any idea where I could find some source code?

Patrick

 

[Patrick Dubois]

On 19 mar, 15:45, KJ <kkjenni...@sbcglobal.net> wrote:

Altera (Sim model and synthesis)
Synplicity (synthesis only)
Lattice (synthesis only)
ISE (synthesis only, .TDF files)

And that's the rub when it comes to LPM, you can't always get
simulation models from the various synthesis vendors even though they
'support' it. The resourceful designer though might see that using
the same interface that LPM uses (i.e. generics and signals) would
make for a good starting point for making their own...while grumbling
to the suppliers about their lack of sim support for a standard that
they 'support'...while they try to claim that 'their' fifo interface
is somehow superior to some others....even though it's not, their
implementation of a fifo might be better, but the interface TO the
fifo is not.

The other reality is that by making you jump through hoops with their
various wizards that purport to 'help' they lock you into their stuff
just a bit.

KJ

I found the source code that was available at edif.org through
archive.org:
http://web.archive.org/web/20031204114425/http://www.edif.org/lpmweb/more/vhdl.htm

It looks like complete source code, I'm not sure what additionnal
support I would need from vendors. It seems to me that I could just
use lpm_fifo_dc from 220model.vhd. Am I missing something?

Patrick

 

[Mike Treseler]

Patrick Dubois wrote:

I found the source code that was available at edif.org through
archive.org:
http://web.archive.org/web/20031204114425/http://www.edif.org/lpmweb/more/vhdl.htm

The internet never forgets

It looks like complete source code, I'm not sure what additional
support I would need from vendors. It seems to me that I could just
use lpm_fifo_dc from 220model.vhd. Am I missing something?

The code is synthesizable as is,
but I would at least clean up the
non-standard libraries and the
odd-ball string generics.

-- Mike Treseler

ps: here's a first cut:
http://home.comcast.net/~mike_treseler/sync_fifo.vhd

 

[FPGA]

On Mar 19, 8:46 pm, Mike Treseler <mike_trese...@comcast.net> wrote:

Patrick Dubois wrote:
I found the source code that was available at edif.org through
archive.org:
http://web.archive.org/web/20031204114425/http://www.edif.org/lpmweb/...

The internet never forgets

It looks like complete source code, I'm not sure what additional
support I would need from vendors. It seems to me that I could just
use lpm_fifo_dc from 220model.vhd. Am I missing something?

The code is synthesizable as is,
but I would at least clean up the
non-standard libraries and the
odd-ball string generics.

    -- Mike Treseler

ps: here's a first cut:http://home.comcast.net/~mike_treseler/sync_fifo.vhd

Thank you everyone for your valuable help.

 

[Morten Leikvoll]

I would suggest to use what I do:

Use a circular addr counter on both sides, make a signal that will indicate
that its 1/4 full and reclock that single signal to the other side (edge
detecting to single clock), to indicate its safe to read 1/4 of the
ramblock. To give a message back to the input clock domain, create a similar
signal on the read side telling that 1/4 is used, telling input tocontinue
to write 1/4 more data. You could be using 1/2 size partitions too, but
quads (or even smaller portions) gives you some headroom to fill more memory
while reading.
If you partition the ram into too small partitions, the reclocking of a
filled part will not work (you do not want to loose any of these signals).
You can calculate the minimum partition by comparing the clocking ration of
your domains, ensuring that every 1/n'th fill will be guaranteed to reclock.

 

[Nico Coesel]

FPGA <FPGA.unknown@gmail.com> wrote:

I wish to design a FIFO to tansfer data from a high speed clock
domain(320 MHz) to low speed clock domain(40 Mhz). I dont wish to use
the cores available from any of the vendors.

Inputs =
DataIn // 16 bit data input that is latched in on the posedge of
clkHigh when Wen is high
Wen // Write enable to strobe in the data into the register
Ren // read enable strobe to let the reg know data was read
out of the DataOut register
clkHigh // High speed clock for writing data in
clkLow // low speed clock for reading data out

Outputs =
DataOut // 16 bit data out that is changed to the next value (or
all low if nothing is yet stored inside) when Ren
goes low after toggling high based on the clkL
Full // signal goes high when all input registers are filled
up.
Empty // Goes high when nothing

How to decide on the depth of register DataOut to ensure that data is
not overwritten. The issue is that the FIFO has to have some high
speed storage capacity to allow for more data coming in then was
written out.

Any suggestions would be appreciated.

Design the entire FIFO (counters & flags logic) to run at 320MHz and
add a clock domain transfer circuit on the low frequency side.

--
Programmeren in Almere?
E-mail naar nico@nctdevpuntnl (punt=.)

 

In comp.arch.fpga FPGA <FPGA.unknown@gmail.com> wrote:

Is task in verilog equivalent to procedure in VHDL? I am trying to
convert a verilog file to vhdl.

Verilog =
// string data type
reg [8*4:1]a;
reg [8*255:0]b;

VHDL =
Is the above equivalent to
variable a : string(1 to 8*4)
variable b : string(1 to 8*255)

Just a thought..:
variable b : string(0 to 8*255)

 

[Robert Miles]

"Niv" <kev.parsons@mbda.co.uk> wrote in message
news:8ae65392-760c-4c39-85e9-abfdd1507e67@b1g2000hsg.googlegroups.com...

Hi all, we currently use VHDL for all our design & verification via
testbenches.
I have been asked to look at alternative verification methodologies,
particularly SystemVerilog.

(I've been on a PSL course a few years ago, but until now never had
the tool(s) to exploit it's use, but
people seem to think SysVerilog may be a better approach anyway.

So, what is the best book(s) to learn SV for a VHDL conversant
audience, and possibly more important,
whare can we quickly learn what SV can do for us above and beyond VHDl
testbenches.

(Cross posted to VHDL group)

Regards, Niv.

Your message arrived with no crosspost. Did you post it separately
to the VHDL newsgroup?

 

[Robert Miles]

"Niv" <kev.parsons@mbda.co.uk> wrote in message
news:8ae65392-760c-4c39-85e9-abfdd1507e67@b1g2000hsg.googlegroups.com...

Hi all, we currently use VHDL for all our design & verification via
testbenches.
I have been asked to look at alternative verification methodologies,
particularly SystemVerilog.

(I've been on a PSL course a few years ago, but until now never had
the tool(s) to exploit it's use, but
people seem to think SysVerilog may be a better approach anyway.

So, what is the best book(s) to learn SV for a VHDL conversant
audience, and possibly more important,
whare can we quickly learn what SV can do for us above and beyond VHDl
testbenches.

(Cross posted to VHDL group)

Regards, Niv.

Your message arrived with no crosspost. Did you post it separately
to the VHDL newsgroup?

 

[HT-Lab]

"KJ" <kkjennings@sbcglobal.net> wrote in message
news:1b5f41df-e273-47c0-b309-460a94735b9e@x19g2000prg.googlegroups.com...
On Apr 21, 5:11 am, Evan Lavelle <nos...@nospam.com> wrote:

You don't need to know
or write *any* HDL code to use Maia; if you can write vectors for your
module, then you can verify it.


Not to be too much of a slug, but I'm kinda missing the point I think
of this tool....

Why would I want to write test vectors (Hint: I don't). Using a
language with control structures is far more concise and easier to
maintain.

If I did have to write test vectors I would probably use something to
generate those test vectors as an output file artifact from a
simulation run.

If you look at tools like Mentor's inFact they do exactly that although they
don't create a vector file but an intelligent testbench instead. The inputs
are high-level rules and actions. These high-level rules are compiled into
testbench graphs which are then use to generate optimised vector sets.

For example to test a UART you write different rules for all the different
options like word size, parity type, number of stop bits, interrupt
sequence, read/write sequence etc. The compile will then use this info to
generate an optimised vector set that test all valid combinations (not 100%
sure on this one). I believe this is one step up from writing assertions and
feeding your design with constrained random data.

This is a trivial example but you can understand that with more rules this
becomes more and more powerful. From what I understand these tools are very
complex since they not only need to find the smartest set of testvectors but
also handle all the different constraints and constraint solvers is one area
which is still heavily being researched.

I would say kudos to Evan for attempting to develop a product like this and
making it freely available to the rest of us,

Hans
www.ht-lab.com

// trivial complete testbench example: 4-bit counter with reset
DUT {
module counter(input CLK, RST; output [3:0] Q)
create_clock CLK // define the clock
[CLK, RST] -> [Q] // define the test vector format}

main() {
[.C, 1] -> [0]; // reset
for(i=1; i <= 16; i++)
[.C, 0] -> ; // count, with rollover

Having flashbacks to generating test vectors in ABEL...something from
20 years ago.

KJ

 

[HT-Lab]

"KJ" <kkjennings@sbcglobal.net> wrote in message
news:1b5f41df-e273-47c0-b309-460a94735b9e@x19g2000prg.googlegroups.com...
On Apr 21, 5:11 am, Evan Lavelle <nos...@nospam.com> wrote:

You don't need to know
or write *any* HDL code to use Maia; if you can write vectors for your
module, then you can verify it.


Not to be too much of a slug, but I'm kinda missing the point I think
of this tool....

Why would I want to write test vectors (Hint: I don't). Using a
language with control structures is far more concise and easier to
maintain.

If I did have to write test vectors I would probably use something to
generate those test vectors as an output file artifact from a
simulation run.

If you look at tools like Mentor's inFact they do exactly that although they
don't create a vector file but an intelligent testbench instead. The inputs
are high-level rules and actions. These high-level rules are compiled into
testbench graphs which are then use to generate optimised vector sets.

For example to test a UART you write different rules for all the different
options like word size, parity type, number of stop bits, interrupt
sequence, read/write sequence etc. The compile will then use this info to
generate an optimised vector set that test all valid combinations (not 100%
sure on this one). I believe this is one step up from writing assertions and
feeding your design with constrained random data.

This is a trivial example but you can understand that with more rules this
becomes more and more powerful. From what I understand these tools are very
complex since they not only need to find the smartest set of testvectors but
also handle all the different constraints and constraint solvers is one area
which is still heavily being researched.

I would say kudos to Evan for attempting to develop a product like this and
making it freely available to the rest of us,

Hans
www.ht-lab.com

// trivial complete testbench example: 4-bit counter with reset
DUT {
module counter(input CLK, RST; output [3:0] Q)
create_clock CLK // define the clock
[CLK, RST] -> [Q] // define the test vector format}

main() {
[.C, 1] -> [0]; // reset
for(i=1; i <= 16; i++)
[.C, 0] -> ; // count, with rollover

Having flashbacks to generating test vectors in ABEL...something from
20 years ago.

KJ

 

[Uwe Bonnes]

xicloid@gmail.com wrote:

I've recently spent more than four hours just trying to catch two
trivial incorrect vector assignments (incorrectly declaring vector as
scalar & 3-bit vector as 4-bit vector) in Verilog design modules.
I'm fairly new to Verilog, and I'm not that comfortable with using
ModelSim or analyzing Verilog codes yet.
So, just in case I make similar mistake some time later, I was
wondering if there is any function in ModelSim that catches those kind
of mistakes, like printing out a warning on the screen when there is a
mismatch in the size of a vector or something.

Try different compiler and read the error messages warnings. Often XST tells
about things that iverilog doesn't.
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

 

[Uwe Bonnes]

xicloid@gmail.com wrote:

I've recently spent more than four hours just trying to catch two
trivial incorrect vector assignments (incorrectly declaring vector as
scalar & 3-bit vector as 4-bit vector) in Verilog design modules.
I'm fairly new to Verilog, and I'm not that comfortable with using
ModelSim or analyzing Verilog codes yet.
So, just in case I make similar mistake some time later, I was
wondering if there is any function in ModelSim that catches those kind
of mistakes, like printing out a warning on the screen when there is a
mismatch in the size of a vector or something.

Try different compiler and read the error messages warnings. Often XST tells
about things that iverilog doesn't.
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

 

[KJ]

"Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message
news:fv7i38$69n6@cnn.xsj.xilinx.com...

My question: what is the cleanest way to describe an FSM requiring
pipelining?

As is usually the case...'it depends'. There are two basic approaches:
1. Add additional states to the FSM to match the latency of the newly
pipelined operation.
2. Add a request/acknowledge handshake signal pair into and out of the FSM
that controls movement to the next state.

#1 is fairly straightforward, but as you're finding out gets to be a pain if
you use this method exclusively instead of just for relatively simple cases
that won't change. This method can also tend to create fairly cumbersome
logic implementation as well (i.e. the state machine logic can get to become
the critical timing path).

For #2, with the request/acknowledge signals what you're doing is
refactoring your logic and using signals to indicate when that process
should wake up and when it has produced a result. Another way of looking at
it is that you're 'subcontracting' or 'outsourcing' that hunk of logic. In
the example you gave the multiply/add operation is the function that you're
outsourcing. From the perspective of the state machine then it simply needs
to tell this other hunk-o-logic when to start (i.e. request) and the
hunk-o-logic in turn needs to tell the FSM when it has completed (i.e.
acknowledge).

This basic approach scales very well and is generally tolerant of further
changes in the actual latency. Using your multiply/add example, you might
at first decide to have one stage of latency (registering the inputs) and
then later decide to make it three (register, inputs, multiply, and sum).
The request/acknowledge signal *interface* between the hunk-o-logic and the
FSM does not need to change, nor does the FSM itself (unlike approach #1).
All that does need to change is you add a couple more flops of delay to
generate the acknowledge.

As you find other critical timing paths you'll still need to figure out
exactly which sub-functions need to be segregated out for pipelining, but
once you've done this, the approach is the same: simply create a
request/acknowledge pair to control that sub-function and tie those signals
into the state machine.

Put the source code for the logic needed to generate the acknowledge
physically right by the hunk-o-logic function itself and it makes it easy to
maintain as well. If the hunk-o-logic is complex enough, you might consider
making it it's own entity/architecture. If not, maybe put it in it's own
separate process (something I do to kind of break up the actual source code
text into manageable sized pieces to make it easy to see what that bit
does). In any case, what you're basically doing is adding a bit of
hierarchy to your design whether it is formal (i.e. separate entities) or
less formal (separate clocked process). Once you've physically segregated
the stuff, you can probably also see that it wouldn't be that hard to
parameterize it so that you could have generics select whether the latency
in some fashion...but that's a bit off topic.

The other thing to consider is whether the latency being introduced by this
outsourced logic needs to be 'compensated for' in some fashion or is it OK
to simply wait for the acknowledge. In some instances, it is fine for the
FSM to simply wait in a particular state until the acknowledge comes back.
In others you need to be feeding new data into the hunk-o-logic on every
clock cycle even though you haven't got the results from the first back. In
that situation you still have the req/ack pair but now the ack is simply
saying that the request has been accepted for processing, the actual results
will be coming out later. Now the hunk-o-logic needs an additional output
to flag when the output is actually valid. This output data valid signal
would typically tend to feed into a separate FSM or some other logic (i.e.
'usually' not the first FSM). The first FSM controls feeding stuff in, the
second FSM or other processing logic is in charge of taking up the outputs
and doing something with it.

When you ponder on this approach some more, you will come to the realization
that this signalling back and forth between various sub-processes boils down
to simply managing data transfer. Once that realization has settled in, it
is worthwhile to study existing data transfer techniques (I'd suggest
Wishbone and Avalon, I prefer Avalon), decide for yourself which signalling
scheme to use and stick to it, using that specification's naming/logic
conventions and go from there and never look back at all the other possible
ad-hoc ways of doing it.

Is there some sort of tool that will let me make a nice bubble diagram but
also indicate which operations need pipelined and will then generate the
proper synthesizable HDL?

Altera's Quartus has a state machine machine viewer that can be exported for
documentation if that's what you're looking for.

Kevin Jennings

 

[David Spencer]

"Dkthechamp" <dkthechamp@gmail.com> wrote in message
news:cbf08467-b48d-485a-9566-ac4b356038ee@f36g2000hsa.googlegroups.com...

Hi,

I am desiging an asynchronous counter with asynchronous reset. I am
using structural approach where i instantiates D FFs, the inverted
output of first FF being the clock of next one. But i want it to be
reset with a given condition and the condition is set as the input to
the module.

Any clues would be appreciated !

Deepak

How about telling your tutor that you're very unlikely to use a ripple
counter in real life and ask him to set you more realistic homework next
time.

 

[John Penton]

water9580@yahoo.com wrote:

On Apr 30, 8:49 pm, gabor <ga...@alacron.com> wrote:
On Apr 29, 11:56 pm, "water9...@yahoo.com" <water9...@yahoo.com
wrote:

wire [6:0] length;
wire [11:0] addr;

assign len_lte=((addr[11:2]+length)<=13'h400)?1'b1:1'b0;

thx

It would help to know:

What you are synthesizing this code into.

What results are not adequate (speed, resource usage)

Are there any useful properties of length or addr that might
help (i.e. one or the other is static or changes only when
len_lte is not required to be valid)

Why does 13'h400 need 13 bits when you compare it to a
sum of 10 and 7 bit numbers

why the (a <= b) ? 1 : 0; format instead of just a <= b;

Regards,
Gabor

my solution:

assign addr_pg=addr[11:2]+length;


always @(*)
begin
if(addr_pg[10])
begin
if(|addr_pg[9:0])
tlp_length=start_dist4k;
else
tlp_length=tlp_length1;
end
else
begin
tlp_length=tlp_length1;
end
end

it can remove a big comparator.

any better coding style?

Where did all those extra signals (tlp_length, start_dist4k) come from.
That is not the same logic.

Personally, I would write the code as is and let the synthesis tool optimise
all the zeros away unless you have evidence that it is not doing so. Might
be nice to be explicit about the zeros:

assign len_lte=({1'b0,addr[11:2]}+
{4'b0000, length} )<=11'h400;

If you want to be explicit about it, then you could get rid of the top of
the adder (the adder is the biggest, slowest bit):

wire [8:0] sum_8_0 = {1'b0,addr[9:2]} + {1'b0,length};
wire carry_10_8 = &addr[11:10];

assign len_lte = ~sum_8_0[8] | ~(|sum_8_0[7:0]) | ~carry_10_8;

I haven't tested the above, so there are probably some little bugs, but you
can see where I'm going. I still think the synthesis tool would do the same
if left to its own devices.

John

--
John Penton, posting as an individual unless specifically indicated
otherwise.

 

[John Penton]

water9580@yahoo.com wrote:

On Apr 30, 8:49 pm, gabor <ga...@alacron.com> wrote:
On Apr 29, 11:56 pm, "water9...@yahoo.com" <water9...@yahoo.com
wrote:

wire [6:0] length;
wire [11:0] addr;

assign len_lte=((addr[11:2]+length)<=13'h400)?1'b1:1'b0;

thx

It would help to know:

What you are synthesizing this code into.

What results are not adequate (speed, resource usage)

Are there any useful properties of length or addr that might
help (i.e. one or the other is static or changes only when
len_lte is not required to be valid)

Why does 13'h400 need 13 bits when you compare it to a
sum of 10 and 7 bit numbers

why the (a <= b) ? 1 : 0; format instead of just a <= b;

Regards,
Gabor

my solution:

assign addr_pg=addr[11:2]+length;


always @(*)
begin
if(addr_pg[10])
begin
if(|addr_pg[9:0])
tlp_length=start_dist4k;
else
tlp_length=tlp_length1;
end
else
begin
tlp_length=tlp_length1;
end
end

it can remove a big comparator.

any better coding style?

Where did all those extra signals (tlp_length, start_dist4k) come from.
That is not the same logic.

Personally, I would write the code as is and let the synthesis tool optimise
all the zeros away unless you have evidence that it is not doing so. Might
be nice to be explicit about the zeros:

assign len_lte=({1'b0,addr[11:2]}+
{4'b0000, length} )<=11'h400;

If you want to be explicit about it, then you could get rid of the top of
the adder (the adder is the biggest, slowest bit):

wire [8:0] sum_8_0 = {1'b0,addr[9:2]} + {1'b0,length};
wire carry_10_8 = &addr[11:10];

assign len_lte = ~sum_8_0[8] | ~(|sum_8_0[7:0]) | ~carry_10_8;

I haven't tested the above, so there are probably some little bugs, but you
can see where I'm going. I still think the synthesis tool would do the same
if left to its own devices.

John

--
John Penton, posting as an individual unless specifically indicated
otherwise.