need a cheap student edition FPGA

Hmm. Your definition of a state machine differs from established FSM
theory.
You focus only on the textual description.

With your definition a CPU-core and its ROM is not a state machine.
Also a shift register used to control other logic would not be a state
machine.
Any script generated state machines also do not count.
Self resetting state machine (JTAG controller anyone?) are also no
state machines because there is no reset signal.


The definition of a state machine that I am used to is:
A set of storage elements that are connected in a way that the
following state of the elements depends on the previous state.
State machines can be arbitrarily partitionend and merged. The whole
chip can be analyzed as one big state machine (usually not a big idea)
or each individual flip-flop can be interpreted as a state machine
(also often a bad idea).

But to give you the benefit of doubt and return to your orginal
question:
Smith-Waterman hardware implementations instantiate tens of thousands
of identical state machines.
Oh, wait, the implentation that we used had not reset. Damn.

Kolja Sulimma


On 17 Sep., 21:43, Weng Tianxiang <wtx...@gmail.com> wrote:
Hi Glen,
There is a theory behind to resolve the problem.

A state machine can be defined in such a scentific way:
1. All states in a state machine have their own names;
2. All states in a state machine are mutually exclusive;
3. Only one state is active in any cycle;
4. The number of states in a state machine must be 2 or more;
5. There must have either asynchronous or a synchronous reset signal
for the state machine and after their assertion, the state machine
must be in initial state.

I guess there are less than 27 engineers in the world who have the
experiences to do the designs.

If your experiences are fully in FPGA and VHDL worlds, you may never
have a chance to get a right guess with any possible wildest
imagination,

Any more question?

Weng
Click to expand...
 
Hi,
1. I am talking about GUESSING the largest number of state machines a
current finished design may have. Not ceiling.

2. State machine can be anything, my definition is only for reference
to clear up any misunderstanding.

3. A synchronous or an asynchronous reset signal is vital, either with
clear routing or a hidden within other procedures.

Weng
 
Weng Tianxiang wrote:
(snip)

3. A synchronous or an asynchronous reset signal is vital, either with
clear routing or a hidden within other procedures.
Click to expand...
I disagree. Some can synchronize without any reset signal, though
they may have one anyway. The receiver in a UART, if started out
of frame, will synchronize to frame boundaries after not so many
characters come through. That is the purpose for start/stop bits.

There are many systems with a large number of self synchronizing
state machines.

-- glen
 
comp.arch.fpga wrote:

(snip)

But to give you the benefit of doubt and return to your orginal
question:
Smith-Waterman hardware implementations instantiate tens of thousands
of identical state machines.
Click to expand...
Like the ones that Paracel used to build and sell as real systems?

Oh, wait, the implentation that we used had not reset. Damn.
Click to expand...
Which one was that?

-- glen
 
"Weng Tianxiang" <wtxwtx@gmail.com> wrote in message
news:1190135851.404698.228480@y42g2000hsy.googlegroups.com...
Hi,
1. I am talking about GUESSING the largest number of state machines a
current finished design may have. Not ceiling.
Click to expand...
My official guess:
light blue.
 
On Sep 18, 11:43 am, "John_H" <newsgr...@johnhandwork.com> wrote:
"Weng Tianxiang" <wtx...@gmail.com> wrote in message

news:1190135851.404698.228480@y42g2000hsy.googlegroups.com...

Hi,
1. I am talking about GUESSING the largest number of state machines a
current finished design may have. Not ceiling.

My official guess:
light blue.
Click to expand...
Hi John_H,
1. The guessing is missing target.
2. The design falls in every person's blind point who have responded
to the post so far.

Weng
 
On Sep 18, 5:07 pm, Weng Tianxiang <wtx...@gmail.com> wrote:
On Sep 18, 11:43 am, "John_H" <newsgr...@johnhandwork.com> wrote:

"Weng Tianxiang" <wtx...@gmail.com> wrote in message

news:1190135851.404698.228480@y42g2000hsy.googlegroups.com...

Hi,
1. I am talking about GUESSING the largest number of state machines a
current finished design may have. Not ceiling.

My official guess:
light blue.

Hi John_H,
1. The guessing is missing target.
2. The design falls in every person's blind point who have responded
to the post so far.

Weng
Click to expand...
I guess 28.
 
Weng Tianxiang wrote:
On Sep 18, 11:43 am, "John_H" <newsgr...@johnhandwork.com> wrote:
"Weng Tianxiang" <wtx...@gmail.com> wrote in message

news:1190135851.404698.228480@y42g2000hsy.googlegroups.com...

Hi,
1. I am talking about GUESSING the largest number of state machines a
current finished design may have. Not ceiling.
My official guess:
light blue.

Hi John_H,
1. The guessing is missing target.
2. The design falls in every person's blind point who have responded
to the post so far.

Weng
Click to expand...
To the extent that my guess is as applicable as anyone elses guess, I
stand behind it.

You are asking a seriously senseless question and frankly I'm tired of
watching the thread drone on and on and on so I just added a little to
it because of the absurdity.

Who cares?!
 
On 18 Sep., 19:17, Weng Tianxiang <wtx...@gmail.com> wrote:
Hi,
1. I am talking about GUESSING the largest number of state machines a
current finished design may have. Not ceiling.
But you do not react if someone answers your question. Can you beat
Click to expand...
the
10k+ state machines of a smith-waterman DNA matcher?

3. A synchronous or an asynchronous reset signal is vital, either with
clear routing or a hidden within other procedures.
Click to expand...
Again, you did not read my post. Many state machines have no reset
signal.
For example the reset signal of a JTAG controller is optional. This is
a state machine that is implemented in virtually every complex piece
of silicon out there.

Kolja Sulimma
 
Hi KS, jg,
I answer your questions directly and clearly here:
1. The number of state machines should be much greater than 100k.

2. "Many state machines have no reset signal. "

I have answered your question:
"A synchronous or an asynchronous reset signal is vital, either with
clear routing or a hidden procedure within other initial procedures."

3. "a single FF_CE can be considered a state machine"

No, a single FF_CE is not included in the count. Otherwise my post for
a guessing doesn't make sense.

4. Shifting registers can and should be counted as a state machine
with only one bit set (or only one bit reset) among all its bits.

Please don't delete group names: comp.lang.verilog, comp.lang.vhdl

Because answering this quiz needs knowledge beyond scopes of FPGA and
VHDL.

A quiz beyond FPGA and VHDL may have been the first time since both
groups were set up 10-20 years ago.

I have been wondering why there nobody is asking such a question:
Why is this quiz beyond scope of VHDL?

Any more questions?

Weng
 
comp.arch.fpga wrote:

(snip)

But you do not react if someone answers your question.
Can you beat the 10k+ state machines of a
smith-waterman DNA matcher?
Click to expand...
If this is the one I remember, then it is wrong:

Smith-Waterman does local alignment which requires finding the
maximum score anywhere in the array. Global alignment only needs
the score at the end. It is interesting, but most DNA research
needs the local alignment.

Paracel and Time Logic make (or made) commercial DNA matching
machines that should qualify as large number of state machines.

-- glen
 
"A synchronous or an asynchronous reset signal is vital, either with
clear routing or a hidden procedure within other initial procedures."
Click to expand...
Nonsense. Consider self synchronizing scramblers. They are
just a batch of XOR gates and FFs. From any unspecified state,
they will put out garbage for N clock ticks. After that,
the output is determined by the input.

--
These are my opinions, not necessarily my employer's. I hate spam.
 
On Sep 19, 3:53 pm, hal-use...@ip-64-139-1-69.sjc.megapath.net (Hal
Murray) wrote:
"A synchronous or an asynchronous reset signal is vital, either with
clear routing or a hidden procedure within other initial procedures."

Nonsense. Consider self synchronizing scramblers. They are
just a batch of XOR gates and FFs. From any unspecified state,
they will put out garbage for N clock ticks. After that,
the output is determined by the input.

--
These are my opinions, not necessarily my employer's. I hate spam.
Click to expand...
Hi Hal,
Can you please put more information on scramblers and their state
machines?

I don't know scramblers.

Weng
 
Can you please put more information on scramblers and their state
machines?

I don't know scramblers.
Click to expand...
The idea is to generate a random bit stream that you can XOR
with a data stream for a serial link to make sure there are
no long strings of 0s or 1s.

It's a pile of FFs and XORs. The same logic as CRCs.
LFSR, Linear Feedback Shift Register is another buzzword.

The "self synchronizing" part means that the output
doesn't need to be reset. It will get to a known state
after N cycles. A single bit error on the link
will produce a multi-bit error after the descrambler.
That pattern of bits is the polynomial used by the scrambler.

The wiki article is pretty good.
http://en.wikipedia.org/wiki/Scrambler_(randomizer)
A digital communications text might be better.

--
These are my opinions, not necessarily my employer's. I hate spam.
 
On Sep 19, 5:58 pm, hal-use...@ip-64-139-1-69.sjc.megapath.net (Hal
Murray) wrote:
Can you please put more information on scramblers and their state
machines?
I don't know scramblers.

The idea is to generate a random bit stream that you can XOR
with a data stream for a serial link to make sure there are
no long strings of 0s or 1s.

It's a pile of FFs and XORs. The same logic as CRCs.
LFSR, Linear Feedback Shift Register is another buzzword.

The "self synchronizing" part means that the output
doesn't need to be reset. It will get to a known state
after N cycles. A single bit error on the link
will produce a multi-bit error after the descrambler.
That pattern of bits is the polynomial used by the scrambler.

The wiki article is pretty good.
http://en.wikipedia.org/wiki/Scrambler_(randomizer)
A digital communications text might be better.

--
These are my opinions, not necessarily my employer's. I hate spam.
Click to expand...
Hi Hal,
Thank you very much for your information.

Weng
 
Hi Hal,
8b/10b is perfect for scrambling function. PCI-e uses 8b/10b
technology.

Scramble technology still uses randomized serial and XOR now? After 8b/
10b technology, I think other randomized XOR scramble technology is
dying out, is it right?

IBM got one patent for 8b/10b technology in 1981, Xilinx filed for 23
patents on 8b/10b implementation in FPGA on one day in 2004.

I think that IBM is really a technology leader in almost all respects
in computer industry. Xilinx is the leader of FPGA.

Weng
 
Far too restrictive. In a TDMA architecture I implemented, one RAM contains
512 locations of N bits each: 512 individual state machines. Each 'virtual
process' was identical, but had different inputs. For this particular
design, a lower bound on the number of states would be 4*512 = 2048, since I
had four instances of that particular module. Probably double that, due to
similar logic structures downstream. If it were appropriate for the
application, scale it up appropriately.

Depending on required processing speed, state machine complexity, target
device capabilities, etc., an internal (or external) RAM could contain
thousands -- or millions -- of individal state machines.

For my particular case, the next states were defined by equations, the last
states were the outputs of the RAMs, and the particular state machine was
selected by the RAMs address. (I instantiated the RAMs, but they could have
been generated by a process. However, the tools aren't always that good at
properly inferring dual-port RAMs, so if you need a particular
structure... )

So, what are the limiting factors? Available logic, available storage
(registers and memory), creativity, and objectives.

What is the value of the answer?

JTW

"Weng Tianxiang" <wtxwtx@gmail.com> wrote in message
news:1190052227.791942.311570@w3g2000hsg.googlegroups.com...
Hi,
OK, a state machine is defined by standard one process or two
processes in VHDL.

There is no short cut.

It can be implemented in anywhere in a design and where the state
machine is located is decided by compilers and beyond the interest of
this topics.

I have to expand the guess to include Verilog group people, because
VHDL people may have no chance to do the designs.

I may know the answer. The final result may surprise everyone who
gives a guess.

Thank you.

Weng
Click to expand...
 
Scramble technology still uses randomized serial and XOR now? After 8b/
10b technology, I think other randomized XOR scramble technology is
dying out, is it right?
Click to expand...
8b/10b has a 20% bandwidth hit. That may be reasonable on short
links where the cost of the link is small relative to the cost
of the end points. But change hats from a computer room
to a Telco. Their costs are mostly the fibers in the ground.
Using scramblers is a no-brainer for 20% cost reduction.

--
These are my opinions, not necessarily my employer's. I hate spam.
 
Weng Tianxiang wrote:
Hi Hal,
8b/10b is perfect for scrambling function. PCI-e uses 8b/10b
technology.

Scramble technology still uses randomized serial and XOR now? After 8b/
10b technology, I think other randomized XOR scramble technology is
dying out, is it right?

IBM got one patent for 8b/10b technology in 1981, Xilinx filed for 23
patents on 8b/10b implementation in FPGA on one day in 2004.

I think that IBM is really a technology leader in almost all respects
in computer industry. Xilinx is the leader of FPGA.

Weng
Click to expand...
80B/10B is not a scrambler. It's a coding mechanism used to balance the
DC offset of the encoded stream. It's a straight encode/decode.

Don't be disappointed and frustrated for what you don't know.
 
Another fat-ass discussion invoked by Weng.

Hey Weng, you always turn on the most crapiest and unhealthiest
discussions.

BTW any big-company chief scientists or fat-ass academic professors
want to discuss about YARDstick, my super tool for custom processor
development?

There is a joke about academic bozzos and their capability of
coding...

http://electronics.physics.auth.gr/people/nkavv/yardstick/
 
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