need a cheap student edition FPGA

[Davy]

Hi Ajeetha,

Thanks a lot!

Do you mean if I don't use clocking block. I have to do something like
below:
@(posedge clk)
#1 data_out = data_in;

And if I use clocking block, I just define #1 in clocking block?

Best regards,
Davy

Ajeetha wrote:

Clocking block is recommended usage in testbench to avoid race
conditions. WIthout it, all your read/write or asynchronous and you are
required to explicitly synchronize them.

HTH
Ajeetha, CVC
www.noveldv.com
Davy wrote:
Hi,

I found in some SystemVerilog examples, people like to add Clocking
Block to driver and monitor. While some other SV examples only use
modport (don't use Clocking Block).

So I am confused with it.
1. Is it recommendation to use Clocking Block?
2. Shall I only use it in testbench component like driver and monitor
(shall I use it in responder)?


Best regards,
Davy

 

[Davy]

Hi Ajeetha,

Thanks a lot!
I am reading your "VMMing a SystemVerilog testbench by example".

In "fifo_cmd_xactor.sv", there is a "task push_task". Is the "With
Clocking Block" equal to "Without Clocking Block" that deal with data
synchronization manually?

//---With Clocking Block---
[code:1:5e5cb63b8f] task push_task (logic [BIT_DEPTH-1:0] data);
begin
$display ("%0t %m Push data %0h ", $time, data);
f_if.driver_cb.data_in <= data;
f_if.driver_cb.push <= 1'b1;
f_if.driver_cb.pop <= 1'b0;
@ ( f_if.driver_cb);
f_if.driver_cb.push <= 1'b0;
end
endtask : push_task [/code:1:5e5cb63b8f]
//-----------------------------


//---Without Clocking Block---
[code:1:5e5cb63b8f] task push_task (logic [BIT_DEPTH-1:0] data);
begin
$display ("%0t %m Push data %0h ", $time, data);
@ (posedge clk)
data_in <= data;
push <= 1'b1;
pop <= 1'b0;
@ ( posedge clk);
@ ( posedge clk)
push <= 1'b0;
end
endtask : push_task [/code:1:5e5cb63b8f]
//-----------------------------

Best regards,
Davy


Ajeetha wrote:

Clocking block is recommended usage in testbench to avoid race
conditions. WIthout it, all your read/write or asynchronous and you are
required to explicitly synchronize them.

HTH
Ajeetha, CVC
www.noveldv.com
Davy wrote:
Hi,

I found in some SystemVerilog examples, people like to add Clocking
Block to driver and monitor. While some other SV examples only use
modport (don't use Clocking Block).

So I am confused with it.
1. Is it recommendation to use Clocking Block?
2. Shall I only use it in testbench component like driver and monitor
(shall I use it in responder)?


Best regards,
Davy

 

[Davy]

Hi Ajeetha,

Forgive me to ask two more question

1. Shall clocking block signals be only used in Non-blocking assignment
(cb_sig <= local_sig )?
I have see them in fifo_cmd_xactor.v.

2. If clocking block signals cannot be used in blocking assignment (
local_sig = cb_sig ), why declear them in monitor. As we all know,
monitor is pure passive and blocking.

Thanks!

Best regards,
Davy


Ajeetha wrote:

Clocking block is recommended usage in testbench to avoid race
conditions. WIthout it, all your read/write or asynchronous and you are
required to explicitly synchronize them.

HTH
Ajeetha, CVC
www.noveldv.com
Davy wrote:
Hi,

I found in some SystemVerilog examples, people like to add Clocking
Block to driver and monitor. While some other SV examples only use
modport (don't use Clocking Block).

So I am confused with it.
1. Is it recommendation to use Clocking Block?
2. Shall I only use it in testbench component like driver and monitor
(shall I use it in responder)?


Best regards,
Davy

 

[Joe User]

On Wed, 29 Nov 2006 18:43:02 +0000, MI5-Victim wrote:

Gagged by BBC Ariel's editor

snip

It looks like English kooks are generally better educated and are much
better spellers than American kooks that I usually see posting this kind
of stuff.

French and Sweedish kooks must be really classy.

--
They laughed at Einstein. They laughed at the
Wright Brothers. But they also laughed at Bozo
the Clown.

-- Carl Sagan


--
Posted via a free Usenet account from http://www.teranews.com

 

Thanks for all the responses and clarifications.

The reason for the initial question is that I require very low power
(both static and dynamic).

Therefore:
- Sampling the slow clock using the fast clock is not possible. I only
want the fast clock to be running when a bus operation is required. I
am using AMBPA APB, so this may be 2 clock cycles (when the PSEL is
active)
- I am trying to reduce gate-count (i.e. I'll try to avoid having the
compare register in both clock domains)

I am hoping that this problem has a solution. When I think about it too
hard, my head hurts :-(

Thanks,

Steven

 

[Utku Özcan]

ram wrote:

I have technology library from altera with 1ps/1ps.This connected to
test becnh,netlist,sdf files are in timescale 1ns/10ps.I want to
convert the altera file to 1ns/1ops.what changes i should do for that
file at the values after #..the technology file is making simulation
very long time.I want to reduce that.Thanking you
kumar

You cannot change technology unless you know what to do.
You have always the chance to get nasty stuff in which you copy the
Verilog description of technology file to another directory and change
`timescales to the settings you need.

Otherwise, I am afraid that it is not a good design practice. You must
say amen to the speed of your simulation. If you really need to speed
up, I suggest you apply Verilog forces in your design.

That way you define a state of your system immediately, which takes
actually a lot of time to be set up in your sim. Or, increase activity
speed of your design, in which you e.g. increase clock of your
programming phase, if any.

As a designer you have the complete freedom, but don't forget, you
change the natural behaviour of the system to save sim time thus
development time at the expense of changing the behaviour, which might
produce unexpected results.

Start the simulations before you go home

Utku.

 

[Stephen Williams]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

ram wrote:

I have technology library from altera with 1ps/1ps.This connected to
test becnh,netlist,sdf files are in timescale 1ns/10ps.I want to
convert the altera file to 1ns/1ops.what changes i should do for that
file at the values after #..the technology file is making simulation
very long time.I want to reduce that.Thanking you
kumar

Reasonable verilog simulators are not impacted by the chosen
precision of the simulation model. They are discrete event based
and do not simply mark the time.

- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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Version: GnuPG v1.4.2 (GNU/Linux)
Comment: Using GnuPG with SUSE - http://enigmail.mozdev.org

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oVpwFzVLyu4GTz7OtK0eFNo=
=r/a7
-----END PGP SIGNATURE-----

 

[ram]

My problem is it is taking too long time for simulation.My system
operates at MHz
how to solve it.

Stephen Williams wrote:

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

ram wrote:
I have technology library from altera with 1ps/1ps.This connected to
test becnh,netlist,sdf files are in timescale 1ns/10ps.I want to
convert the altera file to 1ns/1ops.what changes i should do for that
file at the values after #..the technology file is making simulation
very long time.I want to reduce that.Thanking you
kumar


Reasonable verilog simulators are not impacted by the chosen
precision of the simulation model. They are discrete event based
and do not simply mark the time.

- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.2 (GNU/Linux)
Comment: Using GnuPG with SUSE - http://enigmail.mozdev.org

iD8DBQFFd3lArPt1Sc2b3ikRAqxeAJ9yQaYSKiRkqw2Bee7XvPNOLB0feACeIcQg
oVpwFzVLyu4GTz7OtK0eFNo=
=r/a7
-----END PGP SIGNATURE-----

 

[Stephen Williams]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

ram wrote:

My problem is it is taking too long time for simulation.My system
operates at MHz
how to solve it.

That's waaaaay to vague a question. People here may be able to
help you, but they'll need at a bare minimum the version of Verilog
compiler you are using and some sense of what you are running on
that compiler. From that, you *might* get some optimization tips.

Stephen Williams wrote:
ram wrote:
I have technology library from altera with 1ps/1ps.This connected to
test becnh,netlist,sdf files are in timescale 1ns/10ps.I want to
convert the altera file to 1ns/1ops.what changes i should do for that
file at the values after #..the technology file is making simulation
very long time.I want to reduce that.Thanking you
kumar

Reasonable verilog simulators are not impacted by the chosen
precision of the simulation model. They are discrete event based
and do not simply mark the time.

- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.2 (GNU/Linux)
Comment: Using GnuPG with SUSE - http://enigmail.mozdev.org

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Pp6cRRQdQveYFAbwWg/JeBg=
=jQYG
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[john]

Hello Mike,

Are you advicing that synchronizing the signal between two clock
domains via two flip flops is OK? I have one clock which is running at
24MHz and the second clock running at 1MHz.

John
Mike Treseler wrote:

moogyd@yahoo.co.uk wrote:

When I pass a signal between clock domains (clkfrom to clkto), I use
two FF's in the clkto domain prior to using the signal in this domain.
If there is a timing violation (setup or hold) at the first FF, then
the O/P will become metastable. i.e. Unknown, and it will stay in this
state for a time determind by a probability distribution.

The most likely result of a timing violation in FF1 is proper
synchronization either on that edge or the next. The primary
job of the flop is to eliminate races to the subsequent flops
in the design by retiming the edges. The most common symptom of a logic
race is an "impossible" state transition.

The second flop is there to reduce the odds
of synchronization failure from say once a year to maybe
once every hundred years. That's cheap insurance.
Without any synchronization, I would expect a race problem
in much less than a year -- more likely in less than a millisecond.

For a synchronizer example, search for "retime"
in the reference design here:
http://home.comcast.net/~mike_treseler/

If I am passing a signal from a fast clock domain (16MHz) to a slow
clock domain (100Hz) at 0.18us, do I need to synchronize?

Yes.

The easiest way is to run the "slow" counter at 16MHz
using clock enables. See the "clock enabled counters"
source for an example. Or you could handshake the
transaction with ready and ack signals, properly
synchronized, of course.

e.g. As a simple example, I have a timer on a system bus. The cycle
time register is in the fast domain.

Is there a problem with this code?

Yes.

If you travel down this road you will
eventually reinvent the uart or the fifo.

-- Mike Treseler

 

[Mike Treseler]

john wrote:

Are you advicing that synchronizing the signal between two clock
domains via two flip flops is OK? I have one clock which is running at
24MHz and the second clock running at 1MHz.

I would advise running the module at 24 MHz
and using the second clock as a plain input to
be synchronized and and converted
to a single cycle strobe.

-- Mike Treseler

 

[john]

Hi Mike,
I am trying to write a 48 bit buffer in the FPGA at the rising edge of
the USB clock and then trying to use the 1MHz clock to read the 48bit
bit buffer and then serially outputing them. What I understood from ur
advise that FPGA will run at 24MHz and the 1MHz clock will be input and
pass through flip flops and at the output of the second flip flop will
be used to read the 48bit buffer and serially output the data. Am I
right? Please adivse some sample code >

Regards
John

 

ram wrote:

.I want to
convert the altera file to 1ns/1ops.what changes i should do for that
file at the values after #..the technology file is making simulation
very long time.I want to reduce that.Thanking you

As Stephen said, the time precision does not directly affect the speed
of simulation. An event-driven simulator does not spend time
calculating for simulation times when nothing is happening. It jumps
ahead to the next time when something will happen. There can be
indirect effects if a finer precision causes there to be more unique
simulation times where something happens (i.e. with a coarser
precision, events that would have happened at distinct times have now
been rounded to occur at the same times). But it is unlikely that this
is the cause of your slowdown.

You can probably get faster simulation by turning off timing
simulation, but then you are only getting functional verification.

Your simulator may provide some kind of code profiler that will tell
you where the simulation time is being spent, so that you can tune
those parts of the design to make them more efficient to simulate.

 

[Andreas Ehliar]

On 2006-11-12, borge.strand@gmail.com <borge.strand@gmail.com> wrote:

Is there a dedicated power-on reset function in Verilog? What I want to
achieve is that my own reset functionality will be executed when the
FPGA (Xilinx Spartan3/400) undergoes power-on reset.

If you target an FPGA you might be able to use an initial block to
define the values that flip flops should have on startup.
According to http://news.elektroda.net/initial-value-t127740.html XST
can handle it at least.

/Andreas

 

[Jonathan Bromley]

On 5 Dec 2006 19:09:30 -0800, "Edmond Coté" <edmond.cote@gmail.com>
wrote:

Hello,

What's the status of the following type of interface construct? A
google search revealed that it was discussed in 2004 on the SV-BC list
(http://www.eda.org/sv-bc/hm/1865.html), however, that's the only place
on the web where I've seen any mention.

Example:

interface test_if #(parameter int N = 2);
wire [N-1:0] test;
genvar i;
generate for (i=0; i<N; i++)
modport slave(input test);
endinterface

A better solution, already defined in the 1800 LRM,
would be "modport expressions":

generate for (i=0; i<N; i++) begin : Slaves
modport slave(input .T(test));
end

because then all the modports look identical (they all have an
input called T, which is aliased on to the appropriate bit of
"test"). However, NO TOOLS YET SUPPORT THIS.

PLEASE go and beat on ALL your tool vendors to get them
to support this important feature. I'll be giving you more
ammunition in an upcoming paper at DVCon in February

I am using Mentor Precision RTL and I would like to hear if anyone has
any synthesizable alternatives, short of coding everything out manually
of course.

Yup, that's what you need to do right now :-(
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Edmond Coté]

Jonathan Bromley wrote:

PLEASE go and beat on ALL your tool vendors to get them
to support this important feature. I'll be giving you more
ammunition in an upcoming paper at DVCon in February

You may want to consider my situation Jonathan. I am a graduate student
with enough time on my hands (and motivation, in my case) to play
around with these new features. Despite having access to a plethora of
academic licenses from Synopsys, Mentor and Altera among others, I have
no recourse to any support offered from these vendors.

All to often is the case where I inexplicably crash the compiler,
obtain incorrect synthesis results and yet, I have no recourse to a bug
report form, or a FAE that I can dial up and basically "beat on".
Sadly, if I were an actual R&D engineer testing out these products, I
would have likely moved a long time ago.

Edmond Coté

 

[Paul Jansen]

#1 - Why is one signal rising at 10264ns, and the other at 10263ns?
Trace them back, see where they differ; that'll be your answer.

#2 - Who wrote the relevant simulation models? Is there a race in
them?

#3 - Why are you set at 1ns resolution? Is this a *very* slow chip? I
bet your sim models are set to 1ps; I'd suspect a rounding problem
somewhere.

#4 - What do you get if you enable sdf warnings & errors?

#5 - Is anyone in comp.arch.embedded really going to know the answer
to this one?!

/PJ

 

[Kim Enkovaara]

spectrallypure wrote:

Hi all! I am experiencing a very strange and rather frustrating problem
while trying to run the same backannotated simulation in two different
versions of Modelsim. In both cases I am using exactly the very same
files for everything, and also the same compilation and simulation
commands. The old version (Modelsim 5.8b) simulates fine and gives the
expected results, while a newer release (Modelsim 6.2e) gives erroneous
results. The following caption explains the situation (copy and paste
the following link in your browser):

One possibility is a bug in one of the Modelsim versions. SDF annotation
at least in huge chips usually finds some problems in the simulation
engine. Timing engine errors and differences are really hard to track
usually. You need at least the Verilog standard at hand to consult exact
functionality. The differences are usually much bigger between different
simulator vendors, although all of them should behave the same way.

I would suggest to send a testcase to Mentor. They have more tools to
pinpoint what really goes wrong. Also check the simulation resolution
you are using, rounding errors might be different in different tool
versions.

I made a signoff with 5.8b and 6.2a, both of them had some minor
problems, and different signoff corners needed different simulator
version to work the same way as static timing analysis (which usually is
the golden model).

If you have very complex tristate/opendrain structures 5.8b might cause
different results compared to newer versions (5.8b results are the
incorrect ones). And some early 6.2 versions had some problems with
conditional timing checks.

Also if the design is small have you tried to compare nonoptimized, fast
and vopt flows. As far as I know vopt timing engine is a new one, and if
you use the fast flow the engine behaves differently (the old way).

Also if the design is small easiest way to compare the results is to
record all the signals during the simulation (add log -r /*) and then do
a wave compare in the newer simulator version. Then search from the
comparison the first difference. You might need to change the comparison
default limits to much higher values to complete the comparison
(millions of differences allowed).


--Kim

 

[Thomas Stanka]

Hi,

spectrallypure schrieb:

files for everything, and also the same compilation and simulation
commands. The old version (Modelsim 5.8b) simulates fine and gives the
expected results, while a newer release (Modelsim 6.2e) gives erroneous
results. The following caption explains the situation (copy and paste

I think there are some changes in the preferences between both
versions.
I would start and use the same preferences. Second, there might be some
changes in compilation result when using the same switches, as defaults
changed. Check the release notes for 6.2e to see, if this is applicable
in your design.

bye Thomas

 

[Duth]

Hi,

I agree with Kim. You should not get any of the warnings that you are
getting in 6.2e and 5.8 either. Ensure that the annotation is happening
at the correct instantiation.

Additionally, have you tired to run the simulation using the -novopt
switch? The one major difference is that vopt is on by default in 6.2
versions.

I would not say that this is necessarily a bad thing to have vopt on,
although there could be some issues in the vopt algorithm and a simple
test to look at this is to disable the vopt, by using the -novopt in
both compilation and simulation commands.

Thanks
Duth


Kim Enkovaara wrote:

spectrallypure wrote:
#3 - Why are you set at 1ns resolution? Is this a *very* slow chip? I
bet your sim models are set to 1ps; I'd suspect a rounding problem somewhere.
We also think the problem might have to do with this. I just set the
resolution to 1ns because that is the value of the resolution of the
SDF files, but I have experimented by changing this value and the
timing of the waveform changes A LOT. However, I haven't been able to
make the simulation give the expected results by tweaking this
parameter. The operating frequency of the design is 50MHz.

You should set the resolution to what the models expect, nowadays the
resolution is usually 1ps or 10ps. The models can behave incorrectly
if the resolution is not correct.

And also the SDF must be generated from the layout tools with the same
or better resolution. 1ns resolution for the SDF files sounds very
large, unless you use some exotic or old process. Even for 0.13u process
1ps resolution is sometimes too high in STA.


#4 - What do you get if you enable sdf warnings & errors?

In 5.8b I get a lot (nearly 50,000) of the following warnings:

# ** Warning: (vsim-SDF-3262) ./DFM_TC_Worst.pt.sdf(<-SDF line number
here-&gt: Failed to find matching specify timing constraint.

... but the simulation works. On the other hand, in 6.2e, I get this
same error but a lot more times (something like three times more), I
additionally I get the following error (once again, I get it a lot of
times):

# ** Warning: (vsim-SDF-3261) ./DFM_TC_Worst.pt.sdf(<-SDF line number
here-&gt: Failed to find matching specify module path.

Normally you should not get any warnings or errors from the annotation.
They usually tell that the SDF is annotated to a wrong place or
simulation models do not match the synthesis models (library version
mismatch etc.). You should manually compare the SDF and the models to
see why the errors are there. I have seen usually warnings in special
analog cells, IO-testing structures etc. that are quite hard to model in
simulation.

50k errors is too much, <100 warnings for few gigabyte SDF sounds normal
figure. The tool might do things differently in error conditions
depending on versions.


--Kim