need a cheap student edition FPGA

[Dr Justice]

Thank you for the elaboration!

So not an absolute no-no as such then, but rather an ASIC/technology
precaution/facilitator and a style preference. I'll keep this in mind for
any future ASIC work (entirely hypothetical at this stage, I might add).

DJ
--

 

[Jason Zheng]

Davy wrote:

Hi all,
I want to save data to a file. And I use $fopen, %fwrite, %fclose. But
I found these function only can be called in initial block. When I use
them outside initial block, the compiler report errors??

That's right. You need to put those in a procedural block, such as an

initial block.

I want to use it in a for block, how?
I use Modelsim 5.6.

A for block must be contained within in a procedural block, such as an
initial block. This is true no matter what compiler/simulator you use.

cheers,

jz

 

[Jason Zheng]

Nju Njoroge wrote:

Hi,

I'm using the Verilog-2001 exponential operator to do the following:

`define NUM_COUNTER_BITS 8;
parameter NUM_COUNTER_CYCLES = 2 ** (`NUM_COUNTER_BITS);

When I simulate this in ModelSim 6.0a, launched from Project Nav. (ISE
7.1 SP3), NUM_COUNTER_CYCLLES = 5. However, if I use a parameter for
NUM_COUNTER_BITS instead of `define, as shown below, NUM_COUNTER_CYCLES
= 256, which is the desired result.

parameter NUM_COUNTER_BITS = 8;
parameter NUM_COUNTER_CYCLES = 2 ** (`NUM_COUNTER_BITS);

What are the inherent differences between a parameter and `define
directive that could this problem to occur.

I tried it with ncverilog, and didn't get the bad answer. Is it

posssible that the ; at the end of `define is causing the problem?

Try this in your module:

initial
$display ("NUM_COUNTER_BITS = %d", `NUM_COUNTER_BITS);

 

"Davy" <zhushenli@gmail.com> wrote in message
news:1120737703.470548.257570@g43g2000cwa.googlegroups.com...

Hi all,

I Recommend www.edaboard.com, a good forum discuss all about
electronics.

Best regards,
Davy

Last time I checked, 80-90% of the forum's posters fell into
these categories:

(a) had access to the l8test elite software tools, but
somehow "lost the product manual/documentation"

(b) were incapable of using basic features of their
state-of-the-art EDA-software (employer could afford
a $1,000,000 USD SOC-Encounter license, but couldn't
or didn't spend the extra $10,000 for training)

(c) didn't know how to install from a UNIX-binary (.tar.gz)

(d) oh and couldn't ask the vendor for technical support
because they're too busy, and it's easier to post on
an anonymous internet forum.

We all start learning somewhere, sometimes even by asking
basic questions. But nearly every post there pointed to
a different situation -- the poster downloaded the software
off their l8test eDAw@reZ/KaZAA/bittorrent group, didn't
know how to even install it, couldn't find the documentation
(made they forgot to download the docs?), ...

Is it any better now?

 

"Davy" <zhushenli@gmail.com> wrote in message
news:1120737703.470548.257570@g43g2000cwa.googlegroups.com...

Hi all,

I Recommend www.edaboard.com, a good forum discuss all about
electronics.

Best regards,
Davy

Last time I checked, 80-90% of the forum's posters fell into
these categories:

(a) had access to the l8test elite software tools, but
somehow "lost the product manual/documentation"

(b) were incapable of using basic features of their
state-of-the-art EDA-software (employer could afford
a $1,000,000 USD SOC-Encounter license, but couldn't
or didn't spend the extra $10,000 for training)

(c) didn't know how to install from a UNIX-binary (.tar.gz)

(d) oh and couldn't ask the vendor for technical support
because they're too busy, and it's easier to post on
an anonymous internet forum.

We all start learning somewhere, sometimes even by asking
basic questions. But nearly every post there pointed to
a different situation -- the poster downloaded the software
off their l8test eDAw@reZ/KaZAA/bittorrent group, didn't
know how to even install it, couldn't find the documentation
(made they forgot to download the docs?), ...

Is it any better now?

 

[Jedi]

Ajeetha wrote:

Add on to that list:

(e) This site hosts boat load of illegally dissemainated manuals,
e-books, scanned papers etc.

One of their recent posts read: I've got hold of VERA6.2.8, don't know
how to install it...

(f) Students with absolute no clue about engineering asking
other people for doing their work.


rick

 

[Marko]

One difference is that parameters can be over-ridden by the calling
module via the defparam command. Not true with `define.


On 7 Jul 2005 16:16:48 -0700, "Nju Njoroge" <njoroge@stanford.edu>
wrote:

Hi,

I'm using the Verilog-2001 exponential operator to do the following:

`define NUM_COUNTER_BITS 8;
parameter NUM_COUNTER_CYCLES = 2 ** (`NUM_COUNTER_BITS);

When I simulate this in ModelSim 6.0a, launched from Project Nav. (ISE
7.1 SP3), NUM_COUNTER_CYCLLES = 5. However, if I use a parameter for
NUM_COUNTER_BITS instead of `define, as shown below, NUM_COUNTER_CYCLES
= 256, which is the desired result.

parameter NUM_COUNTER_BITS = 8;
parameter NUM_COUNTER_CYCLES = 2 ** (`NUM_COUNTER_BITS);

What are the inherent differences between a parameter and `define
directive that could this problem to occur.

Thanks,

NN

 

[John_H]

"lindberg" <Linzhichu@gmail.com> wrote in message
news:1121168293.745105.144450@g43g2000cwa.googlegroups.com...

Each RAM is small in size(about 6bit*128 or so) and I want to read from
all of them in one clock period. Will such a number of RAMs slow down
my maximum frequency?

If your memories are part of a large pipelined calculation, your performance
should be superb.

If you're tageting an ASIC, your performance should be great. In FPGAs,
keep in mind that the RAMs are typically distributed across the device and
routing these values to one central processing block could be problematic.

If there's a common address for several hundred memories, the fanout on
those lines may require appropriate buffering schemes and/or replication of
the address values.

 

[Mike Treseler]

jjohnson@cs.ucf.edu wrote:

Does anyone know where I can find a public domain / open source tool
that will read a bunch of VHDL and/or Verilog files, and generate a
block diagram from them?

I don't think there is one.
Quartus/Mentor/Synplicity have an hdl viewer
that can do entity boxes and wires.
Modelsim has a data flow viewer that shows
processes and signals.

What would you do with this diagram
if you had it?

If the aim were to learn a design by others,
I would write a testbench and watch
it run on a simulator.

If the aim were to document the
design, I would do it as comments
in the source and testbench code.

-- Mike Treseler

 

[Colin Marquardt]

Mike Treseler <mike_treseler@comcast.net> writes:

If the aim were to document the
design, I would do it as comments
in the source and testbench code.

I document testcases as comments with a special prefix. These are
then filtered out and processed with LaTeX, giving a nice PDF
file. One could also embed diagrams in description languages like
pstricks, metapost, dot, pic etc. and handle them in the same way.
If somebody has already done this, I'd love to hear about it.

To the original poster: take a look at emacs' vhdl-mode and its
integration into speedbar for a hierarchy parser.

Cheers,
Colin

--
If God had not given us sticky tape, it would have been necessary to
invent it. [Pete Zakel]

 

[Monaks]

"John_H" <johnhandwork@mail.com> wrote in message
news8SAe.7$4K6.251@news-west.eli.net...

"lindberg" <Linzhichu@gmail.com> wrote in message
news:1121168293.745105.144450@g43g2000cwa.googlegroups.com...
Each RAM is small in size(about 6bit*128 or so) and I want to read from
all of them in one clock period. Will such a number of RAMs slow down
my maximum frequency?

If your memories are part of a large pipelined calculation, your
performance
should be superb.

If you're tageting an ASIC, your performance should be great. In FPGAs,
keep in mind that the RAMs are typically distributed across the device and
routing these values to one central processing block could be problematic.

ASICs have routing limitations, too. The datapath-architecture needs to be
carefully evaluated for huge "fan-in" bottlenecks (like a hundreds of
1024->1 mux.) If these exist, register-pipelining (as you suggested) may
be advisable.

If there's a common address for several hundred memories, the fanout on
those lines may require appropriate buffering schemes and/or replication
of
the address values.

Yes, that too!

 

[Anton Erasmus]

On Thu, 14 Jul 2005 15:04:53 -0700, Mike Treseler
<mike_treseler@comcast.net> wrote:

jjohnson@cs.ucf.edu wrote:
Does anyone know where I can find a public domain / open source tool
that will read a bunch of VHDL and/or Verilog files, and generate a
block diagram from them?

I don't think there is one.
Quartus/Mentor/Synplicity have an hdl viewer
that can do entity boxes and wires.
Modelsim has a data flow viewer that shows
processes and signals.

What would you do with this diagram
if you had it?

I have found the Quartus RTL Viewer a tremendous help in developing
a feel for what logic would be generated by what code. It is also
immediately obvious if one has left out a default value for a case
structure and other simple errors that make a huge difference in the
generated logic.

If the aim were to learn a design by others,
I would write a testbench and watch
it run on a simulator.

If the aim were to document the
design, I would do it as comments
in the source and testbench code.

It has also been useful where clients have insisted that they want a
schematic version of the EPLD code.

Regards
Anton Erasmus

 

[m]

On 19 Jul 2005 22:56:00 -0700, "priya" <priya11.karthik@gmail.com>
wrote:

Hi All,

I am writing a Verilog Code for Polyphase FIR Filter.In that i
need to give one of the input is taps valus.here i want to give the
taps values in the form of real array type.But as far as i know verilog
simulator dosnt support real array type.


for example taps value is {0.7,0.3,0.9}

how can i give the above tap values in verilog code...
if anyone have answer,plz let me know....

You seem to want to use fixed point numbers in your implementation of
the filter which requires that you convert your coefficients into
fixed point too. You find your largest (in absolute value) coefficient
which decides how many bits you need for the whole part of the fixed
point number. Then you decide how many bits you need for the
fractional part (the part after the decimal point) which is kind of
tricky because ie 0.7 cannot be represented by a finite number of
binary digits (ie there is no power of 2 number when it is multiplied
with 0.7 gives you a whole number) so you have to use approximate
coefficients in your fixed point filter (0.1011001101b is 0.7
described by 10 fractional bits and it has an error of less than 0.03
percent).

Hope this helps somewhat. I don't know a Fixed point DSP tutorial
off-hand. You can google it and see what you can come up with.

 

[Jason Zheng]

Are you trying to use real array as input ports? Verilog 2001 doesn't
support real or array as input ports, however, SystemVerilog will have
this support. If you are not using real array as input ports, Verilog
2001 lets you declare real arrays for simulation purpose. The useage is
the same for declaring integer or register arrays:

real myarray [1:200];

However, as most simulators have not implemented full verilog 2001
support, I'm not sure all simulators support this. I advise you to write
a testbench and try it out.

-jz

priya wrote:

Hi


Thanks for ur replay.....But i want to give real array type input
into the verilog Code. does Verilog simulator support real array type?

U mentioned that fixed point number method ...here i dont know how we
can use this one in verilog code..if u know the answer ,plz explain me.




thanks
priya

 

[jtw]

Pardon me, but every once in a while someone seems to confuse instant/text
messaging with newsgroups. ;-]

Seriously, it makes the postings much easier to read if spelling is
[reasonably] correct.

Sorry, I'm ignorant about SystemVerilog.

Jason

<bharathiii@rediffmail.com> wrote in message
news:1121663013.190052.46300@g43g2000cwa.googlegroups.com...

hi,
thanx for ur valuable reply. currently i am using cadence IUS 5.5,
this version doesn't support features like class,struct,union etc..
actually i have to generate the packet using Systemverilog.can u
help me out ??

 

[kk]

this is not for verilog.
it is mentioned is specifically for vhdl.

 

[kk]

can -defparam be done from command line of ncsim.
i am unable to use this still.

I'm sure there should be a way of doing this from command line itself.
but i still am unable to figure it out

thanks
-kk

 

kk wrote:

can -defparam be done from command line of ncsim.
i am unable to use this still.

There is no way to do this at simulation time. The design has already
been compiled and elaborated with a particular set of parameter values.
It is too late to change them. If you want a different set of
parameter values, you will need to elaborate again. That is why it is
an ncelab option.

If vsim allows changing parameter values from the simulator command
line, this implies that they are waiting until that point to elaborate
the design (i.e. they don't finish compiling until then).

 

[Ajeetha]

Hi,
AFAIK, Modelsim defers part of elaboration to vsim stage. Recently
they also added vsim -elab switch to store snapshot similar to nc's
flow. So this is kind of expected - i.e. vsim can handle -g at "run
time" (though internally it is elab time).

Just my 2 cents
Ajeetha
http://www.noveldv.com

 

[comp.arch.fpga]

On 20 Sep., 20:54, Weng Tianxiang <wtx...@gmail.com> wrote:

On Sep 19, 9:05 pm, John_H <newsgr...@johnhandwork.com> wrote:

Weng Tianxiang wrote:
Hi Hal,
8b/10b is perfect for scrambling function. PCI-e uses 8b/10b
technology.

Scramble technology still uses randomized serial and XOR now? After 8b/
10b technology, I think other randomized XOR scramble technology is
dying out, is it right?

IBM got one patent for 8b/10b technology in 1981, Xilinx filed for 23
patents on 8b/10b implementation in FPGA on one day in 2004.

I think that IBM is really a technology leader in almost all respects
in computer industry. Xilinx is the leader of FPGA.

Weng

Scrambler cannot be counted as a state machine in any sense.
Wrong. Again.

The most important factor for a circuit counted as a state machine is
that its states are mutually exclusive and only one state is active in
any cycle.
Hmm. Any deterministic system can only be in one state. That is the

whole
meaning of "state". Of course there are non deterministic systems. And
also
non deterministic state machines. Just because you cannot code them in
VHDL
does not mean they do not exist. But I am sure you can provide an
extension to
VHDL that supports quantum computing. My suggestion:
if (condition) maybe
dosomething;
anyways
do somethin
beginning of the end;

Scrambler cannot meet the requirements. If it were, every circuit
would be counted as a state machine.

No, just any sequential circuit. Any circuit with state. Wait, maybe
that's
what the name comes from?
http://en.wikipedia.org/wiki/Finite_state_machine

Shift registers can be counted as a state machine only when only one
bit is set or reset among all its bits. Otherwise it cannot be counted
as a state machine.

You still insist on your reset? Read the JTAG specification for gods
sake.

Kolja Sulimma