EDK : FSL macros defined by Xilinx are wrong

[John Larkin]

On Fri, 10 Jun 2005 22:04:01 +0200, "Falk Brunner"
<Falk.Brunner@gmx.de> wrote:

"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> schrieb im
Newsbeitrag news:6asja1deqev84jtunnakfmqunqls0k3e57@4ax.com...

This is the better solution (if you have the layer available) but split
power planes are OK too. Just be carefull, dont use these as reference
planes for high speed lines, this can bite you.


Why? They're all at AC ground.

Yes, but connected through vias + decoupling caps to "real" ground. It
works, but less good than a real ground plane.

They're also connected by the parallel plane capacitance, which is
typically pretty hefty when the dielectrics are properly thin. If you
don't trust power planes for the "return current" you'll need a lot
more ground planes, hence more layers. I do stuff with jitters in the
low single digits of ps, and use microstrip traces referenced to power
planes all the time.

I blame Johnson for all this obsession with "return currents."

John

 

[Falk Brunner]

"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> schrieb im
Newsbeitrag newsibka1p30g1hs69add4jamu01mi9pc8de2@4ax.com...

I blame Johnson for all this obsession with "return currents."

ROFL.
You got me!

Regards
Falk

 

[Falk Brunner]

"Sylvain Munaut" <com.246tNt@tnt> schrieb im Newsbeitrag
news:42a9fdac$0$346$ba620e4c@news.skynet.be...

Take a look at
http://www.xilinx.com/bvdocs/appnotes/xapp157.pdf
For the FG256 they only show two signal layers.

OK, so this proves the old suggestion.
"Use your head before opening your mouth".
;-)

Regards
Falk

 

[Jeremy Stringer]

Gary Pace wrote:

Strange that - you'd have thought if you're making TV's you'd plan to sell
enough to pay for an ASIC

Could be a time-to-market thing Sell lots, then go to asic later.

Jeremy

 

[John Williams]

Jeremy Stringer wrote:

Strange that - you'd have thought if you're making TV's you'd plan to
sell enough to pay for an ASIC

Could be a time-to-market thing Sell lots, then go to asic later.

Or even better (from Xilinx' perspective), reinvest the income from
being early to market into your next generation of product, rather than
spending the big bucks recreating in ASIC something that's already
working and selling.

John

 

[Davy]

Hi,

Yes I know re-timing, it just push pull the register(rely on the
original netlist), but not insert register.

Is there any tool to insert registers?

Thanks!
Davy

 

[Jim Granville]

Jeremy Stringer wrote:

Gary Pace wrote:

Strange that - you'd have thought if you're making TV's you'd plan to
sell enough to pay for an ASIC


Could be a time-to-market thing Sell lots, then go to asic later.

Or a Digital TV effect. I see the FCC is trying to mandate obsolescence
on all Analog TVs in the USA, by forcing a move to digital.

Waste / landfill ? Not our problem!!

This is a high stakes gamble: would you roll an ASIC, or use an FPGA
while you wait to see the what the political fallout and lobbying
brings, once the dust settles ?

-jg

 

[Evan Samuel]

Two possible causes.

1. You are not using the latest version of the Impact tool. When Xilinx
updates the FAB process to various chips, it will sometimes render older
versions of Impact incompatiable. If you haven't purchased the latest
version of ISE, try the Webpack version of Impact from their website.

2. The parallel 3 cable is prone to noise. Check all your connections an
try moving the cable away from any noise sources.



dejavu99@hotmail-dot-it.no-spam.invalid (damidar) wrote in
news:MfidnZJr6fJ5nzLfRVn_vg@giganews.com:

hi....Please help me for a programmer xilinx XC9536XL (parallel LPT)

When i starter to program, it stopped on:

"Error:IMPACT 583 :the idcode read from the device does not match the
idcode in the bsdl"



Help me thanks a lot.....

 

[Evan Samuel]

Try this site:
http://legacy.memec.com/devkits/americas.shtml
http://www.memec.com/?cmd=supplierlanding&supplier=2#7

 

[Ben Jones]

Yes I know re-timing, it just push pull the register(rely on the
original netlist), but not insert register.
Is there any tool to insert registers?

Well, inserting registers changes your design in a fundamental way.
Most circuits I can think of would just stop working if you added
registers to them at random. Only you, the designer, know exactly
how much pipelining it is legal to apply to a given part of your
circuit. So I don't believe such a tool exists - certainly not in the
general case.

Cheers,

-Ben-

 

[David Brown]

Davy wrote:

Hi,

Yes I know re-timing, it just push pull the register(rely on the
original netlist), but not insert register.

Is there any tool to insert registers?

I would think that would be a very bad idea to try to do automatically -
it would completely change your timing. It's one thing to automatically
do re-timing to improve your margins or your maximum clock rate, but
adding registers will change the function of your logic. You might just
as well ask for a tool to insert extra logic to improve your design.

Thanks!
Davy

 

[John_H]

You have to insert your own registers to make the pipeline a desired
latency.
You can then let the tool move the logic across those boundaries.

How would you specify to the tool what you want pipelined, what you don't,
and what the expected final latency in clocks is?
You insert registers in the paths you want piped.

The tool I use to insert registers: vi.


"Davy" <zhushenli@gmail.com> wrote in message
news:1118807485.054216.114960@g14g2000cwa.googlegroups.com...

Hi,

Yes I know re-timing, it just push pull the register(rely on the
original netlist), but not insert register.

Is there any tool to insert registers?

Thanks!
Davy

 

[Symon]

"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message
news:jphsa1doui4mdv1dhnk389ar9dqa8smov2@4ax.com...

On Mon, 13 Jun 2005 09:29:26 -0700, "Symon" <symon_brewer@hotmail.com
wrote:

Single ended?
Cheers, Syms.


Yup.

Wow, I'm impressed! Single ended clock signal I guess, not random data?

Cheers, Syms.

 

[John Larkin]

On Wed, 15 Jun 2005 09:49:36 -0700, "Symon" <symon_brewer@hotmail.com>
wrote:

"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message
news:jphsa1doui4mdv1dhnk389ar9dqa8smov2@4ax.com...
On Mon, 13 Jun 2005 09:29:26 -0700, "Symon" <symon_brewer@hotmail.com
wrote:

Single ended?
Cheers, Syms.


Yup.

Wow, I'm impressed! Single ended clock signal I guess, not random data?
Cheers, Syms.

Here's one of our gadgets, built for the NIF laser...

http://www.highlandtechnology.com/DSS/V880DS.html

All the fast stuff is EclipsLite logic, pecl mode, and most of it is
single-ended except for a major clock which is a diff microstrip.

If you want low jitter, you have to know The Secret.


John

 

[Yttrium]

you also have the init_signal_spy() command in modelsim that you have to add
to your testbench ...


"CODE_IS_BAD" <Puneetsingh81@gmail.com> wrote in message
news:1118730828.471845.41380@g47g2000cwa.googlegroups.com...

Hi all,
I am using ModelSim PE 6.0d. I have done functional simulation for
my design (i could view all internal signals there) and that works
fine. When i run Post P&R simulation i get some misfunctionality. To
correct the same i need to view internal signals in the post P&R
simulation. But the same does not come if we check the signals listed
under UUT.

I know this has been posted some time back also but i could not
understand correctly. If somebody knows the correct procedure then
please help. Thanx in advance.

 

[Falk Brunner]

"Patrick" <patrick.melet@dmradiocom.fr> schrieb im Newsbeitrag
news:54b3002.0506150202.5ba5002c@posting.google.com...

Sometimes, one of the three cards don't program them.
This is the MAX chip which program the FPGA through the Flash Memory.
This chip is connected to the 3.3V

We notice that when the +3.3V is OK, the +1.5V is not really arrive to
1.5V, and so I think that the MAX begin the programmation when the Vcc
core is not OK and that fail the programming sequence ?

You found the problem. Its power sequencing. Use a voltage monitor to
release a reset for the MAX after ALL voltages are stable.

Regards
Falk

 

[Erik Widding]

As someone who is still working with Spartan II, I was amused to see that
my mothers new television has a Spartan 3 inside ...

Strange that - you'd have thought if you're making TV's you'd plan to sell
enough to pay for an ASIC

Actually these TVs are generally based on atleast one ASIC (a video
decoder and scaler), and an FPGA. The FPGA generally has some simple
glue logic, sitting between the ASIC and the LCD panel. LCD panels
from different manufacturers, many of which are available in
mechanically compatible form factors, often have different electrical
and timing characteristics. With the LCD panel the single largest cost
item in a TV, leaving the glue logic programmable allows the
manufacturers to treat the panel as a commodity item. I would not
expect this FPGA "socket" to go away any time soon.


Regards,
Erik.

---
Erik Widding
President
Birger Engineering, Inc.

(mail) 100 Boylston St #1070; Boston, MA 02116
(voice) 617.695.9233 x207
(fax) 617.695.9234
(web) http://www.birger.com

 

[c d saunter]

Ben Jones (ben.jones@xilinx.com) wrote:
: > Yes I know re-timing, it just push pull the register(rely on the
: > original netlist), but not insert register.
: > Is there any tool to insert registers?

: Well, inserting registers changes your design in a fundamental way.
: Most circuits I can think of would just stop working if you added
: registers to them at random. Only you, the designer, know exactly
: how much pipelining it is legal to apply to a given part of your
: circuit. So I don't believe such a tool exists - certainly not in the
: general case.

This is very true, but there's no reason a designer couldn't specify a
bunch of signals (e.g. the data signal from a combinatorial multiply and
associated control signals) and some tool would add aribtrary (to a user
specified limit) stages of pipelining to all signals to meet timing, with
logic/register shuffling. This would only work the control and data flows
can be aribtrarily pipelined, but many ops can be described this way/

A half way house to acheive this is to use current register shuffling on
the data signals and experimentally add registers to reach timing, and
then pipline associated control signals. If done using a VHDL generate
tc. it's a two second text editor job to do the later.

If someone writes the tools then the whole operation could be scripted,
with the logic to be messed and associated signals isolated in a soure
file.

All in all construtive use of a text editor on the source is much less
hastle

---
cds

 

[Ben Twijnstra]

Hi Jeremy,

Gary Pace wrote:
Strange that - you'd have thought if you're making TV's you'd plan to
sell enough to pay for an ASIC

Could be a time-to-market thing Sell lots, then go to asic later.

You're absolutely right. TV makers make a new TV asic every, let's say,
three years, in order to minimize NRE cost.

New features are being implemented in FPGA _and_ incorporated in the
next-generation ASIC. After three years, you'll have an FPGA-less TV, with
one _with_ FPGA (with new features) coming out the year after, etc etc.

Also, I've written LCD driver code for [TV maker] so that they could be
flexible with panel timing and signalling, thereby freeing them from panel
maker lock-in, and start designing for panels whose specs weren't quite
finished yet.

Best regards,


Ben

 

[sps]

Thanx ppl.

Can I do something like we do with any spartan device, I mean without
using anything(Processor,IPs,Buses), can I map my application on
Virtex2Pro?

Thanx

Regards

sps