EDK : FSL macros defined by Xilinx are wrong

Thanks Rob.

How do I tell Quartus that I want a specific pin to be open drain? Do
I have to do something special? Or is it automatic and transparent to
the user?


Thanks,
Ernie
 
ernie wrote:

How do I tell Quartus that I want a specific pin to be open drain? Do
I have to do something special? Or is it automatic and transparent to
the user?
Click to expand...
It will be inferred automatically from the code
if you write it as Sylvain suggested.

my_od_out <= '0' when my_od_sig = '0' else 'Z';

Picking the pin number for my_od_out
is best done with the Quartus GUI.

-- Mike Treseler
 
"Peter Alfke" <peter@xilinx.com> schrieb im Newsbeitrag
news:1120668551.532800.247620@g14g2000cwa.googlegroups.com...

IT is interesting that despite this frenzy about top speed, most users
always buy the (cheaper) slow speed grades... Makes you wonder what's
so important.
Click to expand...
"Geiz ist geil", a slogan heavily used in advertising of a big electronic
market chain.
;-)

This reminds me of car advertising in Europe, where top speed used to
be the big issue.
"My fast 260 kmph BMW is better than your slow 255 kmph Mercedes !"
Nowadays, the distinction is more about important issues, like the
number of cupholders and foldable back seats...
Click to expand...
Even on the Autobahn here, most top ten cars are limited by electronic, not
engine power. So all the BMW, Mercedes, Porsche easily reach 250 km/h, when
the electronic suddenly decides, "That enough, dude".

Regards
Falk
 
In article <1120654853.854340.227610@z14g2000cwz.googlegroups.com>,
Jon Beniston <jon@beniston.com> wrote:
So a SII -3 is faster than a SII -5, and V4 -10 is slower than V4 -12.

Do I detect a hint of NLP there? :)
Click to expand...
Xilinx used to do the same tihng. But when they were in danger (with
the continued processing/development) of having a XC4000 - -1, they
decided to switch the numbering scheme to "Higher is faster" with the
Virtex line.
--
Nicholas C. Weaver. to reply email to "nweaver" at the domain
icsi.berkeley.edu
 
Duane Clark wrote:
Nju Njoroge wrote:
Hi,

I'm using ModelSim SE 6.0a with ISE 7.1 (SP 2) and EDK (SP 1). I get
the following error with the PPC SmartModel.

# Loading work.ppc405_0_wrapper(structure)
# Loading C:/simlib/EDK_Lib/ppc405_v2_00_c/.ppc405_top(structure)
# Loading C:/simlib/unisim/.ppc405(ppc405_v)
# Loading C:/simlib/unisim/.ppc405_swift_bus(ppc405_swift_bus_v)
# Loading C:/simlib/unisim/.ppc405_swift(smartmodel)
# Loading c:\Modeltech_6.0a\win32/libsm.dll
# ** Error: Unable to read LMC SmartModel library file "** Fatal:
Foreign module requested halt.
# Time: 0 ps Iteration: 0 Instance:
/system/ppc405_0/ppc405_0/ppc405_i/ippc405_swift/ppc405_swift_inst
File: C:/Xilinx/smartmodel/nt/wrappers/mtivhdl/smartmodel_wrappers.vhd
# FATAL ERROR while loading design
# Error loading design
# Error: Error loading design

The VHDL file,
C:/Xilinx/smartmodel/nt/wrappers/mtivhdl/smartmodel_wrappers.vhd, is
where it is supposed to be and it looks legit when I open it. Also, I
recently upgraded from EDK 6.3, in which the SmartModel worked well. In
the upgrade, I followed the usual set of procedures
(http://www.xilinx.com/ise/embedded/ps_ug.pdf, page 120). Additionally,
all the simulations were re-compiled for the new versions of ISE and
EDK.

The smartmodel_wrappers.vhd does not appear to be your problem. The
error message claims the problem is with the "LMC" library. This would
probably be defined in your modelsim project file with a line like:

libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so

Have you made sure that the combination of the environment variable and
the rest of the line points to the correct file?
Yes, I have these variables set appropriately (as instructed by the
Click to expand...
Platform Studio User Guide, page 120). In my modelsim.ini, I have:

libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll

where $LMC_HOME points to %XILINX%\smartmodel\nt\installed_nt.

I did not change this configuration when upgrading from 6.3 to 7.1. In
6.3, this used to work, but it no longer does for 7.1.
 
Duane Clark wrote:
A clk_rd event happens to occur in the time between when fast_event has
arrived, but not all of the fast_column signals. If the clocks are truly
asynchronous, this is guaranteed to happen occasionally. The fast_event
causes slow_event to be captured, but only part of the slow data,
because not all the fast data has arrived yet.
Click to expand...
Also, I should point out that since fast_event goes to all the slow side
registers, it arrives at each individual register at different times,
which is another source of asynchronous problems.

There is a simple rule for situations where that can happen. If a
control signal crossing a clock domain goes to multiple places, then it
must go through a synchronizing flipflop first.
 
Well....

First, let me ask "why"? What's the logic functionality you are after?

Second, what you are doing is driving a net from two different processes,
which unacceptable by the synthesis tool.
try replacing two last processes into one as following:

always @(posedge clk or posedge b)
begin
if (b) c <= 1;
else c <= 0;
end

Vladislav


"vssumesh" <vssumesh_asic@yahoo.com> wrote in message
news:1120660339.335787.104570@g49g2000cwa.googlegroups.com...
hello all,
i have some doubt on the timing specs of FF set and rests.
I wrote the folllowing code in verilog.

always @(posedge clk)
if (a == 0) b <= clk;
else b <= 0;

always @(posedge b)
c <= 1;

always @(posedge clk)
c <= 0;


my intention was to momentarly rest the 'c' and if 'a' is true then
turn it back on. But the synthesizer gave error stating that
simultanious assign ment is not possible. How can i achive this . i
though like setting 'b' will take time thus the setting and resiing of
'c' will take place at differnt times. please give me comments on this
issue.
Click to expand...
 
"Nicholas Weaver" <nweaver@soda.csua.berkeley.edu> schrieb im Newsbeitrag
news:dah51p$1toj$1@agate.berkeley.edu...

In article <3j2j7qFnsjmeU1@individual.net>,
Falk Brunner <Falk.Brunner@gmx.de> wrote:
Even on the Autobahn here, most top ten cars are limited by electronic,
not
engine power. So all the BMW, Mercedes, Porsche easily reach 250 km/h,
when
the electronic suddenly decides, "That enough, dude".

I know the BMW and Mercedes have the limiters, but I thought Porsche
said "We ain't gentlemen, we aren't holding to the gentlemen's
agreement"
Click to expand...
Hmm, dont know at all. I don't own a Porsche. Yet . . . ;-)

Regards
Falk
 
In article <3j2j7qFnsjmeU1@individual.net>,
Falk Brunner <Falk.Brunner@gmx.de> wrote:
Even on the Autobahn here, most top ten cars are limited by electronic, not
engine power. So all the BMW, Mercedes, Porsche easily reach 250 km/h, when
the electronic suddenly decides, "That enough, dude".
Click to expand...
I know the BMW and Mercedes have the limiters, but I thought Porsche
said "We ain't gentlemen, we aren't holding to the gentlemen's
agreement"
--
Nicholas C. Weaver. to reply email to "nweaver" at the domain
icsi.berkeley.edu
 
On Tue, 05 Jul 2005 21:49:09 -0600, Dave wrote:

Is the Xilinx Virtex 4 the fastest FPGA available in in-circuit
reprogrammable format?

Their data sheet claims 450MHz PPC and 500MHz DSP. The -12 speed grade of
the XC4VFX40 or 60 devcies sound like they won't be available until next
year, though.

I couldn't find definitive data in the Altera literature about the speed of
the Stratix II parts. Do these parts run at speeds approaching the Virtex 4
parts?

Does Lattice offer high-speed devices with built-in microprocessor, DSP, and
RAM support? It appears the EC family supports RAM at up to 200MHz.

Thanks.

Dave
Click to expand...
Even though the Xilinx and Altera FPGA appear very similar there are
subtle differences which leads to different choices depending on the
target for you design. I'll give you a simple example, Block RAMs. The
Block RAMs in Virtex2P are faster then the Block RAMs in the Stratix II in
single pipeline mode, i.e. no output register. However the Stratix II
includes an optional output register in the Block RAM component, the
Virtex2P doesn't have an output register (the Virtex4 does). If you use
the output register in the Stratix II then the Stratix II will be faster,
if you don't then the Virtex2P will be faster. So if you were targeting a
design for the Virtex2P you probably won't register the outputs of your
Block RAMs unless you are shooting for a very high frequency because the
registers use up precious flip flips. If you then move the design to a
Virtex2P it will run slower. However if you were designing for the Stratix
II you would use output register because they are free and they'll
simplify routers task because it will have a easier time meeting timing.
If you then move the design to a Virtex2P it will be bigger and it might
be slower because the output register would have to be instantiated in
flip flops. There are lots of choices like that, another example is LUT
RAMs and LUT based shift registers which Xilinx has and Altera doesn't.
because they are there you'll use them if you are targeting Xilinx which
means that that design will be bigger and slower if you put it into an
Altera part. This sort of thing goes both ways, the Altera M512 RAM is 32
deep so if you are targeting an Altera part you will probably make your
small FIFOs 32 words deep, if you then move it to a Xilinx part you'll
need 4 LUTs per bit which will make the design bigger and slower in the
Xilinx part.

The bottom line is that if Altera and Xilinx each gather up a 1000 designs
from their own customer bases and then build for both architectures each
will find that their own architecture is 20% faster then the other guy's.
Neither will be lying, the results will clearly show that their own
architecture is significantly better in an overwhelming number of cases.
The problem is in the sample, if you ask Germans and Englishmen which is
better Lager or Ale you'll get a different answer.
 
Nju Njoroge wrote:
Duane Clark wrote:
Nju Njoroge wrote:
Hi,

I'm using ModelSim SE 6.0a with ISE 7.1 (SP 2) and EDK (SP 1). I get
the following error with the PPC SmartModel.

# Loading work.ppc405_0_wrapper(structure)
# Loading C:/simlib/EDK_Lib/ppc405_v2_00_c/.ppc405_top(structure)
# Loading C:/simlib/unisim/.ppc405(ppc405_v)
# Loading C:/simlib/unisim/.ppc405_swift_bus(ppc405_swift_bus_v)
# Loading C:/simlib/unisim/.ppc405_swift(smartmodel)
# Loading c:\Modeltech_6.0a\win32/libsm.dll
# ** Error: Unable to read LMC SmartModel library file "** Fatal:
Foreign module requested halt.
# Time: 0 ps Iteration: 0 Instance:
/system/ppc405_0/ppc405_0/ppc405_i/ippc405_swift/ppc405_swift_inst
File: C:/Xilinx/smartmodel/nt/wrappers/mtivhdl/smartmodel_wrappers.vhd
# FATAL ERROR while loading design
# Error loading design
# Error: Error loading design

The VHDL file,
C:/Xilinx/smartmodel/nt/wrappers/mtivhdl/smartmodel_wrappers.vhd, is
where it is supposed to be and it looks legit when I open it. Also, I
recently upgraded from EDK 6.3, in which the SmartModel worked well. In
the upgrade, I followed the usual set of procedures
(http://www.xilinx.com/ise/embedded/ps_ug.pdf, page 120). Additionally,
all the simulations were re-compiled for the new versions of ISE and
EDK.

The smartmodel_wrappers.vhd does not appear to be your problem. The
error message claims the problem is with the "LMC" library. This would
probably be defined in your modelsim project file with a line like:

libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so

Have you made sure that the combination of the environment variable and
the rest of the line points to the correct file?
Yes, I have these variables set appropriately (as instructed by the
Platform Studio User Guide, page 120). In my modelsim.ini, I have:

libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll

where $LMC_HOME points to %XILINX%\smartmodel\nt\installed_nt.

I did not change this configuration when upgrading from 6.3 to 7.1. In
6.3, this used to work, but it no longer does for 7.1.
I resolved the issue and now the error goes away: I noticed that my
Click to expand...
installation of ISE was an evaluation one (the one that comes with the
EDK CD's), so I installed the real version (the one that comes in the
ISE CD packages). For some reason, the eval version wasn't properly
compiling the libraries and/or preventing the usage of the
SmartModel... In any case, using the non-eval version got it running.

NN
 
Many thanks to all who responded. Very helpful input. It's given me some
good data to examine.

My application requires multiple stamps of very fast DSPs (for data
acquistion and filtering), a high-speed RAM interface (to store the
acquistion results), failry high-speed disk operations (to off-load and
archive the acquistion results), and several slower-speed housekeeping tasks
(user control input and display output, etc.), which could be handled by an
embedded "soft" processor.

It sounds like the Virtex 4 or the Stratix II is probably the right approach
in this application.


Dave


"Dave" <starfire151@cableone.net> wrote in message
news:11cml61qpqtaq81@corp.supernews.com...
Is the Xilinx Virtex 4 the fastest FPGA available in in-circuit
reprogrammable format?

Their data sheet claims 450MHz PPC and 500MHz DSP. The -12 speed grade of
the XC4VFX40 or 60 devcies sound like they won't be available until next
year, though.

I couldn't find definitive data in the Altera literature about the speed
of the Stratix II parts. Do these parts run at speeds approaching the
Virtex 4 parts?

Does Lattice offer high-speed devices with built-in microprocessor, DSP,
and RAM support? It appears the EC family supports RAM at up to 200MHz.

Thanks.

Dave
Click to expand...
 
Thanks again Phil,

I'll definitely get rid of the clock mux and see what happens to the
output. I've tested the re-loading of coefficients by applying an unit
pulse input and could see that the filter output (impulse response) was
as expected, ie. out came the coefficient set which was loaded in. So
I'd clearly expect the loading of coefficients to be identical under
conditions where the input was a sine wave, but something is clearly
wrong somewhere. So I'm willing to resort to re-designing using good
techniques, and clearly clock muxing is not one of them, even if
chipscope seems to be telling me that things are ok. If this fails then
I will look at the constraints issues.

--Peter Celinski
peter (AT) geckoaudio dot com
 
If the 200 part die is pad limited then the die size(and therfore
cost?) is more closely related to the number of pads(IO) rather than
the amount of logic.

Maybe the 400 is not pad limited.

Who knows how Xilinx do their pricing, if its based on value to the
customer - maybe IO is more important to the customer than logic at
those logic densities.

If you are looking at small production volumes I would choose a single
part to minimise development cost. If larger volumes then I would have
thought this pricing is not so relevant anyway.
 
I've visited the xess website; however, there's only one example for
mouse and the source codes are in Spanish. Anyways, I tried to figure
out what those codes mean and downloaded the bitstream to the fgpa;
however, that doesn't work. I am not sure whether the code is not
working or I have set something wrong. Anybody has experience using
the PS/2 port of XSA-3S1000 board with XST 3.0?
If I just wanna read the mouse, do I have to initialize the mouse
first? If then, how?
 
Austin Lesea <austin@xilinx.com> writes:

<snip>
http://www.xilinx.com/products/virtex4/overview/performance.htm

is a good review of V4, which illustrate how we beat all other FPGAs
in EVERY category.
Click to expand...
Interesting - why did you not use Synplify for the Altera side of
things - was it worse than Altera's synthesiser?

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt
 
Austin Lesea schrieb:

In order to remove or minimize the variation in timing in SOI from the
floating wells, one needs to add taps. The addition of the taps to
every well, results in the area increasing dramatically. That makes the
FPGA cost too much, hence the process is not commercially viable. This
has been one of the reasons for its non-use.
Click to expand...
Also, without knowing as much detauls as austin, I suspect that in a
design as heavily dominated by interconnect as an FPGA the area increase
results in longer wires which increases capacitance and therefore power
consumption and delay. This mitigates the two main advantages of SOI.

Kolja Sulimma
 
hello...any pings to my above problem is highly appreciated....

thanking you

jaggu
 
HI Allan,

I am myself looking for the same. Am using EDK6.3/ISE6.3i. I am also
told that there is no XBD included even in EDK7.1 for the ML402 board.

Allan, were you able to build the reference design without any errors?
For me, the reference design generates lots of errors about unavailable
versions of peripherals referenced in the design. What service packs
are you using.


Any help appreciated.

TIA,

Abhishek
 
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