EDK : FSL macros defined by Xilinx are wrong

[Jeremy Stringer]

Paul Boven wrote:

Having studied the datasheet quite well before getting into this, it is
a lot easier for me to map a desired circuit into FFs, LUTs and the
like. Learning VHDL or even using the schematic editor, feels like a
terribly involved way to convince the software to configure those LUTs
the way I want them. So yes, I can imagine some demand for a FPGA layout
tool that stays this close to the hardware. But 'realy slick and
commercial' probably would put it out of my reach.

HDL's not too bad for laying things out like this, if you have regular
structures, because you can express the relationships algorithmically,
and then easily mix and match this structural code with higher level,
less speed critical HDL code.

My 2c,
Jeremy

 

[Alex Gibson]

"Dimitri Turbiner" <dima_turbiner@yahoo-dot-com.no-spam.invalid> wrote in
message news:UeqdnS6cqvrGQTXfRVn_vg@giganews.com...

Hi Alex, I couldn't find your original email so I thought posting on
CAStalk
Here's my original message:


Hi Alex,

I'm Dimitri Turbiner.
Actually I'm extremely interested in working exactly
on the XUPv2p board and since I saw your post on
CAStalk that you have already a working instalation of
Linux I would like to ask you some questions:

No I'm not the one with the working version of linux yet.
A few people on the uclinux microblaze mailing list have.

I suggest posting on the mailing list and asking them your questions.

John Williams has uclinux working on it.
http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux

original messages were on the uclinux microblaze mailing list
http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/
see below for messages

I'm still waiting on the board to be purchased
(takes a while through the university)

Alex

From the original messages dated 29.04.2005


Or http://www.crhc.uiuc.edu/IMPACT/gsrc/hardwarelab/docs/kernel-HOWTO.html

I've already used these helpful references to get a Linux kernel running on
the PowerPC405 on the Digilent XUP-V2Pro board. I'm new to ucLinux but it
doesn't appear to be much more complicated than the ucLinux steps.

Paul Hi Aurash, hi John,

We are working with the PPC on virtex2p. You do not need Monta Vista
Linux.
All you need is denx eldk: http://www.denx.de/twiki/bin/view/DULG/ELDK
And the penguin ppc linux distribution:
http://www.penguinppc.org/kernel/#developers
(we are using the 2.4 Kernel)
To get started: http://www.klingauf.de/v2p/index.phtml might be helpful.

On the other hand we are also using uClinux on spartan3.
It is really a question of what hardware you have and what you want to do
;-)

Have Fun
Jan

 

[dlharmon]

Without knowing what PCB technology you're using, it's impossible to say.
Here are a few questions off the top of my head.
Can you use microvias? What's your minimum track width? Minimum gap between
tracks? What's the biggest BGA package on the board? Are you prepared to
swap pins on the FPGA to aid the routing process? Is your volume enough to
make it worth spending a lot of time on the layout? How fast are your
risetimes and how long are your traces? Do you have Hyperlynx? Are you gonna
insist on a plane for each of your power supplies, or do you know what
you're doing? ;-)

256 pin BGA, 4mil tack/gap, uvias, two ground planes, routed powers,
quick(ish) turnaround, long and fast traces = 6 layers, maybe even 4 with
one ground plane if you're quite talented and have a lot of time.
Cheers, Syms.
p.s. Simetry (sic)? Pah, I spit on symmetry.

I have laid out my first board using the FT256. I have not had it
fabricated yet. It is 4 layers 6/6mil track/space. The real killer was
the size of the vias. I used 1 solid groundplane and planelets for
VCCIO VCCAUX and VCCCORE. All IO voltages are the same which helps. I
was not able to route out all the IO. I have posted a PDF file
containing the PCB layers at http://dlharmon.com/dspcard.pdf Any
comments on whether or not it will have decent signal integrity would
be appreciated. Maybe it can provide some ideas.

Darrell Harmon
http://dlharmon.com

 

[John Williams]

Alex Gibson wrote:

John Williams has uclinux working on it.
http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux

Credit where credit's due - Paul Hartke did the work, I'm just hosting
the files!

John

 

[Alex Gibson]

"John Williams" <jwilliams@itee.uq.edu.au> wrote in message
news:newscache$9unuhi$4kd$1@lbox.itee.uq.edu.au...

Alex Gibson wrote:

John Williams has uclinux working on it.
http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux

Credit where credit's due - Paul Hartke did the work, I'm just hosting the
files!

John

I thought, Paul had linux running on the v2pro board ?

So he got uclinux running as well. Good

I'm tempted to buy one of the xupv2p boards myself
rather than wait and share the one at uni.

Paul Hartke wrote:

Or http://www.crhc.uiuc.edu/IMPACT/gsrc/hardwarelab/docs/kernel-HOWTO.html

I've already used these helpful references to get a Linux kernel running
on
the PowerPC405 on the Digilent XUP-V2Pro board. I'm new to ucLinux but it
doesn't appear to be much more complicated than the ucLinux steps.

Paul

Alex

 

[Joey]

Hi,

Recently I was trying to implement a plb peripheral. I made a plb peripheral
device using the "Create/Import Peripheral" utility and edited the
user_logic.vhd file according to what I needed. I didn't forget to Import
the peripheral after editing.
Now here is the problem. When I used this peripheral in XPS and generated
the netlist, it gave me the following error and exited.


XST synthesis
plb_decoder_0_wrapper (plb_decoder_0) -
E:\Test\xps_decoder\try01\system.mhs:63
- Running XST synthesis
ERROR:Xst:813 -
E:/Test/xps_decoder/try01/pcores/plb_decoder_v1_00_a/hdl/vhdl/user_logic.vhd
line 53: Body of function UNSIGNED_NUM_BITS not found.
ERROR:MDT - HDL synthesis failed!
INFO:MDT - Refer to
E:\Test\xps_decoder\try01\synthesis\plb_decoder_0_wrapper_xst.srp for
details
ERROR:MDT - platgen failed with errors!
make: *** [implementation/reset_block_wrapper.ngc] Error 2
Done.

The plb_decoder_0_wrapper_xst.srp fiel doesn't say much either. It just
exits where it enters the user_logic.vhd file after the library
declarations. I am also giving a part of the .pao file where all my files
listed can be seen:

lib plb_decoder_v1_00_a support_4M_pk
lib plb_decoder_v1_00_a parameter_4M_pk
lib plb_decoder_v1_00_a derived_param_4M_pk
lib plb_decoder_v1_00_a types_4M_pk
lib plb_decoder_v1_00_a Bit_Node <== UNSIGNED_NUM_BITS is in this file
lib plb_decoder_v1_00_a Shuffle_controller
lib plb_decoder_v1_00_a barrel_shift
lib plb_decoder_v1_00_a decoder_4M_top
lib plb_decoder_v1_00_a generic_dual_port_ram
lib plb_decoder_v1_00_a serialnode
lib plb_decoder_v1_00_a top_interface
lib plb_decoder_v1_00_a user_logic
lib plb_decoder_v1_00_a plb_decoder

I have the above mentioned function in my Bit_Node (.vhd) file which also
accesses all those 4 packages already mentioned in the first 4 lines. Can
anybody help me ?

Joey

 

[Falk Brunner]

"dlharmon" <harmon.darrell@gmail.com> schrieb im Newsbeitrag
news:1118373181.586925.297720@f14g2000cwb.googlegroups.com...

I have laid out my first board using the FT256. I have not had it
fabricated yet. It is 4 layers 6/6mil track/space. The real killer was
the size of the vias. I used 1 solid groundplane and planelets for

??? How is it possible to fanout the balls on just 2 signal layers (1 layer
is "lost" for Ground, the other for VCC)? Or do you mean a 6 layer board
(which leaves 4 layers for signals)?

Regards
Falk

 

[Sylvain Munaut]

Falk Brunner wrote:

"dlharmon" <harmon.darrell@gmail.com> schrieb im Newsbeitrag
news:1118373181.586925.297720@f14g2000cwb.googlegroups.com...


I have laid out my first board using the FT256. I have not had it
fabricated yet. It is 4 layers 6/6mil track/space. The real killer was
the size of the vias. I used 1 solid groundplane and planelets for


??? How is it possible to fanout the balls on just 2 signal layers (1 layer
is "lost" for Ground, the other for VCC)? Or do you mean a 6 layer board
(which leaves 4 layers for signals)?

With 4mil track/space, it's possible to escape all but a few of the
signals on the top layer only. And you can connect the IO you can't
escape directly to VVCO or GND to improve SSO.
You obviously don't escape all balls, only the signals. The power balls
are connected thru via directly to the plane.

IIRC the "official" escape pattern for FT256 is 6/6 and uses top &
botton layer only.


For the posted PDF, I find that the via restring is a little big and
makes big hole in the powerplane. Most notably, the power distributed by
the "annular" power plane looks like it's seriously cut at some place.



Sylvain

 

[Falk Brunner]

"Sylvain Munaut" <com.246tNt@tnt> schrieb im Newsbeitrag
news:42a9c242$0$329$ba620e4c@news.skynet.be...

With 4mil track/space, it's possible to escape all but a few of the

Iam working on a design right now where we have to push a differential pair
between 1mm pitch balls. **** pinout.
But 4mil stuff isnt the thins you want. Expensive and not available from too
many companys.

signals on the top layer only. And you can connect the IO you can't
escape directly to VVCO or GND to improve SSO.
You obviously don't escape all balls, only the signals. The power balls
are connected thru via directly to the plane.

IIRC the "official" escape pattern for FT256 is 6/6 and uses top &
botton layer only.

I doubt it. For a BGA fanout, you need n/2-1 signal layers, where n is the
number of rows/columns (assuming you have a complete ball grid without space
in the center. So for a 16x16 (FG256) you need 7 signal layers. To our
advantage, the inner balls are just VCC/GND, so you get away with 4 signal
layers.

Regards
Falk

 

[Falk Brunner]

"calaf" <calaf_calaf_calaf@yahoo-dot-es.no-spam.invalid> schrieb im
Newsbeitrag news:jYGdnT7auunXIDTfRVn_vg@giganews.com...

problem. Shouldn't a power plane be below or above all the pins of
the FPGA as it happens with ground planes?

This is the better solution (if you have the layer available) but split
power planes are OK too. Just be carefull, dont use these as reference
planes for high speed lines, this can bite you.

Regards
Falk

 

[John_H]

"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message
news:3gtr2mFe8vkdU1@individual.net...

??? How is it possible to fanout the balls on just 2 signal layers (1
layer
is "lost" for Ground, the other for VCC)? Or do you mean a 6 layer board
(which leaves 4 layers for signals)?

Regards
Falk

Top layer takes front 2 rows of balls out without vias.
The next two rows come out the bottom layer with vias.
Both situations take 1 signal between ball or via.

Now - there are 4 signals left in the 5th row for the Spartan3 in the FT256
package - what about them?

By spreading the fanout from the center out, there's a cross where vias
aren't populated. If one can fit two extra signals where the via would have
been (easy) the inside 2 vias on the 5th row can route to the open channel
and the 4th row vias for the center 2 rows fan out toward the center. The
outside 2 vias on the 5th row fan out, changing the 4th row vias from inward
fanout to outward fanout.

Looks clean. There's still room for another signal on the top layer in the
middle where the fanouts spread away from the center.

The ASCII art will look clean only if viewed with a fixed-space font:

| | | | | | | | | | | | | | | | | | | |
| O | O | O | O | |.| | O | O | O | O |
\ \ | / / / \ \ \ \ | /
O O | O O / . \ O O O | O
.--' `--. /
X O O' X . X `O O X

 

[Symon]

"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message
news:3gtukiFebfpaU1@individual.net...

Iam working on a design right now where we have to push a differential
pair
between 1mm pitch balls. **** pinout.
But 4mil stuff isnt the thins you want. Expensive and not available from
too
many companys.

Are you sure? I thought this was industry standard now. It's a 'no added

cost' feature from our pcb house.

I doubt it. For a BGA fanout, you need n/2-1 signal layers, where n is the
number of rows/columns (assuming you have a complete ball grid without
space
in the center. So for a 16x16 (FG256) you need 7 signal layers. To our
advantage, the inner balls are just VCC/GND, so you get away with 4 signal
layers.

Which is why you should use uvias. 4 mil track gap and microvias gets 8

balls deep out without a through via. The money you spend on uvias is easily
recouped on layers saved. And your SI is much better. Great for diff pairs.
Cheers, Syms.

 

[Symon]

"calaf" <calaf_calaf_calaf@yahoo-dot-es.no-spam.invalid> wrote in message
news:jYGdnT7auunXIDTfRVn_vg@giganews.com...

As far I can gather I find some issues: There are some disposition of
vias on the 2.5V planelet that reduce significatively the path's
width for currents (and therefore it raises the impedance.

The vias are plated through. With metal. Like Khan, you're thinking too two

dimensionally. Think like Mr. Spock.

I have
found quite interesting the method used to take the 3.3V to the VCCO
pins but I wonder whether a trace (instead of a plane is not a
problem. Shouldn't a power plane be below or above all the pins of
the FPGA as it happens with ground planes?

No. That's why they invented bypass caps.

Cheers, Syms.

 

[Marc Randolph]

Paul Boven wrote:

JJ wrote:
[...]
I wonder how much demand there would be for a realy slick and
commercial FPGA layout tool that had at least a basic model of the LUTs
and wiring delays that could be correlated with actual devices. I have
some ideas on this but other projects come 1st.

The following layout tools have correlated models of LUTs and wiring
delays:

Amplify from Synplicity
Precision from Mentor
And has Gabor said, PlanAhead, which now belongs to Xilinx.

Having studied the datasheet quite well before getting into this, it is
a lot easier for me to map a desired circuit into FFs, LUTs and the
like.

Howdy Paul,

Mapping is a different issue than having good visability into actual
delays or floorplanning as the others have been discussing.
Interesting, but different.

Learning VHDL or even using the schematic editor, feels like a
terribly involved way to convince the software to configure those LUTs
the way I want them.

Sorry - how exactly are you going to input your design? Using FPGA
editor? User/input-error would kill you, not to mention portability is
basicly zero - so you get to do it all again when you move from a
Spartan II to a Spartan IIE.

But to address your main point, the vendors typically DO provide a way
to do what you describe: you can instantiate the LUTs or FF's
individually with HDLs or schematic tools. Then you're in full control
of how stuff is mapped. Of course, this greatly hampers portability as
well because different chips have different primitives.

For designs of a few hundred to maybe a few thousand LUTs, I guess I
could see being able to map logic to LUTs manually. For anything more
than that, do you really want to spend hours upon hours for even the
simpliest of designs doing what the tool could do in mere minutes with
(usually) acceptable results?

You'll also be missing out on non-obvious optimizations that the tools
could do for you.

In my mind, the main goal of HDL is to provide a standard method of
inputting a design that is mostly vendor independant. A side benefit
is that in some cases, it provides efficient ways to describe more
complex functions. If the tools aren't mapping logic correctly or
efficiently, they need to be improved, not thrown out.

So yes, I can imagine some demand for a FPGA layout
tool that stays this close to the hardware. But 'realy slick and
commercial' probably would put it out of my reach.

The above three tools would probably fall into the really slick and
commerical category.

Have fun,

Marc

 

[John Larkin]

On Thu, 09 Jun 2005 11:17:34 -0500,
calaf_calaf_calaf@yahoo-dot-es.no-spam.invalid (calaf) wrote:

Hi all, I am new in this forum, and I have not found a question as the
stated below. Sorry if it has already done. I have been designing
with Spartan-3 and as a consequence of the number of different power
suply and the pinout distribution on the board it is impossible to me
to have a very reduced number of pcb layers. Allowing for simetries
between powers and gnd layers on the stack I almost can't decrease
from ten. Is there any idea I am missing? maybe as 2.5 V is only
used in configuration I can create islands on the 3.3V layer and
share the ground layer return between both power supply?
I think there must be something else that allow me to work effitienly
wilt fewer layers.
Thanks in advance

I did an S2E in the FG456 package in 8 layers, 6 mil design rules in
places. The same arrangement would probably work for an S3 with three
supplies if you split one of the power planes. The trick of course is
to not go nuts with bypass caps.

I could post some layer pics to alt.binaries.schematics.electronic if
there's demand.

John

 

[John Larkin]

On Fri, 10 Jun 2005 18:46:51 +0200, "Falk Brunner"
<Falk.Brunner@gmx.de> wrote:

"calaf" <calaf_calaf_calaf@yahoo-dot-es.no-spam.invalid> schrieb im
Newsbeitrag news:jYGdnT7auunXIDTfRVn_vg@giganews.com...

problem. Shouldn't a power plane be below or above all the pins of
the FPGA as it happens with ground planes?

This is the better solution (if you have the layer available) but split
power planes are OK too. Just be carefull, dont use these as reference
planes for high speed lines, this can bite you.

Why? They're all at AC ground.

John

 

[Falk Brunner]

"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> schrieb im
Newsbeitrag news:6asja1deqev84jtunnakfmqunqls0k3e57@4ax.com...

This is the better solution (if you have the layer available) but split
power planes are OK too. Just be carefull, dont use these as reference
planes for high speed lines, this can bite you.


Why? They're all at AC ground.

Yes, but connected through vias + decoupling caps to "real" ground. It
works, but less good than a real ground plane.

Regards
Falk

 

[dlharmon]

Falk Brunner wrote:

"dlharmon" <harmon.darrell@gmail.com> schrieb im Newsbeitrag
news:1118373181.586925.297720@f14g2000cwb.googlegroups.com...

I have laid out my first board using the FT256. I have not had it
fabricated yet. It is 4 layers 6/6mil track/space. The real killer was
the size of the vias. I used 1 solid groundplane and planelets for

??? How is it possible to fanout the balls on just 2 signal layers (1 layer
is "lost" for Ground, the other for VCC)? Or do you mean a 6 layer board
(which leaves 4 layers for signals)?

Regards
Falk

It isn't. I just used about 120 of the 171 IO. I used a solid ground
plane and another plane for power. The first 2 rows were brought out
on top and a few IO were brought out on the bottom.

Darrell Harmon

 

[dlharmon]

calaf wrote:

As far I can gather I find some issues: There are some disposition of
vias on the 2.5V planelet that reduce significatively the path's
width for currents (and therefore it raises the impedance. I have
found quite interesting the method used to take the 3.3V to the VCCO
pins but I wonder whether a trace (instead of a plane is not a
problem. Shouldn't a power plane be below or above all the pins of
the FPGA as it happens with ground planes?

Thanks for the tip. I took out a few vias and enlarged the 2.5V
planelet. It is fairly solid now. Unfortunately the clearance around
the via is the minimum allowed by the PCB maker (PCBTrain). The 3.3V
IO does not really have a plane, but has an 0402 cap between the ground
plane at each via. All of the IO are 3.3V LVCMOS. I am going to go
ahead and build it. It has to be better than the alternative (PQ208).

Darrell Harmon

 

[Symon]

"Symon" <symon_brewer@hotmail.com> wrote in message
news:42a9de59_3@x-privat.org...

"calaf" <calaf_calaf_calaf@yahoo-dot-es.no-spam.invalid> wrote in message
news:jYGdnT7auunXIDTfRVn_vg@giganews.com...

As far I can gather I find some issues: There are some disposition of
vias on the 2.5V planelet that reduce significatively the path's
width for currents (and therefore it raises the impedance.

The vias are plated through. With metal. Like Khan, you're thinking too
two
dimensionally. Think like Mr. Spock.

Doh, I was looking at the wrong bit. Shouldn't've gone drinking on a school

night yesterday!
Syms.