EDK : FSL macros defined by Xilinx are wrong

[John_H]

An example in Verilog:

always @(posedge Clk_36MHz)
begin // counting 0-24, inclusive
count <= count + (enable ? -5'd24 : +5'd1);
enable <= (count==5'd24);
out_clk <= enable | (count<5'd12);
if( enable )
begin
// do everything here at
// 1.44 MHz, no gated clock
end
end

A gated clock would be:

wire ClkGated = Clk36MHz | ~enable;
always @(posedge ClkGated)
begin
// do everything at 1.44 MHz with severe clock skew
end

Which - it appears you know - isn't a great way to go.


"Marco" <marcotoschi_no_spam@email.it> wrote in message
news:d6plfi$o79$1@news.ngi.it...
<snip>

What I could do?

<snip>

Since the ratio of 1.44 MHz / 50 MHz is 18/625, you could use one DCM in
frequency synthesis mode to get an 18/25 multiplier (36 MHz). Use that
for your internal clock WITH a clock-enable for the whole thing once
every 25 cycles. Also use that clock enable to drive an IOB register
high which you then deassert 12 or 13 36 MHz clocks later for 48%/52%
duty cycle.

Clean, workable.

<snip>

 

[ARRON]

Today i have tried to modify the parameters: CAS_LAT from 2 to 3,TREF from 64 to 32,and find this have nothing effect in the programm. Now i can assure the problem of reading or writing SDRAM has relation with the cpu. In the Powerpc, the operationt is all right,but in the Microblaze, the Wrong is inevitable, i need more advice, i need your help!

 

[Big Boy]

I tried with Synplify 8.10, and it does work correctly.

So, this is probably a limitation (or bug, call it what you want!)
with 7.7.1!

Thanks.

 

[John Larkin]

On Wed, 01 Jun 2005 00:44:02 -0400, Mike Monett <no@spam.com> wrote:

John Larkin wrote:

[...]

Suppose I have an AC power system, and I can digitize a pair of
voltage and current waveforms. I want to report everything: trms
volts/amps, true power, reactive power, phase angle. The line
frequency could vary from maybe 20 to 80 Hz for a stationary
generator, or 200-800 for an aircraft system (including startup and
weird situations.) I'll digitize to 16 bits, at maybe 20K
samples/second or something. I'm considering doing all the signal
processing in an FPGA, crunching maybe 8 voltage+current pairs.

For the rms volts/amps, we could just square the samples, filter, and
allow my pokey uP to occasionally pick up that and square root.

True power is just the product of the e*i samples, lowpass filtered.
Easy.

Isn't that Volt-Amperes? You need the phase angle to separate the
components into true power and reactive power.

VA would be the product of the RMS-averaged voltage and current
values, which throws away phase information. The average of the
instantaneous e/i sample pairs is true power, just as if you'd used an
analog multiplier to calculate power.

What's tricky is the reactive power/phase angle thing.

Can't you just detect the zero crossings in the voltage and current
waveforms and get the phase angle between them?

No, because I only have the digitized samples, and because the current
waveform has a huge dynamic range and might be very ugly. The voltage
waveform in a power system is usually pretty close to a clean sine.

John

 

[John Larkin]

On Wed, 01 Jun 2005 13:36:24 GMT, Fred Bloggs <nospam@nospam.com>
wrote:

Pathetically trivial when you use Parseval's Identity and various
elementary results relating multiplication in the time domain to
convolution in the frequency domain and take note that the frequency
domain representation is on an orthogonal basis...

Thanks, Fred, you're always so helpful.

John

 

Just multiply your angle by 2^N/360 and that's all.

I see!

John_H mention that earlier but i wasn't fully understood. I know what
I need to do now.

Thanks for your help

pvnguyen

 

[Ben Jones]

Hi Lina,

"Jon Beniston" <jon@beniston.com> wrote in message
news:1117616106.265895.110170@g43g2000cwa.googlegroups.com...

Get EDK 7.1, which has support for h/w floating point.

Just to clarify - this is almost but not quite true. If your code is running
on MicroBlaze, then the new EDK does indeed include support for a
floating-point unit in the FPGA fabric. If you are using the PowerPC (and
since you're using V2-Pro, I suspect you probably are), then it doesn't.

I can suggest a few options:

1) Use a Microblaze core with FPU, either for your whole application or to
accelerate those algorithms which use floating point arithmetic;
2) Get a PowerPC floating-point unit, for example:

http://www.qinetiq.co.uk/home_rtes/quixilica_products/firmware_cores/quixili
ca_fpu_ppc.html

3) Consider moving to Virtex-4 FX, which will soon have a PowerPC
floating-point unit available.

Hope this helps,

-Ben-

 

[Duane Clark]

dexue wrote:

ARRON wrote:

I have added the opb_spi core in my project,I can assure the opb_spi have been inserted in the project(because i can find the synthesise and implemention file of opb_spi).But i can't find any parameter about opb_spi in the xparameters.h,and can't the head file in the directory of PPC405_0/libsrc or PPC405_0/include, what is wrong?


Sometimes if you manually add ipcores to .mhs file, EDK does not put
parameters to xparameters.h file. You have to use the Add/EDit Core GUI
to add ipcore correctly.

I'll just add that what goes into the xparameters.h file is determined
by the file system.mss in the base of your project. This is a plain text
file with very simple parameters. You can always add an entry to it for
your spi core.

 

[John_H]

You're a good man, Philip. This information is what I needed. If only the
patent wasn't so hard to comprehend!

It'll take some time to understand what *would* happen with two (nearly)
independent clocks where the only restriction is that the rising edges
aren't "close" but the information is there.

Thanks again.

"Philip Freidin" <philip@fliptronics.com> wrote in message
news:5c6r91hng8p8frdpv4194lqj1ml4rr2b5u@4ax.com...

On Tue, 31 May 2005 17:52:07 GMT, "John_H" <johnhandwork@mail.com> wrote:
There's been a little side discussion about the Xilinx IOB cell DDR
output
registers. The common idea of a DDR output register is A) the use of two
registers clocked off different phases of the same clock with a mux
controlled by the clock so the register just updated goes out.

It was my recollection from dicussions here that B) the DDR output
register
didn't have a physical mux but was effectively a two-clock register.

Is it A or B ?

or C, something with an XOR (nope)

or D, something else:

The Virtex-II DDR flops are described in patent 6777980
and is available at:

www.FreePatentsOnline.com

or

http://www.uspto.gov/patft/index.html


The architecture is more a pair of transparent latches, and a
mux-ish structure that does not really have an equivalent in
normal logic.


Philip


Philip Freidin
Fliptronics

 

[Joey]

Hi Lina

I was also experiencing the same problems. Infact the computation was taking
such a long time. At the end what we did was rewrite the whole program with
very less computations. For example use "register" variables/keywords ,
compute commonly used variables before hand and so on and at the end we got
a satisfactory computational speed.
One more hint: Put the instructions in the ISOCM memory and dont use any
Instruction side cache memory !! The results which I got were more than 10
times better
Joe

"lina" <lnzhao@emails.bjut.edu.cn> schrieb im Newsbeitrag
news:ee8e9cb.-1@webx.sUN8CHnE...

Hi all, I am doing some programmes with EDK 6.3i on the Virtex-II Pro50.
There are many math computing in the program, and I do them using the

software libs provided by the board, as a result, it is very very slow that
we could not endure. So I would like to know the effective and simple method
to speed up the float computing. Please help me. Thank you very much.

 

[Joey]

You can just make use of pointers and thats easy enough, isn't it?

"Marco" <marcotoschi_no_spam@email.it> schrieb im Newsbeitrag
news:d7kfc5$fup$1@news.ngi.it...

"John Williams" <jwilliams@itee.uq.edu.au> wrote in message
news:newscache$w5ndhi$t3a$1@lbox.itee.uq.edu.au...
Hi Marco,

Marco wrote:
Which C function should I use to perform read or write into block ram
(connected to opb bus with opb bus controller)?

Xio_in8 and Xio_out8 ?

Not necessary - just read and write it like normal memory.

Regards,

John


Could you explain, please?

Normally, when I write a C program, I create variables... and everything
is
stored in memory, but it is implicit.

So, what sohuld I do to read or write into memory? In what way may I
save,
in example a matrix into block ram?

Thanks
Marco

 

I's hard to say what's wrong, you may try these:

1) Test it with different brands/sizes HDDs
2) If I remember corectly, you may need to use the WriteDMAExt. (48 bit
addressing)
3) A Maxtor HDD spec. also help
4) It sounds like the address was truncated/ or wrapped around

 

[Marco]

"Joey" <johnsons@kaiserslautern.de> wrote in message
news:d7kpmg$m53$2@news.uni-kl.de...

You can just make use of pointers and thats easy enough, isn't it?

"Marco" <marcotoschi_no_spam@email.it> schrieb im Newsbeitrag
news:d7kfc5$fup$1@news.ngi.it...
"John Williams" <jwilliams@itee.uq.edu.au> wrote in message
news:newscache$w5ndhi$t3a$1@lbox.itee.uq.edu.au...
Hi Marco,

Marco wrote:
Which C function should I use to perform read or write into block
ram
(connected to opb bus with opb bus controller)?

Xio_in8 and Xio_out8 ?

Not necessary - just read and write it like normal memory.

Regards,

John


Could you explain, please?

Normally, when I write a C program, I create variables... and everything
is
stored in memory, but it is implicit.

So, what sohuld I do to read or write into memory? In what way may I
save,
in example a matrix into block ram?

Thanks
Marco

I can use C pointers to point to address space mapped from microblaze?

 

[Jon Beniston]

For example use "register" variables/keywords ,
compute commonly used variables before hand and so on and at the end we got
a satisfactory computational speed.

With GCC there should be no need for this. Was you compiling with
optimisation switched on (-O2)?

Cheers,
Jon

 

Kishore,

Usual i test the FPGA by writing test program such as LED test...If you
have an LED on board which is connect to FPGA why not use a counter and
switch on and off the LED.

Praveen

 

[Benjamin J. Stassart]

The xparameters.h, other include files, and libraries are based on the
driver selected for that peripheral.

In XPS, select Project->Software Platform Settings (or double click on the
processor in the System tab) and assign a driver to the opb_spi. You can
select between none, spi, and generic. I would recommend selecting spi.

As Duane Clark pointed out you can also manually add the spi driver to your
[project name].mss file.

There is no problem with manually adding IPs to the .mhs file, but if you
want to use their driver one must also add it to the .mss file.

Tip: One can assign the default drivers to all the IP in the system by
selecting Project->Assign Default Drivers.

"ARRON" <mlpei279@gmail.com> wrote in message
news:ee8e9e2.-1@webx.sUN8CHnE...

I have added the opb_spi core in my project,I can assure the opb_spi have
been inserted in the project(because i can find the synthesise and

implemention file of opb_spi).But i can't find any parameter about opb_spi
in the xparameters.h,and can't the head file in the directory of
PPC405_0/libsrc or PPC405_0/include, what is wrong?

 

[ARRON]

hello,everyone.I always build my project and compile it in EDK,but now i want to compile my project in gcc,who can tell me the process of compile the project step by step, thanks a lot!!!!

 

For more information on the Incremental Compilation feature in Quartus
II 5.0, refer this chapter in the Quartus II handbook -
http://www.altera.com/literature/hb/qts/qts_qii51015.pdf

Seshan
seshans@altera.com

 

[Krzysztof Szczepanski]

Just prepare any projects which deal with the issues and run an
implementation flow.
Then Xilinx software give you the answer.

krzysztof

Użytkownik "Yttrium" <Yttrium@pandora.be> napisał w wiadomości
news:Qz2ne.106661$k57.6462564@phobos.telenet-ops.be...

Hey,

I have to start a V4 design and am looking through a datasheet and i was
wondering if you can connect a regional clk to a DCM (if in a nearby
regional clk domain)? or even through logic?

kind regards,

Y

 

[ARRON]

Adding opb_spi through ADD/EDIT CORE is correct, and the opb_spi has drivers in the MSS file,which is 1.00.b, i am confused for this problem.