EDK : FSL macros defined by Xilinx are wrong

[Simon Peacock]

I think that's because one of the standards counts transistors in its MTBF..
so a PAL is more reliable than an FPGA but less reliable than an HC00.

Simon

"Peter Alfke" <peter@xilinx.com> wrote in message
news:3F6B9895.CB08B483@xilinx.com...

I think the answer is " more than 100 million, but less than 300 million".

We are caught between embarrassment: "that's how many we need" and
pride: "that's how good we are, to be able to make and sell that many
for a reasonable price".

An then there still are some people who really and seriously (!) think
they can calculate device reliability and MTBF from the total number of
transistors. These guys do not seem to die out, even though we have told
them, and proven to them, again and again, that such calculations are
utter nonsense.

So Ray is right, you would need another seven or eight fingers...
Peter Alfke
========================
Ray Andraka wrote:

More than you can count on both hands and feet, even if you count in
binary


Arnaldo Oliveira wrote:

Hi!

Could someone tell me how many transistors are integrated on the
XC3S5000
Spartan-3 device?
Thank You.
Arnaldo.

--

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[MNQ]

Hi Srikanth

Have you thought about using CPLDs? Xilinx offer the coolrunner II kits
for around $49. I have bought one for my own development purposes and it
seems to be fairly straight forward in use and has many I/Os.

Naveed



"Srikanth Anumalla" <srikanth@unlserve.unl.edu> wrote in message
news:SJ0ab.27397$NM1.21271@newsread2.news.atl.earthlink.net...

Jesse Kempa wrote:

I'm not sure what your cost requirements are, but for getting off the
ground one recently released development platform comes to mind....
check out Omniwerks (www.omniwerks.com), who offers a complete 802.11
FPGA/Embedded CPU development kit, with board/software/IP. They use
the Nios CPU & uc/OS II operating system on the software side.

Jesse Kempa
Altera Corp.
jkempa at altera dot com




The reason I went for fpga was to have wireless networking (802.11)
Actually, the sensors are 3-4 miles apart, I need the data until a
base station from where I will transfer the data to the internet.
the base station is located in the filed and will be 1-2 miles distant
from each sensor. So how do I transfer (in realtime) the data until the
base station from the sensor. Is it possible with PCI micro.
Please suggest me if there is a better solution other than fpga cpu
for doing this (wireless networking).

Thanks in advance
Srikanth

I know development kits costs are high. Suppose If I want to have 10
such embedded system, do I need to have 10 development kits, I am very
new to this, so please ignore my nonsence if any.

Srikanth

 

[Antti Lukats]

antti@case2000.com (Antti Lukats) wrote in message news:<80a3aea5.0309230458.3934bcc3@posting.google.com>...

do_not_reply_to_this_addr@yahoo.com (Sumit Gupta) wrote in message news:<ae680d56.0309230000.265514b4@posting.google.com>...
I have added a keyboard controller to my soc implementation.

http://www.c-nit.net

download of cpu.v and soc.zip are bad links http: 404 not found
please fix

antti
if you copy the url to those files and fix the \ to / manually then

all the files are downloadable

antti

 

[rickman]

Did my answer help you? I understand what you are tying to do, but your
description still is not clear enough to tell me exactly what you want
for an output.

Can you define exactly the state of the two signals at this point? Will
one always be low going high or will it vary?


James Williams wrote:

This is to detect the negotiation phase of the IEEE 1284 parrallel port.

I will use the output to disable the current active communications mode, and
begin a negation phase to determine and set a new mode of operation. I must
detect the changes of both of these signals because they are also used for
compatibility mode and EPP mode tranfer opperations, but they don't
transistion at the same time when in commucations mode. The transition of
these two signals at near the same time only occurs at the negotiation
phase.

Regards,

James.

"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F707610.FD7BBB09@yahoo.com...
James Williams wrote:

Hello,

I am just learning how to program using VHDL language. I am trying to
figure out how I can generate a device which detects when two signals
change
state at the same time. Below is a timing diagram. It must be able to
detect whether both signals changed state in the same time.

A: -------|_____________

B:________|-------------
^--- I need to detect this state change.

What is the best approach for this and how would it look in VHDL?

How do you define "at the same time"? This would imply that there is an
instant in which the transition is made. In reality the transition
takes an amount of time, during which the voltage that represents the
logic state goes from one valid range, through the invalid range to the
other valid range. So there is a grey area in both time and voltage
where you don't actually know if the signal is a 1 or a 0.

If you can work though that issue, the logic required would need a
memory (FF) to know the past state of the signals. If you see that
either signal has changed state, but the XOR of the two signals has not
changed state, then you know that both inputs have changed state.

So the next question is, exactly what do you need as an output? This is
not a typical circuit needed in a typical design. So exactly how it
will be implemented will depend on just what you are looking for as an
output (how you plan to use it).

This also sounds like a homework problem. I expect the assignment is
not to design a circuit since any circuit for this will be full of
hazards. More likely this is to make you think about the problems in
such a circuit.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Christian Schneider]

Well, you can either put an area constraint on an module (search for
AREA_GROUP in the manual), or you can put LOC constraints on either
primitives or modules. So I am afraid you have to put the process into
an own module.

Chris

Matthias Müller wrote:

Hello,
I'm working on a project with XC2V2000 and ISE4.2.
Does anyone know, if there is a location constraint to locate a SINGLE
PROCESS on a certain quadrant or slice-range?
Thank you,
Matthias

 

[Sumit Gupta]

antti@case2000.com (Antti Lukats) wrote in message news:<80a3aea5.0309230458.3934bcc3@posting.google.com>...

do_not_reply_to_this_addr@yahoo.com (Sumit Gupta) wrote in message news:<ae680d56.0309230000.265514b4@posting.google.com>...
I have added a keyboard controller to my soc implementation.

http://www.c-nit.net

download of cpu.v and soc.zip are bad links http: 404 not found
please fix

antti

Fixed !

Thanks
Sumit

 

[Jon Elson]

James Williams wrote:

Hello,

Is it possible to get the IEEE 1284 parrallel core for the ISE Webpack? I
am just a hobbiest and can't afford to pay thousands for the for release of
the ISE. I just want to be have to use the 1284 parrallel interface on my
device.




This is a slave device? Do you need the full-scale 1284 protocol for device

recognition, or just the handshaking part of it? I have built a set of
devices that
control CNC machine axes using the 1284 handshaking (read encoder position,
compute new velocity, send velocity to DAC or step pulse rate generator).

I get a transfer rate of about 800 nS per byte. I put an address
counter in the
device, so consecutive registers can be loaded (or read) without sending
a new address.

I found the most useful info on the protocol in the data sheets for the SMC
37C665 series of chips. Note that the chips in motherboards do NOT follow
the Microsoft document on signal timing. SMC chips send the strobes at
the same time as the data. UMC chips send the strobes BEFORE the data!
(The standard shows the strobes being delayed by an unstated amount.)

The hardware to control this is trivial. It fits on one small page of
schematics,
and can be implemented in small CPLDs, as well as FPGAs.

Jon

 

[SneakerNet]

"Antti Lukats" <antti@case2000.com> wrote in message
news:80a3aea5.0309222237.7c93ed9a@posting.google.com...

"SneakerNet" <nospam@nospam.org> wrote in message
news:<fIObb.156268$JA5.3828849@news.xtra.co.nz>...
Hi All

Has anyone successfully implemented USB 2.0 or USB 1.1 protocol in
Altera
Device. If yes, can you pls start me off. I'm not able to make any
progress
in this. I have found couple of sites in ths area, but always end
towards a
brick wall.

if you dont say what your problem is how could one help?
the USB cores available are working out of box for Xilinx, for altera
you need to change the technology dependant portions and it should
again work.

antti

Hi Antti
Thanks for the response. I actually contacted you regarding USB page that
you mentioned in this newsgroup a while back (Japanese language).
Ok firstly regarding USB implementation, the way I see it, there are 3 major
parts, which are:
1. USB Transceiver (to connect the FPGA and the PC)
2. FPGA Implementation
3. Windows App

Now
1. USB Transceiver - I have found out that the Philips PDIUSBP11A is quite
suitable for this job. However if you look at this pdf (which shows the
circuit connection) www.semiconductors.philips.com/acrobat/
applicationnotes/AN10007-01.pdf , on page 5 of this pdf there are 2 circuit
diagrams. I'm not able to understand the difference between upstream and
downstream circuits. Pls help/advice.
2. FPGA Implementation - Antti, you replyed saying (for altera you need to
change the technology dependant portions and it should again work.). What do
you mean by this? Help Again. Where can I download the USB cores to begin
with? Once I can get hold of the USB core, I guess I'll have a starting
point.
3. Windows Implementation - I have no clue with regards to windows drivers.
Any help in this matter would be very greatful.

Thanks guys

 

[Neil Franklin]

jetmarc@hotmail.com (jetmarc) writes:

a VHDL or Verilog implementation of an FPGA?

I know that somebody started one about 2 years ago, but I can't find
the bookmark anymore. The main problem was that the custom FPGA
needs a custom toolchain, and that makes it a really huge project.

That would have been the:

MPGA - Meta Programmable Gate Array
http://ce.et.tudelft.nl/~reinoud/mpga/README.html


--
Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Blacksmith
- hardware runs the world, software controls the hardware
code generates the software, have you coded today?

 

[Peter Alfke]

No comment...
Peter Alfke

 

[Vinh Pham]

Is there anything in the physics that encourages this?

It doesn't involve physics and in fact it is pretty straight forward, but
it's hard to understand without a visual diagram to help. I couldn't find
anything useful on the Web, and no textbook comes to mind. Dr. Howard
Johnson recommends this book:

"I think John Wakerly covers a lot of good points about metastability in his
book Digital Design Principles and Practices, Prentice-Hall, 1990 (ISBN
0-13-212838-1). He has a nice "ball and hill" description that I find very
helpful."

You could do it yourself by drawing a diagram of two flip-flops. Connect a
wire from FF#1's Q output to a cloud which represents a variable amount of
delay. Then hook that cloud to FF#2's D input. Both flip-flops are
connected to the same clock (you can assume there's zero clock skew). Now
start drawing (or simulating) waveforms, varying the delay and clock
frequency, to see what conditions cause a setup-time violation and hold-time
violation.

Two things that you should discover is:

1) A setup-time violation can be fixed either by reducing the delay or
increasing the clock period.

2) A hold-time violation can ONLY be fixed by ADDING delay.

If designers had to worry about both setup and hold time, we'd have to worry
about minimizing logic delay (so we can meet our performance goals) BUT
having enough logic delay (so we don't violate hold-time). Even if EDA
tools warned us when we have hold-time violations, what a waste of time
having to go back to fix your logic. It's better to prevent the violations
by having zero-hold time. That way instead of worrying about two things
during logic design, I only have to worry about one thing, minimizing logic
levels/delay.

You can have zero hold-time by making sure you have a large enough
clock-to-Q delay, or by adding delay in front of the FF's D input. The
problem with the first solution is the IO flip-flop of your chip might take
an input from an external register which has clock-to-Q you can't guarantee
without taking time to check. Once again, we want to minimize the things we
have to worry about, so it's better to add delay to the D input of a
flip-flop.

When you have zero hold-time, what you're doing is increasing your
setup-time, thereby reducing the maximum clock rate your chip can run at.
So your sacrificing some performance for ease of design. As a designer I
rather have ease of design and peace of mind.

Well I hope that was helpful, and more importantly I hope that it's correct.
I had to give it my best guess because zero hold-time is one of those things
everyone does and uses, but most dont' know why.


Regards,
Vinh Pham

 

[Vinh Pham]

The logical thing to do would be to combine this with the previous
thread, implement a XC6216 on top of a Virtex-II, use the XC6200 tools
that still exist, and satisfy those folks who can no longer get the
XC6200 for research purposes...

Heh, someone should implement an Altera architecture on a Virtex :_D

(not poking fun at the idea of a meta FPGA, of course)


Regards,
Vinh Pham

 

[John Williams]

Brian Drummond wrote:

On 22 Sep 2003 12:15:59 -0700, jetmarc@hotmail.com (jetmarc) wrote:


a VHDL or Verilog implementation of an FPGA?

I know that somebody started one about 2 years ago, but I can't find
the bookmark anymore. The main problem was that the custom FPGA
needs a custom toolchain, and that makes it a really huge project.

Marc


The logical thing to do would be to combine this with the previous
thread, implement a XC6216 on top of a Virtex-II, use the XC6200 tools
that still exist, and satisfy those folks who can no longer get the
XC6200 for research purposes...

That's a great idea...

John

 

[rickman]

SneakerNet wrote:

"Antti Lukats" <antti@case2000.com> wrote in message
news:80a3aea5.0309222237.7c93ed9a@posting.google.com...
"SneakerNet" <nospam@nospam.org> wrote in message
news:<fIObb.156268$JA5.3828849@news.xtra.co.nz>...
Hi All

Has anyone successfully implemented USB 2.0 or USB 1.1 protocol in
Altera
Device. If yes, can you pls start me off. I'm not able to make any
progress
in this. I have found couple of sites in ths area, but always end
towards a
brick wall.

if you dont say what your problem is how could one help?
the USB cores available are working out of box for Xilinx, for altera
you need to change the technology dependant portions and it should
again work.

antti

Hi Antti
Thanks for the response. I actually contacted you regarding USB page that
you mentioned in this newsgroup a while back (Japanese language).
Ok firstly regarding USB implementation, the way I see it, there are 3 major
parts, which are:
1. USB Transceiver (to connect the FPGA and the PC)
2. FPGA Implementation
3. Windows App

Now
1. USB Transceiver - I have found out that the Philips PDIUSBP11A is quite
suitable for this job. However if you look at this pdf (which shows the
circuit connection) www.semiconductors.philips.com/acrobat/
applicationnotes/AN10007-01.pdf , on page 5 of this pdf there are 2 circuit
diagrams. I'm not able to understand the difference between upstream and
downstream circuits. Pls help/advice.

I have not looked at the circuits, but upstream is closer to the PC and
so is a "host" type connection while downstream is closer to (or is) the
peripheral. I think there are only very small differences having to do
with initialization protocol.

2. FPGA Implementation - Antti, you replyed saying (for altera you need to
change the technology dependant portions and it should again work.). What do
you mean by this? Help Again. Where can I download the USB cores to begin
with? Once I can get hold of the USB core, I guess I'll have a starting
point.

I think he was saying that he is aware of IP that works in the Xilinx
chips and so would work in any other FPGA. But the coding style may
have used chip specific features (like the 16 bit SRL in the Xilinx
parts). If so, this code may need to be changed to something more
generic for an Altera part. Any Xilinx features that are instantiated
will need to be replaced for sure.

Check www.opencores.org. They have USB 1.1 and 2.0 implementations
available. I don't know if they are vendor specific or not.

3. Windows Implementation - I have no clue with regards to windows drivers.
Any help in this matter would be very greatful.

This depends on your application. I believe there is a generic set of
drivers to support a "human interface device" or similar which means it
works like a mouse or keyboard in terms of sending data in small
packets.

Again, I am not directly experienced with this, but I have been
listening intently when others discuss this here and elsewhere.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Antti Lukats]

Peter Alfke <peter@xilinx.com> wrote in message news:<3F70E4F9.2A7A642D@xilinx.com>...

No comment...
Peter Alfke

Hi Peter,

this is something, I mean if someone (like you) doesnt hold it back
to say 'no comments' it means something, need to figure out what

FYI

MPGA Meta Gate array

pure Xilinx SRL16 oriented design,

1 MPGA cell = 1 Virtex slice
bitstream is prepared as ASCII chart that can be directly downloaded!
yes you have ASCII chart you edit it and download to FPGA

KRPAN (OC embedded FPGA)

this is very similar to Algotronix CAL1024 with little bit enhanced
interconnect and cell architecture

1 KRPAN cell is approx 26 Virtex slices

KRPAN comes with verilog to bitstream tool that does map place and route
(simulated annealing), it also has some Floorplanner, software is written
100% in Java and does work.

both the cell sized indicated for fpga-fpga include bitstream programmin
interface.

antti@openchip.org

I wonder if your comment is still no comment?
guess it is.
me smiling here

 

[Antti Lukats]

"James Williams" <james@williams-eng.com> wrote in message news:<bkpq2c$d4aa$1@news3.infoave.net>...

Hello,

Is it possible to get the IEEE 1284 parrallel core for the ISE Webpack? I
am just a hobbiest and can't afford to pay thousands for the for release of
the ISE. I just want to be have to use the 1284 parrallel interface on my
device.

what you mean you cant afford ISE (full release) there is no difference
if you use ISE or ISE Webpack in this case.

a full IEEE1284 peripheral core is available from japanese site
it did show the windows parallel port enumaration screen i.e. the
parallel port device is recognized as plug and play and displays
manufacturer info.

unfortunatly I cant find the link any more
it wasnt of interest for me so I forgot.

but for simple handshaking its not hard to hand-craft it from scratch

antti

 

[Antti Lukats]

"James Williams" <james@williams-eng.com> wrote in message news:<bkpq2c$d4aa$1@news3.infoave.net>...

Hello,

Is it possible to get the IEEE 1284 parrallel core for the ISE Webpack? I
am just a hobbiest and can't afford to pay thousands for the for release of
the ISE. I just want to be have to use the 1284 parrallel interface on my
device.

http://www.nahitech.com/nahitafu/fpgavhdl/index.html

there are 2 links to IEEE1284 vhdl for xilinx
found it

google: IEEE1284 FPGA


antti

 

[Glen Herrmannsfeldt]

"Vinh Pham" <vinh-pham@hawaii.rr.com> wrote in message
news:QC5cb.1055$Ak3.463@twister.socal.rr.com...

Is there anything in the physics that encourages this?

It doesn't involve physics and in fact it is pretty straight forward, but
it's hard to understand without a visual diagram to help. I couldn't find
anything useful on the Web, and no textbook comes to mind. Dr. Howard
Johnson recommends this book:

"I think John Wakerly covers a lot of good points about metastability in
his
book Digital Design Principles and Practices, Prentice-Hall, 1990 (ISBN
0-13-212838-1). He has a nice "ball and hill" description that I find very
helpful."

You could do it yourself by drawing a diagram of two flip-flops. Connect
a
wire from FF#1's Q output to a cloud which represents a variable amount of
delay. Then hook that cloud to FF#2's D input. Both flip-flops are
connected to the same clock (you can assume there's zero clock skew). Now
start drawing (or simulating) waveforms, varying the delay and clock
frequency, to see what conditions cause a setup-time violation and
hold-time
violation.

It was more obvious to me connecting Qbar to D of the same FF. Then there
is no question about clock skew.

Two things that you should discover is:

1) A setup-time violation can be fixed either by reducing the delay or
increasing the clock period.

2) A hold-time violation can ONLY be fixed by ADDING delay.

If designers had to worry about both setup and hold time, we'd have to
worry
about minimizing logic delay (so we can meet our performance goals) BUT
having enough logic delay (so we don't violate hold-time). Even if EDA
tools warned us when we have hold-time violations, what a waste of time
having to go back to fix your logic. It's better to prevent the
violations
by having zero-hold time. That way instead of worrying about two things
during logic design, I only have to worry about one thing, minimizing
logic
levels/delay.

But if there is clock skew, then even zero hold time isn't good enough. You
can't make it too easy.

You can have zero hold-time by making sure you have a large enough
clock-to-Q delay, or by adding delay in front of the FF's D input. The
problem with the first solution is the IO flip-flop of your chip might
take
an input from an external register which has clock-to-Q you can't
guarantee
without taking time to check. Once again, we want to minimize the things
we
have to worry about, so it's better to add delay to the D input of a
flip-flop.

When you have zero hold-time, what you're doing is increasing your
setup-time, thereby reducing the maximum clock rate your chip can run at.
So your sacrificing some performance for ease of design. As a designer I
rather have ease of design and peace of mind.

Not so long ago I was reading about the design of pipelined computers. In
most cases there should be enough logic never to have to worry about hold
time, but in some cases FF's are wired with no logic in between. Then you
might need to add some to be sure. There is also a design for a combination
latch and two level of logic. That helps in allowing faster clocks for the
amount of logic per pipeline stage.

Well I hope that was helpful, and more importantly I hope that it's
correct.
I had to give it my best guess because zero hold-time is one of those
things
everyone does and uses, but most dont' know why.

-- glen

 

[Antti Lukats]

"SneakerNet" <nospam@nospam.org> wrote in message news:<p43cb.157047

Has anyone successfully implemented USB 2.0 or USB 1.1 protocol in
[deleted]

USB11T11A FS/LS USB tranceiver

usb_phy (opencores) UTMI interface that connects to USB11T11A

usb1.1 (opencores) connects to usb_phy (opencores) connects to
USB11T1A it is not HID but it will enumerate in hardware iw the USB
host will 'see' it, but ther is no host software provide

usb (japanase desing) full HID USB core includes USB11T1A model) can
directly be connected to usb D+ D- pins! (no tranceiver chip), there
is some VB test program to talk to the core (as it is HID peripheral)

antti
PS I am afraid you have todo some homework cant do it for you

 

[ykagarwal]

Not so long ago I was reading about the design of pipelined computers. In
most cases there should be enough logic never to have to worry about hold
time, but in some cases FF's are wired with no logic in between. Then you
might need to add some to be sure. There is also a design for a combination
latch and two level of logic. That helps in allowing faster clocks for the
amount of logic per pipeline stage.

Please excuse me if i go somewhat out of the topic
this seems somewhat relating to wave pipeline
concept used in asics .. just want to know can present fpgas can make
use of this kind of
pipeline concept ? people have tried this doing manually as google
tells me.
or the future fpgas plus routing softwares are going to do this stuff
automatically.

--yka