EDK : FSL macros defined by Xilinx are wrong

[Chen Wei Tseng]

Allan,

For your point 2, it's already implemented in ISE6.1i with the
<project>.cmd_log file.

Again, thanks for the suggestions. And it's best for you to open a case
with the Xilinx support for the feature enhancement requests to make
sure we capture the requests with a actual case.

Regards, Wei
Xilinx Applications

Allan Herriman wrote:

On Wed, 24 Sep 2003 14:05:29 -0600, Chen Wei Tseng
chenwei.tseng@xilinx.com> wrote:


Hi Marc,

Xilinx do welcome user inputs on improving the tools. You're more than
welcomed to let me know or open hotline cases for change requests on
Xilinx software tools. We all benefits from specific constructive
suggestions!

Best Regards, Wei
Xilinx Applications


Ok, here are my suggestions for today.

1. Allow multiple installations of (different versions of) Xilinx
software on the same machine. Drop the use of the XILINX environment
variable - it's a PITA.

2. Add a "save project as script" command to the project manager.
This allows a user to use the GUI to set up their project options,
then save a shell script or batch file and then never use the GUI
again.

Regards,
Allan

 

[James Williams]

What part of it can be commented out. Does the PC care that it is a plug
and play connection?

Will it fit on a CPLD 95xxx?

Regards,

James


"Antti Lukats" <antti@case2000.com> wrote in message
news:80a3aea5.0309242225.6c35065f@posting.google.com...

Jon Elson <jmelson@artsci.wustl.edu> wrote in message
news:<3F7208C4.3050506@artsci.wustl.edu>...
James Williams wrote:

Is there one with the IEEE 1284 Core VHDL that is in english?


I poked around a while and found the VHD file, which seems readable.
I haven't tried to UNDERSTAND it yet, however - that is different.


http://www.nahitech.com/nahitafu/fpgavhdl/ieee1284_2/ieee1284main-ver01.vhd

good, come alone and you all will learn japanese as god as I

I dont understand nothing in japanese.
And this is how I read japanese HDL/FPGA pages:
1 check pictures
2 check all hyperlinks, even if page is japanese the línks may have
english page names
3 download all HDL files and all archive files, check whats inside

the link what you found seems to be full IEEE1284 peripheral core with
plug and play support (there is screenshot of the plug and play
enumeration
so I assume it is working and verified on FPGA)

the design does synthesise out of box for
Xilinx XST 256 Slices
or 60% of XC95 144
for Actel APA075 its 25%

the design is larger than commercial IEEE1284 cores, but it has
plug and play enumaration built in (what you can easily comment out if
needed)

antti

 

[James Williams]

I found that it did synthesise into an XC95144, however is does not fit into
the device use the fitter of the ISE.

Regards,


James

"Antti Lukats" <antti@case2000.com> wrote in message
news:80a3aea5.0309242225.6c35065f@posting.google.com...

Jon Elson <jmelson@artsci.wustl.edu> wrote in message
news:<3F7208C4.3050506@artsci.wustl.edu>...
James Williams wrote:

Is there one with the IEEE 1284 Core VHDL that is in english?


I poked around a while and found the VHD file, which seems readable.
I haven't tried to UNDERSTAND it yet, however - that is different.


http://www.nahitech.com/nahitafu/fpgavhdl/ieee1284_2/ieee1284main-ver01.vhd

good, come alone and you all will learn japanese as god as I

I dont understand nothing in japanese.
And this is how I read japanese HDL/FPGA pages:
1 check pictures
2 check all hyperlinks, even if page is japanese the línks may have
english page names
3 download all HDL files and all archive files, check whats inside

the link what you found seems to be full IEEE1284 peripheral core with
plug and play support (there is screenshot of the plug and play
enumeration
so I assume it is working and verified on FPGA)

the design does synthesise out of box for
Xilinx XST 256 Slices
or 60% of XC95 144
for Actel APA075 its 25%

the design is larger than commercial IEEE1284 cores, but it has
plug and play enumaration built in (what you can easily comment out if
needed)

antti

 

[Lorenzo Lutti]

"Peter Alfke" <peter@xilinx.com> ha scritto nel messaggio
news:3F6F1A16.EC328D4F@xilinx.com...

Lorenzo, you must be pretty smart if you can solve the
"worst nightmare
ever invented" in a mere ten minutes...

Touche`.

--
Lorenzo

 

[Amontec Team, Laurent Gau]

James Williams wrote:

What part of it can be commented out. Does the PC care that it is a plug
and play connection?

Will it fit on a CPLD 95xxx?

Regards,

James


"Antti Lukats" <antti@case2000.com> wrote in message
news:80a3aea5.0309242225.6c35065f@posting.google.com...

Jon Elson <jmelson@artsci.wustl.edu> wrote in message

news:<3F7208C4.3050506@artsci.wustl.edu>...

James Williams wrote:


Is there one with the IEEE 1284 Core VHDL that is in english?



I poked around a while and found the VHD file, which seems readable.
I haven't tried to UNDERSTAND it yet, however - that is different.



http://www.nahitech.com/nahitafu/fpgavhdl/ieee1284_2/ieee1284main-ver01.vhd

good, come alone and you all will learn japanese as god as I

I dont understand nothing in japanese.
And this is how I read japanese HDL/FPGA pages:
1 check pictures
2 check all hyperlinks, even if page is japanese the línks may have
english page names
3 download all HDL files and all archive files, check whats inside

the link what you found seems to be full IEEE1284 peripheral core with
plug and play support (there is screenshot of the plug and play
enumeration
so I assume it is working and verified on FPGA)

the design does synthesise out of box for
Xilinx XST 256 Slices
or 60% of XC95 144
for Actel APA075 its 25%

the design is larger than commercial IEEE1284 cores, but it has
plug and play enumaration built in (what you can easily comment out if
needed)

antti



look out our Chameleon POD based Parallel port.

We have designed on it 1284 EPP controller, it works fine, and is fully
tested in your ' OCDemon Raven JTAG ' configuration.
Our EPP controller core is very small and can be mapped on a 64
Flip-Flops device (ex: Xilinx Coolrunner XCR3064XL or other CPLD)

Contact me if you want pur EPP controller core, I can give you the VHDL
source if you need.

Laurent
Amontec Team
www.amontec.com
_____________________________________
We provide new low cost solutions for FPGA Download and Processor Debug
(parallel port and USB support)

------------ And now a word from our sponsor ----------------------
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[Vinh Pham]

thank you for your explanation ; now i will have no more regret to use
all those registers !

Heh yeah, registers are "free." If your design can handle the register
delays, use them as often as you can, it'll make your routing easier. I
throw in registers without thinking about it. I'm sure if I ever work for
an ASIC company, I'll have to unlearn that habit.

Also the LUTs can be used as 1-bit wide shift registers that can be 1-16
"registers" deep. They're called SRL16s. Very handy for adding delay to
signals to make them line up with other signals, clock cycle wise.


Regards,
Vinh

 

[Antti Lukats]

"James Williams" <james@williams-eng.com> wrote in message news:<bkv30s$pp0$1@news3.infoave.net>...

I found that it did synthesise into an XC95144, however is does not fit into
the device use the fitter of the ISE.

Regards,

with plug and play and debug disabled it fits into XC9572 with ISE

antti

 

[James Williams]

What parts are the plug and play?

Why is there a separate IEEE1284_IN and out port? Couldn't that be the same
8bit bidirectional port?

Also,

I asked if I could get the EPP VHDL that you mentioned, but I had to change
my email address because of the current virus going around was swamping my
incoming messages. My new email is jlw@williams-eng.com

Regards,


James

"Antti Lukats" <antti@case2000.com> wrote in message
news:80a3aea5.0309252122.75ef10c2@posting.google.com...

"James Williams" <james@williams-eng.com> wrote in message
news:<bkv30s$pp0$1@news3.infoave.net>...
I found that it did synthesise into an XC95144, however is does not fit
into
the device use the fitter of the ISE.

Regards,

with plug and play and debug disabled it fits into XC9572 with ISE

antti

 

[Chris Ebeling]

Mikhail,

I see your point!

The following code will address the problem
tested against F.31i

library ieee;
use ieee.std_logic_1164.all;

entity ff_test is
port (clk, sync_reset, clk_ena : in std_logic;
outf : inout std_logic
);
end entity ;


architecture test of ff_test is
signal din : std_logic := '1' ;
attribute keep : boolean ;
attribute keep of din : signal is true ;

begin
process(clk)
begin
if (clk'event and clk = '1') then
if sync_reset='1' then
outf <= '0';
elsif clk_ena='1' then
outf <= din ;
else
outf <= outf ;
end if;
end if;
end process;

end architecture test ;

MM wrote:

Hi all,

I want the code below to synthesize as a FF with a sync reset and CE,
however XST does something quite different (target technology is Virtex II).
It routes my clk_ena signal to the REV pin and ties D and CE to VCC. The
sync_reset is recognized OK and gets routed correctly to the SR pin. I
realize that if I had a "regular" input signal instead of '1' under the
clock enable statement it would have worked fine, but what should I do if I
need to tie it to VCC?

process(clk)
begin
if rising_edge (clk) then
if sync_reset='1' then
outf <= '0';
elsif clk_ena='1' then
outf <= '1';
end if;
end if;
end process;

Thanks,
/Mikhail

 

[Paul Leventis]

Hi Sebastian,

Prof. Steve Wilton's group at the University of British Columbia is doing
work on a Programmable Sytem-on-a-Chip. They generate HDL for an arbitrary
sized FPGA core, and implement it in Standard Cells on a ASIC. The tool
also spits out a compiler for the core (p & r + bitstream generator). They
published a paper at CICC on it, and have some other publications.

Take a peak at http://www.ece.ubc.ca/~stevew/soc.html.

Regards,

Paul Leventis
Altera Corp.

"Sebastian Lange" <Sebastian_Lange@gmx.de> wrote in message
news:6877ff81.0309220526.2f5b7d3e@posting.google.com...

This post may seem a bit awkward, but has anyone ever come across a
VHDL or
Verilog implementation of an FPGA? It would be very instructional to
have a
look at it. IMHO, it should be at any rate possible to implement a
small FPGA as a bit file sitting on top of another FPGA. Our group is
currently working on some ideas for minimizing the reconfiguration
data in dynamically reconfigurable FPGA applications.
It would be very kind if anyone could point me to any resources...
Thank you so much in advance...

Sebastian

 

[Joe Chisolm]

SneakerNet wrote:

Hi Ken

Thanks for the important tip. I'll give that a shot. (so there is no way u
can send me driver? all i need is a driver with vendor id = 0c91 and
product id = 2001).
Anyway like u mentioned, very big pity that the guys didn't include
drivers and they gave their whole vhdl code free. Pity!

Hope god has mercy on my soul while i'm doing usb driver.. LOL
Thanks Ken
Kind Regards
[snip]

You might look for a book by the title (I think) "UBS made easy" or
something like that. My copy must be packed away. It had a lot of
info on Windows drivers and included several VB examples on the CD.
If I can find the book I'll post the ISBN but I remember I got it
from Amazon.

--
Joe Chisolm - Arizona

 

[Vinh Pham]

Coregen lets me use the same name for a component I've modified. It just
asks if I'm sure I want to overwrite my old files.

But I use Coregen manually (i.e. I invoke it myself instead of using Project
Manager). Are you using Project Manager? If so perhaps by default it
prevents you from overwriting an old component file because it doesn't know
if another project is using that same file but expecting the old bus width,
for example.

That's just a wild guess. Good luck.


Regards,
Vinh

 

[marlboro]

Just about the circle: <BR>
Another approach for circle drawing is using trignometry. <p>The inputs for circle drawing macro are of course the circle Center(X0,Y0), Radius R, and the real time scanning index (x,y), assume active pixel matrix is 512x512. <p>First we need to check if vertical index is within the drawn circle by compare |y-Y0| &lt;= R, if yes then scale |y-Y0| to radius R. Let say <BR>
yy = |y-Y0|/R. For this we may use LUT for 1/R, L1(R) = 1/R. <p> yy = |y-Y0| * L1(R) (1) <p>Notes that yy = sin(teta), teta is an angle in first quadrant, <BR>
0&lt;= yy &lt;= 1 <p>Known sin(teta) one can find cos(teta) by another LUT, let say <p> L2(yy)=xx, where xx=cos(teta) <BR>
or <BR>
&amp;nbsp;L2(|y-Y0| * L1(R)) = xx (2) <p>Notes: sin^2(teta) + cos^2(teta)=1 <p>Perform multiplying to find out <BR>
|x-X0| = R*xx <p>or <p>|x-X0| = R*L2(|y-Y0| * L1(R)) (3) <p>solve for x from (3) : <p>x = X0 +- R*L2(|y-Y0| * L1(R)) (4) <p>From equation (4), one can see x is a function of X0, Y0, R, and y. Note that (4) can be computed during horizontal blank time (take several clock cycles), register results, and perform another calculation... <BR>
That means for a pair of LUTs L1, L2, it can draw more than one circle. <p><p><p><p><p><p><p><p><p>use LUT to figure out |x-X0|, where LUT imply function F(S) = C where S=sin(teta) and C = cos(teta) in the first quadrant. <p><p><p><p>We can use RAM LUT for this function <BR>
F(S)= C, where S=sin(theta) and C=cos(theta) in the first quadrant circle. The inputs to this circle macro function are of course the Center(X0,Y0) and Radius R.

 

[marlboro]

Just about circle: <BR>
Another approach for circle drawing is using trignometry. <p>The inputs for circle drawing macro are of course the circle Center(X0,Y0), Radius R, and the real time scanning index (x,y), assume active pixel matrix is 512x512. <p>First we need to check if vertical index is within the drawn circle by compare |y-Y0| &lt;= R, if yes then scale |y-Y0| to radius R. Let say <BR>
yy = |y-Y0|/R. For this we may use LUT for 1/R, L1(R) = 1/R. <p>yy = |y-Y0| * L1(R) (1) <p>Notes that yy = sin(teta), teta is an angle in first quadrant, <BR>
0&lt;= yy &lt;= 1 <p>Known sin(teta) one can find cos(teta) by another LUT, let say <p>L2(yy)=xx, where xx=cos(teta) <BR>
or <BR>
&amp;nbsp;L2(|y-Y0| * L1(R)) = xx (2) <p>Notes: sin^2(teta) + cos^2(teta)=1 <p>Perform multiplying to find out <BR>
|x-X0| = R*xx <p>or <p>|x-X0| = R*L2(|y-Y0| * L1(R)) (3) <p>solve for x from (3) : <p>x = X0 +- R*L2(|y-Y0| * L1(R)) (4) <p>From equation (4), one can see x is a function of X0, Y0, R, and y. Note that (4) can be computed during horizontal blank time (take several clock cycles), register results, and perform another calculation... <BR>
That means for a pair of LUTs L1, L2, it can draw more than one circle.

 

[Jon Elson]

Vinh Pham wrote:

The orignal question was: What algorithms can you use to generate live
video, that contains only line art (lines, rectangles, curves, circles,
etc.), if you can't use a frame buffer.

The benefit of using a frame buffer is flexibility. Namely you get random
access to any pixel on the screen. This opens up a wide range of algorithms
you can use to play the performance-area-complexity tradeoff game.

Without a frame buffer, you only have sequential access to your pixels. No
going back, no going forward. Quite Zen I suppose. Anyways, you lose access
to a lot of frame buffer algorithms, but some can still be used.



I guess you are talking about raster-scan displays without a pixel to pixel

frame buffer behind it, and not about vector-drawing displays (like an
oscilloscope in X-Y mode).

Interesting theoretical enterprise, but I really don't see the point. I
remember quite
some years ago talking to a guy who had invested millions of $ in developing
software for Evans&amp;Sutherland color vector displays for the drug design
industry. I just casually threw out the comment that in 5 years the E&amp;S
gear
would be in the dumpster, and everybody would have switched to pixel/raster
scan systems. They were doing stuff with up to 100,000 simulated spheres
on the screen, and he essentially told me I was so nuts that he couldn't
even
begin to explain how impossible it would be for a frame buffer to ever
handle
such a task. Well, of course, all that is history now, and his company
had to
invest a BUNDLE in converting all their software to adapt to the frame
buffer mode of doing things.

Jon

 

[Vinh Pham]

Lot's of good stuff. I'll have to read it later tonight. I just wanted
to

Don't worry about it, there's nothing profound in it, I just carried away
when I start writing :_)

modify one assumption you made. Resolution. I'll be working at 4K x 2.5K
and maybe as high as 4K x 4K and 60 frames per second soon. My current
work
is at 2K x 1.5K, 60 fps though.

Jeeze that's quite a bit of bandwidth there.

http://www.ecinemasys.com/products/display/edp100/pdf/edp100_preliminary.pdf

Cool way to expand the use of a Cinema Display. I bet HD sized CRTs are
awfully heavy and delicate. So with your product someone could view live HD
footage from inside a small helecoptor, for instance? Looks like it'll
change the way people think of and us HD displays. Pretty cool to make a
product that can affect the way people do their work.

The design is 100% mine, electrical, board layout, mechanical, FPGA,
firmware, GUI, etc.

Must be fun having a hand in every aspect of a product, it's your baby.
Like the olden days of hand crafted cars, before Ford turned it into an
assembly line.

Some of the highlights: Two 1.485GHz inputs, two 1.485GHz outputs,
165MHz
DVI output, USB, lots of interesting real-time processing going on.

Is PCB layout particulary challenging? Heh everything probably is when
you're processing that much data. Doesn't seem like it needs much
ventilation, so heat's not much of a problem?

:&gt; Yes, it has a frame buffer (four frames actually). No, it shouldn't be
used

to render graphics primitives.

But...but...;_)

 

[Vinh Pham]

Interesting theoretical enterprise, but I really don't see the point.

Someone just had a rare situation where they couldn't use a frame buffer.
You can think of it as an intellectual exercise :_)

I remember quite some years ago talking to a guy who had invested millions
of $ in developing

Hahaha no wonder he refused to believe you. Sort of like when you buy a
crappy product, but you make yourself believe it's great, because of all the
money you spent on it.

Did E&amp;S's vector display draw only outlines of spheres, or shaded? Shading
with x-y vectors doesn't sound too fun.

What do you think was the main reason why people switched to pixel/raster?
Simplicity? Scales better?

Thanks for the interesting anecdote Jon

 

[Martin Euredjian]

"Jon Elson" &lt;jmelson@artsci.wustl.edu&gt; wrote:

I guess you are talking about raster-scan displays without a pixel to
pixel
frame buffer behind it, and not about vector-drawing displays (like an
oscilloscope in X-Y mode).

Interesting theoretical enterprise, but I really don't see the point.

And you wouldn't outside of a contextual reference frame that allowed you to
understand where/why this might be important. It's a very narrow field of
application. Not mainstream at all.


--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"

 

[Martin Euredjian]

"Jan" wrote:

Looked at the spec's of the EDP100. Looking very nice indeed.. So to
convert
the HDSDI into DVI you would need a deďnterlacer and a frame rate
converter.

....

If you don't mind, I'd like
to know how many fieldstores are actually used in the deinterlacer.

I can't get into the internals at that level as some things must remain
proprietary. I'm sure you understand.

The de-interlacer uses some conventional algorithms and a couple of
not-so-standard techniques. Keep in mind, this is a monitoring device, and,
as such, it tries very hard to not modify the incoming HD stream too much.
Some de-interlacing techniques produce great looking pictures that are
highly synthetic. That's OK if you are building a deinterlacer for a system
that will then have to process the image further or for something like home
TV. Probably no OK for professional use. At least that's my approach.
Seems to work.

I'm just curious since I'm roughly in the
same business.

Can you elaborate? Privately would be OK, of course.

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"

 

[Kening]

Mario Trams wrote:

Isaac wrote:

Hi Isaac,


I am trying to read 36 signal one by one from FPGA using different
addresses and these signal are of 3 bits length. My address bus is
bidirectional (32 bit length)and it's on tristate while not performing
read operations.
I am using PCI API fucntion to perform open , read and write
operations as it is PCI FPGA reconfigurable board having XCV600
device. The values are being read by using SRAM in the board and I am
using addresses which are properly mapped to PCI bus and Onboard
Memory. Now the problem is that I delebrately make a loop to read the
sequence of signal again and again in order to make sure I am reading
the correct output every time. But the thing is that in different
iteration the values of different signal are not the same. it means
that the signal which is being read is changing all the time. But
according to simulated desing this is not the case , I must have been
reading the correct output everytime .
Is there is any design constraint ? My desing has internal clock as
well is this is affecting the signal. But in simulation this is not
the case .


Your problem is almost impossible to be solved from remote.
You say that it is working well in simulation. Do you mean
functional simulation (i.e. pure VHDL code) or back-annotated
simulation (i.e. simulation of the synthesized design including
estimated delays etc.)?

Are you also sure that you meet all timing parameters when
accessing the RAM?


Also one thing more does the VHDL coding style effect the read from
FPGA or not. Because in my other desing I have state machine and
number of different states in the Process (desing is synchronous) and
I am using CASE statement to move from one state to another. When I
download this into the chip and when I perform read operation after
writing data into the chip I am getting nothing from FPG.
If any one can tell me how to stabilize particular signal so that it
could to read oout from FPGA.


Absolutely! VHDL coding style might have heavy impact on the result.
To give an example effect I once encountered with Synopsys:
When you have a clocked process with asynchronous reset and a couple
of registers inside, and you forget to include one signal in the
reset clause, then Synopsys created a register where the output
is feed back and is ORed at the input. As a result, once the
register turns to '1', it can never turn to '0' again.
But in functional simulation you do not see that effect (exept from
the fact that the register is not initialized during reset).

That's another reason why it is important to simulate the
synthesized design.

Regards,
Mario