EDK : FSL macros defined by Xilinx are wrong

[Peter Alfke]

Antti Lukats wrote:

Hi Peter,

this is something, I mean if someone (like you) doesnt hold it back
to say 'no comments' it means something, need to figure out what

It just meant that I had read Neil's wide-ranging posting and found it

meaningless to answer, because that would just lead to further
outbursts. The subjects he brought up have been discussed in this
newsgroup ad nauseam...
Peter

 

[Marc Randolph]

Peter Alfke <peter@xilinx.com> wrote in message news:<3F6F1A16.EC328D4F@xilinx.com>...

Lorenzo Lutti wrote:


Yes! But be afraid of iMPACT user interface, which is the worst
nightmare ever invented. I've lost more than ten minutes to understand
how to use a PROM with iMPACT...

Lorenzo, you must be pretty smart if you can solve the "worst nightmare
ever invented" in a mere ten minutes...
Peter Alfke

Howdy Peter,

I interpreted his comment to mean that he wasted ten minutes on
just one aspect of the many that form the nightmare that is iMPACT.
And I have to agree with him. The tool sure works like it was
designed by someone that doesn't actually have to use it more than
once or twice. The rest of the Project Navigator (at least on 5.x),
while noticably better than iMPACT, is also very disappointing coming
from a company that produces such high caliber hardware.

Have fun,

Marc

 

[James Williams]

Is there one with the IEEE 1284 Core VHDL that is in english?

Regards,

James
"Antti Lukats" <antti@case2000.com> wrote in message
news:80a3aea5.0309232339.5e68de5f@posting.google.com...

"James Williams" <james@williams-eng.com> wrote in message
news:<bkpq2c$d4aa$1@news3.infoave.net>...
Hello,

Is it possible to get the IEEE 1284 parrallel core for the ISE Webpack?
I
am just a hobbiest and can't afford to pay thousands for the for release
of
the ISE. I just want to be have to use the 1284 parrallel interface on
my
device.

http://www.nahitech.com/nahitafu/fpgavhdl/index.html

there are 2 links to IEEE1284 vhdl for xilinx
found it

google: IEEE1284 FPGA


antti

 

[Vinh Pham]

It was more obvious to me connecting Qbar to D of the same FF. Then there
is no question about clock skew.

That's a good idea too. Whatever works for you.

But if there is clock skew, then even zero hold time isn't good enough.
You
can't make it too easy.

I was simplifying the example for the sake of making things easier to
understand. But you are correct that during real design you need to take
clock skew into account. That is one reason why FPGA vendors make great
efforts to provide a low skew clock network. I'm sure FPGA software also
takes clock skew into account when analyzing a design.

Not so long ago I was reading about the design of pipelined computers.
In
most cases there should be enough logic never to have to worry about hold
time, but in some cases FF's are wired with no logic in between. Then you
might need to add some to be sure.

Yeah I agree with you that there's usually enough logic so you wouldn't have
to worry. And with FPGAs a significant amount of delay comes from the
routing.

One advantage of having zero hold-time parts is that you can port a proven
design to a faster speed grade without having to worry about a hold-time
violation.

There is also a design for a combination
latch and two level of logic. That helps in allowing faster clocks for
the
amount of logic per pipeline stage.

Do you happen to have a URL to that example? It sounds interesting.


--Vinh

 

[Glen Herrmannsfeldt]

"Vinh Pham" <vinh-pham@hawaii.rr.com> wrote in message
news:tUkcb.1068$5z.548@twister.socal.rr.com...

It was more obvious to me connecting Qbar to D of the same FF. Then
there
is no question about clock skew.

That's a good idea too. Whatever works for you.

But if there is clock skew, then even zero hold time isn't
good enough. You can't make it too easy.

I was simplifying the example for the sake of making things easier to
understand. But you are correct that during real design you need to take
clock skew into account. That is one reason why FPGA vendors make great
efforts to provide a low skew clock network. I'm sure FPGA software also
takes clock skew into account when analyzing a design.

Not so long ago I was reading about the design of pipelined computers.
In most cases there should be enough logic never to have to
worry about hold time, but in some cases FF's are wired with no logic
in between. Then you might need to add some to be sure.

Yeah I agree with you that there's usually enough logic so you wouldn't
have
to worry. And with FPGAs a significant amount of delay comes from the
routing.

One advantage of having zero hold-time parts is that you can port a proven
design to a faster speed grade without having to worry about a hold-time
violation.

I think this is what Peter was trying to point out somewhere along the line.

There is also a design for a combination latch and two level of logic.
That helps in allowing faster clocks for the
amount of logic per pipeline stage.

Do you happen to have a URL to that example? It sounds interesting.

It is called the "Earle latch", which seems to find 38 hits on Google.

I have no idea if it is at all useful today. Consider that it was in the
days when individual transistors were glued onto ceramic chips, with
metalized wiring on them. The 360/91 was built with pretty much a discrete
version of ECL.

The book I have is called "The Architecture of Pipelined Computers" by Peter
M. Kogge. Copyright 1981, so you might consider it more of a history book.
Still, many ideas from that time are still in use today.

-- glen

 

[Chen Wei Tseng]

Hi Marc,

Xilinx do welcome user inputs on improving the tools. You're more than
welcomed to let me know or open hotline cases for change requests on
Xilinx software tools. We all benefits from specific constructive
suggestions!

Best Regards, Wei
Xilinx Applications

Marc Randolph wrote:

Peter Alfke <peter@xilinx.com> wrote in message news:<3F6F1A16.EC328D4F@xilinx.com>...

Lorenzo Lutti wrote:


Yes! But be afraid of iMPACT user interface, which is the worst
nightmare ever invented. I've lost more than ten minutes to understand
how to use a PROM with iMPACT...

Lorenzo, you must be pretty smart if you can solve the "worst nightmare
ever invented" in a mere ten minutes...
Peter Alfke


Howdy Peter,

I interpreted his comment to mean that he wasted ten minutes on
just one aspect of the many that form the nightmare that is iMPACT.
And I have to agree with him. The tool sure works like it was
designed by someone that doesn't actually have to use it more than
once or twice. The rest of the Project Navigator (at least on 5.x),
while noticably better than iMPACT, is also very disappointing coming
from a company that produces such high caliber hardware.

Have fun,

Marc

 

[Vinh Pham]

Still, many ideas from that time are still in use today.

That is true. And sometimes people discover new uses for old techniques.
It never hurts to learn them, because they can give you ideas on how to
solve your current problems. Thanks for the information Glen. I found a
lot of links to Earle Latches but no diagrams. I guess the design is too
old for the internet.


--v

 

[Jon Elson]

James Williams wrote:

Is there one with the IEEE 1284 Core VHDL that is in english?


I poked around a while and found the VHD file, which seems readable.

I haven't tried to UNDERSTAND it yet, however - that is different.

http://www.nahitech.com/nahitafu/fpgavhdl/ieee1284_2/ieee1284main-ver01.vhd
<http://www.nahitech.com/nahitafu/fpgavhdl/ieee1284_2/ieee1284main-ver01.vhd%27>

Jon

 

[SneakerNet]

Hi Antti
Thanks for the response.
haha. I don't expect anyone to do work for me, othwersie I won't learn
anything, but I wouldn't mind some guidance along the way from you guys..
Anyway I need to ask 2 questions regarding your reply.
1. When you say USB11T11A, do you mean the Philips tranceiver PDIUSBP11A? If
no then I'm sorry but i'm not able to find anything on USB11T11A. Have I
gone blind?
2. Regarding the usb (japanese design), I have ended up towards a brick
wall. What I mean to say is, I have been looking at the design for couple of
hours and there are 4 components that I'm not sure what they do. The main
problem is that the code was written for a Xilinx component and because I'm
using Altera component, I'm do not have the librabires that these component
are using.
Firstly the library defined is (which is for Xilinx only (pls correct me if
i'm wrong))
library unisim;
use unisim.vcomponents.all;

and the 4 components that are using this library are
u_DLL : CLKDLL
port map ( CLKIN => CLKINM,
CLKFB => GCLK,
RST => RST,
CLK0 => GCLKM,
CLK2X => CLKM,
LOCKED => LOCK
);

u_GCLK : BUFG
port map ( I => GCLKM,
O => GCLK
);

u_CLK : BUFG
port map ( I => CLKM,
O => CLK
);

u_CLKIN : IBUFG
port map ( I => CLKIN,
O => CLKINM
);

If you can explain me how I can replace these components for Altera design,
I will have a step to progress. If I can get past this point, then I have
something to try on the chip and play around. My problem is that right now I
can't go past compiling as Quartus doesn't recognize these components (or
the library). Pls Advice

Thanks again

Regards


"Antti Lukats" <antti@case2000.com> wrote in message
news:80a3aea5.0309240119.7925b682@posting.google.com...

"SneakerNet" <nospam@nospam.org> wrote in message news:<p43cb.157047
Has anyone successfully implemented USB 2.0 or USB 1.1 protocol in
[deleted]

USB11T11A FS/LS USB tranceiver

usb_phy (opencores) UTMI interface that connects to USB11T11A

usb1.1 (opencores) connects to usb_phy (opencores) connects to
USB11T1A it is not HID but it will enumerate in hardware iw the USB
host will 'see' it, but ther is no host software provide

usb (japanase desing) full HID USB core includes USB11T1A model) can
directly be connected to usb D+ D- pins! (no tranceiver chip), there
is some VB test program to talk to the core (as it is HID peripheral)

antti
PS I am afraid you have todo some homework cant do it for you

 

[Glen Herrmannsfeldt]

"Vinh Pham" <a@a.a> wrote in message
news:r7ncb.1311$5z.1162@twister.socal.rr.com...

Still, many ideas from that time are still in use today.

That is true. And sometimes people discover new uses for old techniques.
It never hurts to learn them, because they can give you ideas on how to
solve your current problems. Thanks for the information Glen. I found a
lot of links to Earle Latches but no diagrams. I guess the design is too
old for the internet.

I wonder if I can get this to work:


Fixed width font required:

clock -------
| nand )------------\
data -------- \
| \
|----
| nand )---------------| nand ) -------------- out
out ----
| /
---- /
| nand )------------/
clockbar ----


Clock and its inverse, clockbar, apparently don't have so strict timing
requirements as one might guess.

To implement AND/OR logic, the number of inputs on the final nand can
be increased, and additional copies of the left middle nand can be
added, also with more inputs.

-- glen

 

Peter Alfke <peter@xilinx.com> wrote in message news:<3F6F9240.E1B74AB5@xilinx.com>...

Here are some practical points.
For all but the most extremely fast applications ( say up to 200 MHz),
synchronous counters are built using a global clock, and the bult-in
free ripple carry structure, which of course determines a max frequency
(where the ripple carry can still meet the set-up time requirements of
the MSB.) Decoding TC can be quite tricky, that's why I suggested the
digital differentiator which actually detects TC+1.

It is interesting to see this discussion come up, I had never thought
about doing a cout/TC (delayed) in this way!

To implement the "digital differentiator", the best I could come up with
was a falling edge detector on MSB using an AND gate, an inverter and a
flip-flop.

D gets the MSB and Q is ANDed with NOT(MSB). Depending on use, I guess
the AND output could be synchronized (delay of 2 clocks then) if needed.

Keeping this clever TC method in mind, I'm trying to build a
programmable frequency divider which uses a 20-bit loadable synchronous
counter. The divisor is held in a register and is arbitrary, so no
clever apriori optimizations. Currently I'm targetting a Flex6K but I'm
also eyeing a Xilinx Spartan XL part.

I found if I have a counter setup to count down and decode on count == 1
which drives a DFF and is used to SLOAD the counter, I need a large
number of LUTs to implement the decode/compare logic(not surprising).

To use the TC method above(counting-up), I need to load my counter with
the 1's complement of my divisor.

Is the only alternative to count-down (and lots of LUTs) or count-up/TC
(1's comp. of divisor) for my frequency generator to use a phase
accumulator arrangement? Did I miss any other clever tricks?

Thanks in advance.

-- Jay

 

[Allan Herriman]

On Wed, 24 Sep 2003 14:05:29 -0600, Chen Wei Tseng
<chenwei.tseng@xilinx.com> wrote:

Hi Marc,

Xilinx do welcome user inputs on improving the tools. You're more than
welcomed to let me know or open hotline cases for change requests on
Xilinx software tools. We all benefits from specific constructive
suggestions!

Best Regards, Wei
Xilinx Applications

Ok, here are my suggestions for today.

1. Allow multiple installations of (different versions of) Xilinx
software on the same machine. Drop the use of the XILINX environment
variable - it's a PITA.

2. Add a "save project as script" command to the project manager.
This allows a user to use the GUI to set up their project options,
then save a shell script or batch file and then never use the GUI
again.

Regards,
Allan

 

[Eric Smith]

Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> writes:

1. Allow multiple installations of (different versions of) Xilinx
software on the same machine. Drop the use of the XILINX environment
variable - it's a PITA.

Conflicting requirements. The XILINX environment variable is what
ALLOWS multiple installations. That's how the pieces of an installation
find the other related pieces, rather than some other version.

 

[rickman]

SneakerNet wrote:

Hi Antti
Thanks for the response.
haha. I don't expect anyone to do work for me, othwersie I won't learn
anything, but I wouldn't mind some guidance along the way from you guys..
Anyway I need to ask 2 questions regarding your reply.
1. When you say USB11T11A, do you mean the Philips tranceiver PDIUSBP11A? If
no then I'm sorry but i'm not able to find anything on USB11T11A. Have I
gone blind?
2. Regarding the usb (japanese design), I have ended up towards a brick
wall. What I mean to say is, I have been looking at the design for couple of
hours and there are 4 components that I'm not sure what they do. The main
problem is that the code was written for a Xilinx component and because I'm
using Altera component, I'm do not have the librabires that these component
are using.
Firstly the library defined is (which is for Xilinx only (pls correct me if
i'm wrong))
library unisim;
use unisim.vcomponents.all;

and the 4 components that are using this library are
u_DLL : CLKDLL
port map ( CLKIN => CLKINM,
CLKFB => GCLK,
RST => RST,
CLK0 => GCLKM,
CLK2X => CLKM,
LOCKED => LOCK
);

u_GCLK : BUFG
port map ( I => GCLKM,
O => GCLK
);

u_CLK : BUFG
port map ( I => CLKM,
O => CLK
);

u_CLKIN : IBUFG
port map ( I => CLKIN,
O => CLKINM
);

If you can explain me how I can replace these components for Altera design,
I will have a step to progress. If I can get past this point, then I have
something to try on the chip and play around. My problem is that right now I
can't go past compiling as Quartus doesn't recognize these components (or
the library). Pls Advice

This is something I know a bit more about. These are all clock
components. CLKDLL is a DLL (Delay Locked Loop) like a PLL only more
Xilinx like The Altera parts have PLLs depending on the part. I
don't know if this is required or just used to allow different external
and internal clock rates.

The BUFG and IBUFG are just clock buffers. They are used to drive the
internal clock distribution networks. Altera should have equivalent
components or you may not need to instantiate them since they are
typically locked to a given pin and should be inferred by most tools.
Read up a bit on the Xilinx and Altera chips and this will all be very
clear.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Allan Herriman]

On Thu, 25 Sep 2003 10:35:48 +1000, Allan Herriman
<allan.herriman.hates.spam@ctam.com.au.invalid> wrote:

On Wed, 24 Sep 2003 14:05:29 -0600, Chen Wei Tseng
chenwei.tseng@xilinx.com> wrote:

Hi Marc,

Xilinx do welcome user inputs on improving the tools. You're more than
welcomed to let me know or open hotline cases for change requests on
Xilinx software tools. We all benefits from specific constructive
suggestions!

Best Regards, Wei
Xilinx Applications

Ok, here are my suggestions for today.

1. Allow multiple installations of (different versions of) Xilinx
software on the same machine. Drop the use of the XILINX environment
variable - it's a PITA.

2. Add a "save project as script" command to the project manager.
This allows a user to use the GUI to set up their project options,
then save a shell script or batch file and then never use the GUI
again.

3. Add options to XST to allow defines, parameters and generics to be
set from the command line as well as from a project file.

Regards,
Allan.

 

[Allan Herriman]

On 24 Sep 2003 18:14:12 -0700, Eric Smith
<eric-no-spam-for-me@brouhaha.com> wrote:

Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> writes:
1. Allow multiple installations of (different versions of) Xilinx
software on the same machine. Drop the use of the XILINX environment
variable - it's a PITA.

Conflicting requirements. The XILINX environment variable is what
ALLOWS multiple installations. That's how the pieces of an installation
find the other related pieces, rather than some other version.

(Say) the value of XILINX is c:\xilinx42, which points to the ISE 4.2
installation.

Now run the 5.2 FPGA Editor
Start|Programs|Xilinx ISE 5|Accessories|FPGA Editor

It bombs 'cause it tries to use the wrong version of a library. It
doesn't have to bomb (since it can know where it is installed, and
doesn't need to look at an environment variable to find out), but
that's the way Xilinx wrote it.

The XILINX environment variable is what ALLOWS multiple installations.

Could you explain that (using my example) more fully please?

(BTW, I have used the XILINX variable in the past to select different
versions within scripts, so I know what you mean, but I still think it
needs to be improved.)

Regards,
Allan

 

[Antti Lukats]

Jon Elson <jmelson@artsci.wustl.edu> wrote in message news:<3F7208C4.3050506@artsci.wustl.edu>...

James Williams wrote:

Is there one with the IEEE 1284 Core VHDL that is in english?


I poked around a while and found the VHD file, which seems readable.
I haven't tried to UNDERSTAND it yet, however - that is different.

http://www.nahitech.com/nahitafu/fpgavhdl/ieee1284_2/ieee1284main-ver01.vhd

good, come alone and you all will learn japanese as god as I

I dont understand nothing in japanese.
And this is how I read japanese HDL/FPGA pages:
1 check pictures
2 check all hyperlinks, even if page is japanese the línks may have
english page names
3 download all HDL files and all archive files, check whats inside

the link what you found seems to be full IEEE1284 peripheral core with
plug and play support (there is screenshot of the plug and play
enumeration
so I assume it is working and verified on FPGA)

the design does synthesise out of box for
Xilinx XST 256 Slices
or 60% of XC95 144
for Actel APA075 its 25%

the design is larger than commercial IEEE1284 cores, but it has
plug and play enumaration built in (what you can easily comment out if
needed)

antti

 

[Julien Eyries]

Allan,

thank you for your explanation ; now i will have no more regret to use
all those registers !

Julien .

 

[Allan Herriman]

On Thu, 25 Sep 2003 15:55:52 +1000, Allan Herriman
<allan.herriman.hates.spam@ctam.com.au.invalid> wrote:

On 24 Sep 2003 18:14:12 -0700, Eric Smith
eric-no-spam-for-me@brouhaha.com> wrote:

Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> writes:
1. Allow multiple installations of (different versions of) Xilinx
software on the same machine. Drop the use of the XILINX environment
variable - it's a PITA.

Conflicting requirements. The XILINX environment variable is what
ALLOWS multiple installations. That's how the pieces of an installation
find the other related pieces, rather than some other version.

(Say) the value of XILINX is c:\xilinx42, which points to the ISE 4.2
installation.

Now run the 5.2 FPGA Editor
Start|Programs|Xilinx ISE 5|Accessories|FPGA Editor

It bombs 'cause it tries to use the wrong version of a library. It
doesn't have to bomb (since it can know where it is installed, and
doesn't need to look at an environment variable to find out), but
that's the way Xilinx wrote it.

The XILINX environment variable is what ALLOWS multiple installations.

Could you explain that (using my example) more fully please?

To make it more interesting, try to run both 4.2 and 5.2 fpga editors
at the same time (yes, I have wanted to do this), both run from the
start menu, without using
Start|Programs|Control Panel|System|Advanced|Environment Variables
to change the value of XILINX.

Well written software would do this without a hitch. The only reason
Xilinx software doesn't do it is because customers don't complain
enough. Well, I'm complaining.

Allan.

 

[rickman]

Eric Smith wrote:

Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> writes:
1. Allow multiple installations of (different versions of) Xilinx
software on the same machine. Drop the use of the XILINX environment
variable - it's a PITA.

Conflicting requirements. The XILINX environment variable is what
ALLOWS multiple installations. That's how the pieces of an installation
find the other related pieces, rather than some other version.

That may be the way it is implemented, but I believe Allan is asking
that they change the implementation. I know that I can have separate
versions of Netscape, Visio, MS Office and many other packages running
on the same machine. All I have to do is double click on the icon to
run them. No changes to environment variables or other system wide
changes.

Surely this could be done with CAD tools if the vendor really wanted to
make the change.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX