EDK : FSL macros defined by Xilinx are wrong

[Steven K. Knapp]

WebPack 6.1i, due out at the end of September, supports the Spartan-3
XC3S50, XC3S200, and XC3S400. The present version supports just the XC3S50.
http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=ISE+WebPack
---------------------------------
Steven K. Knapp
Xilinx Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3: Make it Your ASIC

"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F29C811.5B21458E@yahoo.com...

I thought this was discussed in a thread here, but I can't find it even
with Google Groups. Anyone have the skinny on what version will support
the XC3S400 and when that is likely to be out?

Hmmm... maybe I should search my email instead of here.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Neeraj Varma]

WinNT is not supported. Only XP or Win2K. We've tried it on NT, but it does
not work.


"Jim Wu" <jimwu88NOOOOSPAM@yahoo.com> wrote in message
news:QSdYa.15959$mZ6.13063@nwrdny02.gnilink.net...

I am currently using Xilinx Webpack 4.1 on a WinNT (SP6) machine and
thinking to upgrade to version 5.2. The web site does not say v5.2
supports
WinNT. I was wondering if anyone has tried the latest webpack on WinNT.

Thanks
Jim

 

[Hal Murray]

There isn't much FPGA related in here any more... I'm not sure
where this sort of thing gets discussed. I expect the low end
micro hackers are good at it.

What do you mean about "Be sure to fixup the broadcast case"?

see below

1. Is only the UDP protocol sufficient to be implemented in FPGA for
simple data transfers to the target (FPGA) from the PC? Do I need also
the ARP or other protocols?

Yes, you need to answer ARP requests. You can generally fake that
when getting started if you hard wire it into the ARP table on the
machine you are testing from.

You also need DHCP if you don't want to put your IP address into a
config file someplace.

2. Which protocols can I miss when the PC knows the 32-bit IP number
of the target? Is a 48-bit ethernet address required?

The hardware works on the 48 bit host ID. You could hack around that
if you have control of the other end too, but that is abusing Ethernet
rather than using it. (Which might be OK if you just need to do a
one off hack and don't want to talk to several machines.)

3. Suppose that all UDP packets will also be forwarded through the
router(s) to the target. Does it needs a special attention when only
the UDP is implemented? Will the routers change the IP header (and UDP
header) of the UDP packets before they are arrived at target?

The routers will update the hop count. Mostly, they won't touch
anything else. (except to fixup the checksum)

The trick with simple implementations for UDP over Ethernet is that
you don't have to know about routers. When you get a packet,
you send the answer back to where you got it. That happens at
both the Ethernet layer and at the IP layer. All the info you
need is in the headers.

4. Is the connection negotiation required between the PC and the
target? Do you think that the PC will always transfer some UDP packets
without restrictions?

The server side of simple UPD protocols doesn't need to save any info.
It gets a request packet, looks at a few command bytes (you have to invent
this layer of protocol), does what it says (say reads the temperature
and puts in into the packet) then fixes up the packet (say changes
the packet type from query to response) and sends it back.

The send-it-back part involves copying the source field from the packet
into the destination. That happens twice - Ethernet/48 bit layer and
also at the IP/32 bit layer. Then you put your info into the source
fields, fixup a few more header bytes, compute the IP checksum, and
send it off. Note that this doesn't know if it's sending back directly
or through a router.

Except for the broadcast, you could just swap the source/destination
fields.

The simple/stateless server moves all work of retransmissions and timers
back to the other end.

If you want to do something a bit more complicated, the next step
is probably TFTP/BOOTP. It's often used to fetch boot files
over the network. (for example, because you don't have a disk,
or you are installing new software)

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.

 

[Patrick MacGregor]

Take a look at Core Foundry. They specialize in making FPGAs a less
expensive solution compared to an ASIC or ASSP. That includes the licensing
and small quantities.

For example, they can stuff two independent OC48 performance monitors, and
do concatenated payload extraction, in the slowest speed grade 1C3 Cyclone
part. Qty = 1, that part costs about $17. A single channel ASSP might run
you $150 or more, times 2. Plus you use less board space and power.

I've talked to them about licensing and they can work in a variety of ways.
One of interest was spreading the license "fee" out over some quantity of
parts. This gets applied when parts are purchased, so there isn't any
up-front fee to burden an engineering budget. It gets tacked onto the BOM
like any other component on the board. The fee is qty dependent like any
other part, and expires after a predetermined total amount is paid. You can
even buy out the license with a lump sum if desired.

There seem to be as many ways to license IP as their are vendors.

Good luck.



"Ken Land" <kland1@neuralog1.com> wrote in message
news:vj2cblrm4st563@news.supernews.com...

Hi,

This is a high level question about IP Core business models.
I know about the "free" cores at opencores.org and I know you can pay
someone $15,000.00 to license a USB core.

What I'm looking for are companies that are in the middle whose pricing
competes with dedicated chips.

For example I need a USB 2.0 port on a project. I can call my NetChip
rep
and for $8-$15 (Qty. 30-50) a pop put a USB port in my design. Now for
annual quantities in the low 100's the IP Core's $15,000 startup fee is
out
of the question.

So my question is, are there any IP Core companies that compete with
NetChip
(or Cypress etc.) on pricing models?

Thanks,
Ken

 

[Jay]

Hi,

I do agree gate counting is a silly work especially when our ASIC group only
have function specifications and no RTL codes. They just can say their logic
may be ### NAND gates.
Unfortunately my boss don't think so, and I have to build whole proto board
even before the ASIC group can finish all codes.
Anyway, thanks for your kindly comment. It's very helpful to me.

Best Regards
Jay
"Andrew Paule" <lsboogy@qwest.net> ??????:3F3131B9.5050602@qwest.net...

Hi Peter:

I agree 100% (an RS is the most fundamental valid flop) - and for a D
type you do need two more gates.
I guess that the whole premis here is that there is some talk going
around trying to make an FPGA - ASIC conversion "standard", being able
to count the whatevers in an FPGA and relate that to whatever type of
gate the ASIC manufacturer is doing. Until there is an understnding of
the ASIC type being targeted, and the FPGA type being used to proto,
there cannot be any sort of gate counting relationship, but I don't want
to jerk the poor guys chain too hard. I think that he's been assigned
the task, and is trying to learn some fundamentals, albeit in the wrong
frame.

Andrew

Peter Alfke wrote:

Andrew Paule wrote:


snip>Let's say that this is a 2 input nand case - you need two of
these for a simple flop, and can build logic accordingly -



Wow, a flip-flop out of two 2-input NANDs ?
Yes, you can make them into a latch with independenr SET and RESET
(active Low), but you need 2 more gates to make it a D input, and you
double the whole thing to get from a latch to a flip-flop. And then
there is Clock Enable, and perhaps asynchronous CLEAR and/or PRESET,
plus perhaps Clock inversion.
You get all that in FPGA flip-flops "for free".

I agree gate count is silly in FPGAs, but let's not distort the argument
even further.
Peter Alfke, Xilinx

 

[Giuseppeł]

From the 5.0 version, ISE doesn't support Nt.
You have to upgrade to Win2000 or Xp if you want to upgrade.
Another way is to use Red Hat Linux and wine but I never tried it.
I hear that the new release 6.x, that will be available in the end of 2003,
support Linux native, but I'm not sure.

Regards
Giuseppe

"Jim Wu" <jimwu88NOOOOSPAM@yahoo.com> ha scritto nel messaggio
news:QSdYa.15959$mZ6.13063@nwrdny02.gnilink.net...

I am currently using Xilinx Webpack 4.1 on a WinNT (SP6) machine and
thinking to upgrade to version 5.2. The web site does not say v5.2
supports
WinNT. I was wondering if anyone has tried the latest webpack on WinNT.

Thanks
Jim

 

[Jim Wu]

Sorry, my mistake. I was thinking in a case where another branch exists to
set a = 1. e.g

if (a&b) a <= 0;
else if (c) a <= 1;

is certainly not the same as

if (b) a <= 0;
else if (c) a <= 1;

Anyway, synthesis tools are supposed to remove any redundant terms in
equations. As for the power saving, in CMOS, ideally there shouldn't be
additional power consumption if a doesn't change value.

Jim Wu
jimwu88NOOOOOSPAM@yahoo.com


Robert Finch <robfinch@sympatico.ca> wrote in message
news:ZvhYa.4853$pq5.746907@news20.bellglobal.com...

If you write down the truth table, you will see the two equations are
not
equivalent.

Ok,

line a b new a
-----------
1 0 0 a (old a)
2 0 1 a (old a)
3 1 0 a (old a)
4 1 1 0 (new value for a=0)

the only time 'a' changes is if both a and b are 1
however, looking at line 2, it is safe to convert the table to the
following:

a b new a
-----------
1 0 0 a (old a)
2 0 1 0 (new value for a=0) - no problem because old value already be zero
3 1 0 a (old a)
4 1 1 0 (new value for a=0)

 

[Peter Alfke]

Eric, what makes you think that 62 MHz I/O transfer is a problem?
You can easily go twice as fast...

Peter Alfke, Xilinx
=========================
Eric wrote:

Hello! I'm trying to move 125 MB/sec bidirectionally off a daughter
card, for a total of 250 MB/sec. I worry that even if I double the 8
bit bus in each direction to 16-bits (32 data pins todal) I'll still
be pushing a single-ended signal across a connector at 62.5 MHz. I
can't go wider because I run out of pins on my QFP.

I've started looking at LVDS, but it seems that xilinx has very little
information on how to actually _use_ lvds in a project. National has
some great app notes, but they're largely targeted at the national
family of SERDES products. Can anyone offer any suggestions for
high-speed multi-board data transfer between FPGAs? Has anyone ever
tried building a SerDes in a spartan-IIE, and if so, what kinds of
speeds have you been able to get?

Thanks for the help!
...Eric

 

[Jim Wu]

Given the assumption that there is at most one intersection, you can
actually combine the two vectors into an 1x50 vector and count which number
appears twice.

Jim Wu
jimwu88NOOOOSPAM@yahoo.com


"John_H" <johnhandwork@mail.com> wrote in message
news:4HuYa.21$OX.9443@news-west.eli.net...

Since you can describe it so easily, yes it can be implemented in
hardware.

The question left unanswered is how much speed do you want at the cost of
size?

If the vectors are loaded a byte at a time, the comparisons could be made
as
the vectors are loaded.
A broad-side identity compare of 20 values versus 30 values could be done
in
one clock but the number of compares are huge.

Stepping through each comparison - one per clock cycle - would take up to
600 clock cycles to achieve a match.

Does this homework have a desired outcome in area or speed?


"Zhen" <zhenxu2000@hotmail.com> wrote in message
news:7b390929.0308070736.128be22@posting.google.com...
I have a question:
There are two vectors, V1 and V2. V1 is a 1*20 vector and V2 is a 1*30
vector. V is the intersection of V1 and V2. We already have known that
V only can be either a null vector or a 1*1 vector(that is at most
there is one element in V1 and V2 is the same). for example:V1 =
[2,5,6,8,9,42,...], V2=[21,24,4,9,35...]then V=[9].
So the input is: V1 , V2,
output: V (0, if the intersection is null)
Can this function be implemented in hardware? Can it be implemented in
a chip? which chip can I use? what is the cost? what is the delay?
Thanks,

 

[Tom Kirsch]

Just a quick rule of thumb? About a 10:1 ratio of FPGAs to ASIC.

To get a better estimate, size the FPGA(s) based on how many flip-
flops, RAM, and I/O you need; forget about counting gates, that
gets ridiculous.


Jay wrote:

Hi all,

I'm doing prototyping for ASICs. Before I start my work, I have to estimate
the gates the FPGA or CPLD would use.
I know it's hard to get a precise result. I just want some common answer,
1:3 between ASIC and FPGA/CPLD gate count?(not consider the memory, just
logic)
Please tell me your experience.

Thanks,
Jay

 

[Jay]

Rob,

In article <3F2E0028.A07801D3@ob-wan.com>, judd@ob-wan.com says...

Add to that the need for an expensive IAR compiler for the AVR core and
it's pretty average. It's difficult to do a meaningful feature
comparison though, owing to the different architectures. I do know that
the EP1C6 and APA150 are very similar in price (when the config chip is
added into the equation). May check out the Atmel too, just to be sure
I'm not missing out on any bargains.

You have alternatives besides IAR.

The CodeVision compiler from http://www.hpinfotech.ro/ looks good, I
have associates who used it and didn't have anything unpleasant to say.
There is a version of the compiler that also supports the FPSLIC too. It
supports a number of optimizations and also includes pragmas so you can
optimize for speed or size.

There is also ImageCraft (www.imagecraft.com). I test drove the 30-day
eval and found it had functionality, but wasn't laid out (in my opinion)
as well as the above. Code produced looked OK I found CodeVision was
better in some instances, but I didn't spend too much time trying to
optimize for my test runs.

There is also AVR-GCC if you feel like dealing with GNU stuff...I have
*major* problems with this toolchain since(among other issues) it does
not support "dead code" removal which should rip out any pieces of
compiled code that aren't referenced in your program. I have a small set
of C routines that I use in many of my projects but often not all
functions in the "common set" C file are used. GCC won't remove those
(even if you mess around with the linker scripts).

Also, there aren't any pragmas for optimization (just your standard -o1
-o2 -o3 switches) which means you have to segment code into seperate
files to get it optimized the way you want (very sub-optimal).

GCC just wasn't meant for 8-bit micros, and I found plenty of fault with
the code it generates too.

Anyway, you have some alternatives.

-- Jay.

 

On Sat, 02 Aug 2003 02:12:02 +1000, Rob Judd <judd@ob-wan.com> wrote:

Nicholas,

No, manufacturability is the main concern. I don't have easy access to
high volume production machinery, which is almost guaranteed to be
necessary for most of the newer packages. If I can plug it in, great. If
not, I need to be able to hand-solder it with a standard Weller iron.

Rob

^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

if you are looking for plug in cabaliity as main criteria, then Rena
Electronics sell a board that is 15x15 PGA foot print with a
XC2S100-5VQFP onboard. get you 100k gates and nice prototyping plugin
capabilities.

You can also buy just the TQFP/VQFP to PGA adaptor board with no FPGA.

Also they will sell you an adaptor board and you send them the chip
and they will attach it.

This will not give you small physical size but ease from soldering
fine pitch QFP packages.

The only way I would attempt soldering BGA packages on a small scale
production is to use a hot plate and a lot of flux. Place the PCB,
should be FR4 min., on the hot plate at about 275C with BGA on board
aligned as close as possible. Use liquid flux and wait about 30
seconds. If the BGA is close to alignment, +/- half a ball width,
then it will align with the pads. Once it starts to float the remove
from the hot plate gently. Let cool and pray!

james

^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

Nicholas C. Weaver wrote:

In article <3F2A4153.66C411AD@ob-wan.com>, Rob Judd <judd@ob-wan.com> wrote:
Hi,

My application requires a lot of core but few physical i/o lines. Can
anyone suggest a modern fpga that is delivered in a 68-pin plcc and/or
80-pin pqfp package?

Is your concern board area? Hand soldering? Cost?

A small BGA package might be appropriate, as a .5mm spacing BGA for a
small pincount is really tiny, if the concerns are board area and
cost.
--
Nicholas C. Weaver nweaver@cs.berkeley.edu

 

[rickman]

"Steven K. Knapp" wrote:

"Rob Judd" <judd@ob-wan.com> wrote in message
news:3F2A4153.66C411AD@ob-wan.com...
Hi,

My application requires a lot of core but few physical i/o lines. Can
anyone suggest a modern fpga that is delivered in a 68-pin plcc and/or
80-pin pqfp package?

Thanks,

Rob

Sorry to act as a shill, but I believe the Xilinx Spartan-3 family provides
the largest amount of logic with the fewest number of I/O pins.

....snip...


Well, all the marketing "stuff" aside, I have been thinking about this
the last few days, and I think marketing teams are missing some
opportunities. I know that in some of my recent designs, I could have
used a small to medium FPGA instead of a CPLD if the FPGA were available
in a small package. And contrary to what FAEs may tell you in this
newsgroup, FPGAs with Flash is not a bad idea either.

If a 50K gate FPGA (1,536 logic cells in the XC3S for example) could be
put in a 48 pin TQFP, and include Flash on die, then that would be a
great product! I know that the chip designers would have a hard time
figuring out how to do this, but it would be a CPLD killer! I have
already replaced one of the larger CPLDs on my current board with an
FPGA. I have a second CPLD that could easily be replaced by an FPGA
with flash. Even if they had to go back to .25 micron process to get
the flash, would that be so bad? A decent FPGA could easily be built at
those densities that would kick CPLD butt.

Is Lattice the only company that thinks a decent sized FPGA with on die
flash is a good idea?

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Jim Granville]

rickman wrote:

"Steven K. Knapp" wrote:

"Rob Judd" <judd@ob-wan.com> wrote in message
news:3F2A4153.66C411AD@ob-wan.com...
Hi,

My application requires a lot of core but few physical i/o lines. Can
anyone suggest a modern fpga that is delivered in a 68-pin plcc and/or
80-pin pqfp package?

Thanks,

Rob

Sorry to act as a shill, but I believe the Xilinx Spartan-3 family provides
the largest amount of logic with the fewest number of I/O pins.

...snip...

Well, all the marketing "stuff" aside, I have been thinking about this
the last few days, and I think marketing teams are missing some
opportunities. I know that in some of my recent designs, I could have
used a small to medium FPGA instead of a CPLD if the FPGA were available
in a small package. And contrary to what FAEs may tell you in this
newsgroup, FPGAs with Flash is not a bad idea either.

If a 50K gate FPGA (1,536 logic cells in the XC3S for example) could be
put in a 48 pin TQFP, and include Flash on die, then that would be a
great product! I know that the chip designers would have a hard time
figuring out how to do this, but it would be a CPLD killer! I have
already replaced one of the larger CPLDs on my current board with an
FPGA. I have a second CPLD that could easily be replaced by an FPGA
with flash. Even if they had to go back to .25 micron process to get
the flash, would that be so bad? A decent FPGA could easily be built at
those densities that would kick CPLD butt.

Yes, and there is also a hole in the CPLD sector, around TQFP64.
CPLD started with PLCC68/PLCC84 pin devices, but never replaced them
with the move to SMD, so you have just 44/100 commonly.

Is Lattice the only company that thinks a decent sized FPGA with on die
flash is a good idea?

Look at the FLASH ProASIC from Actel, that's quite close to what you
describe. Comes in TQFP100 and FBGA144. Getting to TQFP48 is a bigger
ask, as the market would be thinning a lot - how many Vcc/Gnd/Core/JTAG
pins do
you loose ?

FBGA144 is not as nice to apply, but it is 13mm on an edge, so not much
larger than TQFP48.
No, you cannot deploy this on single sided PCB.
TQFP100 is 16mm / edge, and that is single sided possible.

Philips have pitched at this big core/small package (TQFP48) with their
first ARM uC variants.

-jg

 

[rickman]

Ken Jaramillo wrote:

I'm using Quartus II version 3.0 and am having trouble meeting setup
and hold timing. This is a large PCI design in the
Cyclone 12C device. The routing I'm getting is really bad so my
setup time violations are pretty bad. I can fix the setup times by
inserting 2 LCELL buffers on the PCI clock and placing the buffers
in such a way to get a lot of clock insertion (around 8 ns). If I synthesize the
design without hold time fixing enabled then I can get Tsu and Tco
to pass (just barely). I have the PCI logic back annotated (placement
not routing). If I then synthesize while enabling hold time fixing
Quartus fixes most of the hold time violations but breaks the setup
timing even though the PCI logic is back annotated. I think Quartus
must be pretty dumb as far as fixing hold timing. If the worst
case setup time is around 15 ns (8 ns clock insertion + 7 ns PCI setup
time requirement) then those worst case paths should have no problem
with hold times. If quartus just placed delays on the short paths
it could fix hold timing. But I suspect that it's placing the delays
around the pin and affecting both long and short paths.

Has anyone else seen this? Does anyone have any idea of how to fix hold
timing while not breaking the setup paths?

I think the best way to fix the setup and hold time problem is to fix
the routing. The best way to fix the routing is to fix the placement to
permit the routing to be good.

Even if you fix the timing by adjusting the relative clock delay, I
don't think buffers are the way to do it. The delay from a buffer can
vary over a wide range. So you may add a lot of delay max and very
little min. The min delay will help with the hold time, but the large
max delay will detract a lot more from the setup! Perhaps a DLL is what
you need?

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Mike Treseler]

Ken Jaramillo wrote:

I'm using Quartus II version 3.0 and am having trouble meeting setup
and hold timing.

A hold violation is very rare on any FPGA if the design is synchronous
and the dedicated clock distribution is used.


-- Mike Treseler

 

[Eric]

Eric wrote:

Hello! I'm trying to move 125 MB/sec bidirectionally off a daughter
card, for a total of 250 MB/sec. I worry that even if I double the 8
bit bus in each direction to 16-bits (32 data pins todal) I'll still
be pushing a single-ended signal across a connector at 62.5 MHz. I
can't go wider because I run out of pins on my QFP.

I've started looking at LVDS, but it seems that xilinx has very little
information on how to actually _use_ lvds in a project. National has
some great app notes, but they're largely targeted at the national
family of SERDES products. Can anyone offer any suggestions for
high-speed multi-board data transfer between FPGAs? Has anyone ever
tried building a SerDes in a spartan-IIE, and if so, what kinds of
speeds have you been able to get?

Thanks for the help!
...Eric
Peter Alfke <peter@xilinx.com> wrote in message news:<3F32788A.4DDCA931@xilinx.com>...
Eric, what makes you think that 62 MHz I/O transfer is a problem?
You can easily go twice as fast...

Peter Alfke, Xilinx
=========================

I'm too poor to buy an IBIS simulator I've been reading all sorts
of data sheets and app notes on LVDS that have made me worry about any
sort of single-ended signals one can reliably send over a short bus.
I read that PCI has really tight timings and is evidently really hard
to design for; it's only 33 MHz. Sure, it's a bus with multiple cards,
but AGP is a single card in a single slot, and only runs at 66 MHz. I
feared that if "real" EEs (instead of us biologists that just play
them when we need equiment that doesn't exist) don't want to push a
card interconnect above 66 Mhz, there must be a good reason.

So I'm trying to figure out what I can reasonably expect from a
4-layer FR4 board and a 68-pin high-density mini-D connector. This is
my first high-speed interconnect project, and it may just be paranoia.
Are you suggesting I shouldn't lose too much sleep over a ~125 MHz
single-ended bus covering a distance of 6" or so? or should I stick to
differential signaling for those types of speeds? I'd love to just
make my bus wider, but I run out of IOs on my Spartan-IIE PQFP and I
can't afford to have someone put down a BGA on a PCB.

Ahh, the joys of low-cost student design !

Thanks again for all the help,
...Eric

 

[Antti Lukats]

Is Lattice the only company that thinks a decent sized FPGA with on die
flash is a good idea?

actel ProAsic+
and upcoming ProAsic will have not only flash configuration but user
BlockFlash cells

antti

 

[dave garnett]

Read the bible - "High Speed Digital Design", by Johnson and Graham !

Dave

"Eric" <eric_usenet@yahoo.com> wrote in message news:bfab5081.0308072211.3143ae8f@posting.google.com...

Eric wrote:

Hello! I'm trying to move 125 MB/sec bidirectionally off a daughter
card, for a total of 250 MB/sec. I worry that even if I double the 8
bit bus in each direction to 16-bits (32 data pins todal) I'll still
be pushing a single-ended signal across a connector at 62.5 MHz. I
can't go wider because I run out of pins on my QFP.

I've started looking at LVDS, but it seems that xilinx has very little
information on how to actually _use_ lvds in a project. National has
some great app notes, but they're largely targeted at the national
family of SERDES products. Can anyone offer any suggestions for
high-speed multi-board data transfer between FPGAs? Has anyone ever
tried building a SerDes in a spartan-IIE, and if so, what kinds of
speeds have you been able to get?

Thanks for the help!
...Eric
Peter Alfke <peter@xilinx.com> wrote in message news:<3F32788A.4DDCA931@xilinx.com>...
Eric, what makes you think that 62 MHz I/O transfer is a problem?
You can easily go twice as fast...

Peter Alfke, Xilinx
=========================


I'm too poor to buy an IBIS simulator I've been reading all sorts
of data sheets and app notes on LVDS that have made me worry about any
sort of single-ended signals one can reliably send over a short bus.
I read that PCI has really tight timings and is evidently really hard
to design for; it's only 33 MHz. Sure, it's a bus with multiple cards,
but AGP is a single card in a single slot, and only runs at 66 MHz. I
feared that if "real" EEs (instead of us biologists that just play
them when we need equiment that doesn't exist) don't want to push a
card interconnect above 66 Mhz, there must be a good reason.

So I'm trying to figure out what I can reasonably expect from a
4-layer FR4 board and a 68-pin high-density mini-D connector. This is
my first high-speed interconnect project, and it may just be paranoia.
Are you suggesting I shouldn't lose too much sleep over a ~125 MHz
single-ended bus covering a distance of 6" or so? or should I stick to
differential signaling for those types of speeds? I'd love to just
make my bus wider, but I run out of IOs on my Spartan-IIE PQFP and I
can't afford to have someone put down a BGA on a PCB.

Ahh, the joys of low-cost student design !

Thanks again for all the help,
...Eric

 

[Manfred Kraus]

Every signal, that is used in a " if rising_edge " (also falling edge)
statement will be treated as if it was a clock signal. This means it gets a
clock buffer by default. To avoid this, use IBUFs for the signals, you dont
want to have BUFGs.
..
..
component IBUF
port(I: in STD_LOGIC; O: out STD_LOGIC);
end component;

begin

-- force the usage of IBUF for Rd and Wr signals
-- Without the IBUF, XST uses an BUFGP by default.

U1: IBUF port map (I => Rd_in, O => Rd);
U2: IBUF port map (I => Wr_in, O => Wr);
..
..
..

Hint: You can replace the generic "IBUF" by a variant that meets your I/O
Standard.


-Manfred Kraus

-mkraus
-at
-cesys
-dot
-com