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So clever people used the DDS to create a sine wave, then filtered the
sine wave with an analog filter, then used a comparator to slice it back
into the digital domain, with reduced jitter.
What sort of analog filter do I need for this approach?
Do I need a serious narrow band pass filter? Aka a crystal if
I want a real good one, which probably means I should just get
a packaged osc.
Or will a simple R/C low pass filter that cuts off at the target
frequency provide enough attenuation at the 3rd/5th harmonics
to make a low-jitter clock?
R/C filters are pretty cheap. You might need some ugly op-amps
and more Rs and Cs to get several poles. [But logic is cheap too,
especially if you already have an FPGA and board space is critical.]
But it is a tortuous detour, and faster multi-phase DDS
seems to be so much simpler...
That just reduced the jitter by a factor of "multi". Right?
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At what process size does the 3.3 volt compatibility go away?Anything is possible,
But you can't use 90nm for 5V. The minimum size you can use is .35u.
A combo 90 nm/ .35u process is not in the roadmap, so that makes life a bit
tough.
But then again, where is the $?
Peter and I are engineers, not marketeers, so we defer to the marketing folks
who seem to know just how large (small) the 5V market is....
Austin
Hi,
As a study for a project I need to investigate the possibility of
implementing a tiny TCP/IP stack and tiny MAC controller on FPGA. This
stack is capable to transfer some data packets directly into S(D)RAM
without help of the microcontroller. Thus a simple communication via
Ethernet from the desktop PC is required for download/upload to/from
the memory.
The FPGA board is attached to an Ethernet PHY device such as DP83847A.
In this case a MAC controller was implemented in FPGA but the FPGA
utilitization is too high. There is less room available for other
blocks. My intention is to build a small TCP/IP stack and MAC blocks
in the FPGA and the transaction between FPGA/Ethernet PHY and the
desktop PC has to kept as simple as possible. Thus no heavy/extensive
protocol is needed.
The questions raised are:
1. What is the minimum TCP/IP function set required to do simple file
transfer and etc.?
2. Is it possible to perform all tasks only in FPGA without help of
the microprocessor?
3. Are there any resources (VHDL code and C program on PC) available
on this topic?
I will welcome all comments and suggestions. please feel free to write
us at erik.coenders@philips.com Thank you all.
I hope Google won't eat the first reply, so here's an addition to it,
some parts of fitter report are below:
news@rtrussell.co.uk wrote in message news:<bgdmcf$73u$1@nntp0.reith.bbc.co.uk>...
I have a design (admittedly making heavy use of the device resources)
which successfully fits into an XC9536 but not an XC9536XL. This is
something I hadn't anticipated when migrating to the newer part. Is
this to be expected, and is it likely that by tweaking any fitter
options (or otherwise) I will be able to get the design to fit ?
I am using Xilinx Foundation F4.2i, Build 3.1.196.
Richard.
http://www.rtrussell.co.uk/
cpldfit: version E.33 Xilinx Inc.
Fitter Report
Design Name: iw Date: 4- 1-2003,
4:17AM
Device Used: XC95144XL-5-TQ144
Fitting Status: Successful
**************************** Resource Summary
****************************
Macrocells Product Terms Registers Pins Function
Block
Used Used Used Used Inputs
Used
143/144 ( 99%) 558 /720 ( 77%) 100/144 ( 69%) 111/117 ( 94%) 415/432
( 96%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used
Remaining
------------------------------------|---------------------------------------
Input : 58 58 | I/O : 104
5
Output : 44 44 | GCK/IO : 2
1
Bidirectional : 8 8 | GTS/IO : 4
0
GCK : 1 1 | GSR/IO : 1
0
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 111 111
*********************Function Block Resource
Summary***********************
Function # of FB Inputs Signals Total O/IO
IO
Block Macrocells Used Used Pt Used Req
Avail
FB1 18 53 53 67 12/0
15
FB2 18 53 53 57 7/0
15
FB3 18 51 51 87 14/0
15
FB4 18 51 51 71 0/1
15
FB5 18 52 52 83 8/0
14
FB6 18 52 52 72 1/7
13
FB7 18 51 51 66 0/0
15
FB8 17 52 52 55 2/0
15
---- ----- -----
-----
143 558 44/8
117
So, in dense design you can't rely on Xilinx tools only, I was always
1-2 cells over 144 when I was playing with options, so I had to
constrain things myself...
Are you saying that you lose all of the speed and area over the whole dieRick,
It has to do with the foundires.
What do you offer as your lowest cost standard CMOS process?
.18/.35 was really popular (and still is).
.15/.35 was the half-step between .18 and .13.
.13/.25 is the dominat process right now (3.3V is a tough push, and has to
be done carefully, and 5V is definitely gone)
90nm/.25u is what we are in for Spartan 3, so there has to be a reason
(like all those three letter companies that offer standard CMOS
processes....)
If you havce 90nm/.35u (no reason why it can't be done), you lose all your
speed and area by having to drive the huge .35u transistors (makes for a
more expensive die).
Does it mean that figure 6. in xapp139 (Device configuration flow
diagramm) has error? The "Reconfigure path" trough "Shundown sequence"
is available or not?
under "shutdown sequence" i mean the process described on p14 XAPP139
[ from XAPP139
1. Load the CFG_IN instruction into the JTAG instruction register.
Next, go to the SHIFT-DR
....
COR (Configuration Option Register) with the SHUTDOWN bit = 1
....
]
the described process does not need access to PROG
--------------------
Thanks.
Sergey.
Why not try a D flip-flop with the not-Q output connected back to the DI have a querry regarding CPLD, we are using. It is XC9536XL and
XC9572TQ100 Xilinx CPLDs.
I tried to develop a simple divide by two scheme, with a T flip flop,
with T pin tied high and clock given to flip flop through one of the
global clock I/O pins of CPLD. It is expected to get pulses of half
the frequency at Q output of the flip flop, with Q output toggling at
every positive edge of clock. However, I get some pulses of
continually varying frequency at the output pin.
The devices I used are, XILINX WEBPACK ISE 4.2 as HDL editor, Impact
tool for program download.
Kindly guide me as to the possible sources this ambiguity.
Austin Lesea <Austin.Lesea@xilinx.com> wrote:
...
: If you havce 90nm/.35u (no reason why it can't be done), you lose all your
: speed and area by having to drive the huge .35u transistors (makes for a
: more expensive die).
Austin,
just for interest, is there any document showing the schematics of such a
mixed voltage output stage? I think driving the PMOS of the output stage is
quite tricky, without sacrificing to much current.
Bye
--
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Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
On Mon, 04 Aug 2003 09:46:48 -0700, Austin Lesea wrote:
Rick,
It has to do with the foundires.
What do you offer as your lowest cost standard CMOS process?
.18/.35 was really popular (and still is).
.15/.35 was the half-step between .18 and .13.
.13/.25 is the dominat process right now (3.3V is a tough push, and has to
be done carefully, and 5V is definitely gone)
90nm/.25u is what we are in for Spartan 3, so there has to be a reason
(like all those three letter companies that offer standard CMOS
processes....)
If you havce 90nm/.35u (no reason why it can't be done), you lose all your
speed and area by having to drive the huge .35u transistors (makes for a
more expensive die).
Are you saying that you lose all of the speed and area over the whole die
or just for the IO section? If it's just the IO that would be OK in a part
like this. A part aimed at the 5V interface market doesn't need fast IOs
because the clock rates in that world are low. It does need the logic and
RAM density of a modern part, if it wasn't any denser than an old .18u
part then you might as well stick with the older part or live with
external level shifting transceivers.
Hi,
I have to connect a LCD-I2C to my FPGA.
My LCD can be supplied only with 5V, and I have only a 3.3V.
Do you know a low cost step-up dc-dc converter solution.
I only need 2 mA as output current.
Regards,
Laurent
Scary stuff indeed John!I got my UARTlite driver for uClinux working just yesterday
I will check out your source from work and take a look tomorrow butstill a couple of bugs but expect to iron them out today.
I most certainly do. Should save me some time since I have a kernelYou are welcome to try it in PPC linux if you wish
If not I am certainly not bothered in fixing that since you are savingIn principle it should drop straight into Linux.
Is this a University related project perchance?http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
Yeah I had a few tough moments figuring out the alignment and dealingI was going through the serial driver code recently and realised this is
not going to be a trivial patch because there is no standard support for
describing odd register offsets like with the XuartLite in serial.c.
Certainly I will try your driver and submit any patches and so forth.
OK cool. What is the status of V2Pro/PPC linux these days from a userI most certainly do. Should save me some time since I have a kernel
booting now on the Insight board and falling over after it tries to
flush the ring buffer to a non-existent serial console.
I am actually really pleased because prior to this there were a whole
host of memory management issues which would not go away and still there
are spurious and unexplaned Machine Checks that e.g. NetBSD just ignore.
Yeah I'll avoid the 16550 for as long as possible, for simple consoleI was looking at the Microblaze stuff earlier thinking someone must have
already solved this problem and avoided buying the 16550 for Linux.
Yep - see my post a few lines down. uClinux plus RTAI real-timehttp://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
Is this a University related project perchance?
Hi,
I'm trying to use stacked 100Mbit ethernet modules with the Nios Development
Kit (Apex 20K) to create a secure firewall/bridge device for a university
project.
However, I can't even get the example application included with the kit,
"nedk_bridge.c" to work.
I have the nedk_bridge program running on the Apex board. Each ethernet
module is connected via crossover cable to a PC. I then try doing a simple
ping from one PC to the other and view the results using the Ethereal packet
sniffer:
snip
The 1st PC sends the ARP request, the 2nd PC receives it, replies to the
request, but the 1st PC never recieves the reply. The Nios for some reason
never sends the final packet. If I initiate the ping from the other PC, the
same thing happens - the first three packets are sent, but the last one is
dropped.
Is the Nios even capable of functioning for the purpose I want to use it
for? I noticed that the Nios always initializes the ethernet modules in
half-duplex mode. Altera themselves give frustratingly little info about
this.
I am using Quartus II 2.2, SOPC builder 2.52 (Nios CPU version 2.1), and
Nios EDK 2.0 (LAN91C111 modules).
Thanks,
Simon
Look around for a simple charge-pump circuit.Hi,
I have to connect a LCD-I2C to my FPGA.
My LCD can be supplied only with 5V, and I have only a 3.3V.
Do you know a low cost step-up dc-dc converter solution.
I only need 2 mA as output current.
Does it do any good to use a similar setup for power?Not "all", just one extra per Vcco power/ground pin pair is all that is required
to reduce ground bounce by another 20% (roughly). The IO is set to a strong
standard (ie GTL, PCI, CMOS 24 mA, etc.) and set to a logic '0'. The pin is
connected to the ground plane just like a ground pin. Adding pins past the
first leads to a very small improvement (not worth it).
How does that table/CAM get initialized?The other thing is that networking switches employ hardware lookup
(using CAM) to decide which port an incoming network frame should go out.
A router could probably use a similar scheme to route a packet,
avoiding a routing table in software(software means slow.)
I figured why the decided to do that was mostly down to making theYeah I had a few tough moments figuring out the alignment and dealing
with pointer aliasing and stuff - seems to be mostly figured out now.
I am about to take a look at that which will be fun because I cannot beThe uartlite is a funny thing, on the surface it looks like a fully
featured uart, but when I delved a bit deeper there are some
idiosyncracies that make it just that bit more tricky - like the
interrupt generation, for example.
As I said privately there is a bunch of patches but not a single sourceOK cool. What is the status of V2Pro/PPC linux these days from a user
perspective?
We only need the UART for debugging which makes the 16550 IP a littleYeah I'll avoid the 16550 for as long as possible, for simple console
stuff the uartlite should be fine.
Not "all", just one extra per Vcco power/ground pin pair is all that is required
to reduce ground bounce by another 20% (roughly). The IO is set to a strong
standard (ie GTL, PCI, CMOS 24 mA, etc.) and set to a logic '0'. The pin is
connected to the ground plane just like a ground pin. Adding pins past the
first leads to a very small improvement (not worth it).
Does it do any good to use a similar setup for power?
--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.