EDK : FSL macros defined by Xilinx are wrong

[Lorenzo Lutti]

"Kolja Sulimma" <news@sulimma.de> ha scritto nel messaggio
news:b890a7a.0307310821.4bbe0c89@posting.google.com...

A few weeks ago I send out a request for quotes for 100
pieves XC2S200
to all european xilinx distributors and got a single
response!

You are so damn right, same problem here in Italy. I gave up some
time ago, now I buy Xilinx parts from Digikey for the prototypes, and I
let the assembliers buy them for the production.

I wonder why Xilinx doesn't have a WebShop where you can buy anything...
why only the CPLDs? And why it doesn't provide a direct samples service
like other big companies? Each time I ask my distributor for a sample is
a pain in the ass, I never know when (or if) it will arrive.

--
Lorenzo

 

[Philip Freidin]

On 2 Aug 2003 12:28:58 -0700, sandeep_babel@yahoo.com (Sandeep) wrote:

Hello everyone,


I am new in this field.. i just wanted to ask which development boards
will be best suited for starters.. are there any sites that gives a
comparison of the different development kits from the different
vendors, and some cheap distributor of these kits in the US.
Also wanted to know abt some projects for beginners in fpga design..
please suggest me some and the associated reading that i will have to
do with them.

thnks a lot in advance,

-- sandeep

Have a look at:


http://www.fpga-faq.com/FPGA_Boards.htm



===================
Philip Freidin
philip@fliptronics.com
Host for WWW.FPGA-FAQ.COM

 

[Jimmy Zhang]

Rich, do you happen to live in SF bayarea? If so could you email me using
address of this posting?
I am looking for some help on FPGA.

Thanks,
Jimmy Zhang

"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F2D3614.AD21FDEF@yahoo.com...

zhengyu wrote:

I've got two quick question. I don't have FPGA yet, but I want someone
to
offer me some quick comments

1. I have got to do some 64 bit integer comparison, actually I have to
do up
to 64 comparisons at the same time, the output is whether there is any
pair
that equals.

This is not a question...

Equality compares are easy. It uses a two input XOR for each bit with
all the results being OR'd together. This will take 32 LUTs for the XOR
and the first OR gate and 11 more LUTs to combine the rest for a total
of 43 LUTs in four levels. If the design uses the "special" features
that most chips have (ORing of LUTs within a CLB), you can use the LUTs
in pairs or even groups of four and reduce the number of levels for
speed.


2. If I want to create an 16 bit address space, that would translate to
512
k bits, does Vertex II give enough
block RAM so I don't have to use SRAM to do that? What kind of latency
performance should I expect from
typical SRAM, is 5ns read access reasonable?? what is the performance of
block ram??

Is that 16 bit address (64k words) of 8 bit words? Because 64k x 8 =
512K.

You can get this much RAM in the VirtexII if you use the XC2V500 part.
Or in the new Spartan3 you could use a XC3S1500. I am not sure which
will be cheaper, but I bet it is the Spartan3.

The speed of the block RAM will be much faster than anything external to
the FPGA. The block ram will be synchronous and lends itself well to
pipelined operations.

A lot of how you design will be implemented will depend on your data
flow which you have said nothing about. Think about how the storage
will be orgainized and accessed. Obviously one large block of memory
with one interface will not let you do 64 compares at one time. If you
rate of performing these compares is not fast, you can use one compare
logic block and run the different data through it sequentially. Then
one memory could easily do the job.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Neeraj Varma]

Cypress is anyway getting out of the PLD business...
http://www.eet.com/semi/news/OEG20030730S0063


"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F2A84FE.20106575@yahoo.com...

Marc Randolph wrote:

rickman <spamgoeshere4@yahoo.com> wrote in message
news:<3F29C212.EC74896B@yahoo.com>...
I have been given a very good price on the Coolrunner XCR3512XL, but
even with 512 macrocells, including small FIFOs (8 bits x 16 words,
two
FIFOs) uses up half the chip.
^^^^^^^^^^^^^
Unless the design is complete and you can verify that it fits AND you
have a pinout, this would scare the hell out of me. I have to admit
not having used the Coolrunnner, but over the past six years, we have
had an absolutely horrible time making very minor changes to
moderately full 95xxx series Xilinx CPLD's. Again, this may not apply
as much to the Coolrunner, since it is a completely different family -
but I'd still verify it first.

I agree with the other poster - what about the Cypress or Lattice
devices? I realize that gets you away from your "all Xilinx" board,
but is there really a good reason for desiring that (except maybe you
can get all parts from one distributor)?

No, sticking with Xilinx is not a strong desire since the software is
not common anyway. But Lattice has nothing that will fit this socket
and I have not been able to get a decent price on a Cypress part. I
guess that is also part of my goal to use Xilinx. I have gotten some
really great pricing on the parts I have discussed with them. They are
working with me, so it makes me want to work with them.

But I agree that using the XCR3512XL is scaring me as well. That is why
I am asking about other Xilinx alternatives.

I am sure I looked at the Cypress parts. I need about 170+ IOs in a 256
FBGA. The insides are not real important since that many IOs almost
always means a larger part than what I need, say 20,000 gates or 1000
LUT/FF. The memory is optional since with that many FFs I can make my
own FIFOs easily. Any idea of what a real price in a Cypress part would
run? I don't really see much that will fit the socket unless I am
missing something.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[rickman]

Lorenzo Lutti wrote:

"Kolja Sulimma" <news@sulimma.de> ha scritto nel messaggio
news:b890a7a.0307310821.4bbe0c89@posting.google.com...

A few weeks ago I send out a request for quotes for 100
pieves XC2S200
to all european xilinx distributors and got a single
response!

You are so damn right, same problem here in Italy. I gave up some
time ago, now I buy Xilinx parts from Digikey for the prototypes, and I
let the assembliers buy them for the production.

I wonder why Xilinx doesn't have a WebShop where you can buy anything...
why only the CPLDs? And why it doesn't provide a direct samples service
like other big companies? Each time I ask my distributor for a sample is
a pain in the ass, I never know when (or if) it will arrive.

If you are getting free Xilinx samples you are doing better than in the
US. Xilinx does not sample FPGAs in the US and I have never gotten a
disti to sample one either.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Andrew Paule]

What kind of gates - If you are running standard cell type ASIC, then
the vendor can give you a good idea. If it's a semi custom, you can
figure about 40 transistors for most standard logic gates and flops, but
you'll have to build your own and steer the currents with the available
resistors.

Are there mapped cells (i.e. cells that are fixed in your target ASIC)?
Are there dedicated I/O flops, are there clock specific mask layers?
You need the architecture of your target ASIC to get a good idea of this
ratio, and the architecture of your FPGA -Actel SX and SXA can get
pretty close to 1:1 for some types of ASICs, old PAL based CPLD
structures are dependent on what they call a gate, most others are in
between somewhere.

Andrew
Jay wrote:

Hi all,

I'm doing prototyping for ASICs. Before I start my work, I have to estimate
the gates the FPGA or CPLD would use.
I know it's hard to get a precise result. I just want some common answer,
1:3 between ASIC and FPGA/CPLD gate count?(not consider the memory, just
logic)
Please tell me your experience.

Thanks,
Jay

 

[Jay]

Thanks for your response.

To simplify the case, just suppose that I have a 5k gate array ASIC designs
(general logic for control and interface)to implement to one CPLD(may be
CoolRunnerII)

What's the relationship between the ASIC gate array and CPLD macrocells?

"Andrew Paule" <lsboogy@qwest.net>
??????:ynlXa.981$h_3.65136@news.uswest.net...

What kind of gates - If you are running standard cell type ASIC, then
the vendor can give you a good idea. If it's a semi custom, you can
figure about 40 transistors for most standard logic gates and flops, but
you'll have to build your own and steer the currents with the available
resistors.

Are there mapped cells (i.e. cells that are fixed in your target ASIC)?
Are there dedicated I/O flops, are there clock specific mask layers?
You need the architecture of your target ASIC to get a good idea of this
ratio, and the architecture of your FPGA -Actel SX and SXA can get
pretty close to 1:1 for some types of ASICs, old PAL based CPLD
structures are dependent on what they call a gate, most others are in
between somewhere.

Andrew
Jay wrote:

Hi all,

I'm doing prototyping for ASICs. Before I start my work, I have to
estimate
the gates the FPGA or CPLD would use.
I know it's hard to get a precise result. I just want some common answer,
1:3 between ASIC and FPGA/CPLD gate count?(not consider the memory, just
logic)
Please tell me your experience.

Thanks,
Jay

 

[Serg_Y]

Does it mean that figure 6. in xapp139 (Device configuration flow
diagramm) has error? The "Reconfigure path" trough "Shundown sequence"
is available or not?

under "shutdown sequence" i mean the process described on p14 XAPP139

[ from XAPP139
1. Load the CFG_IN instruction into the JTAG instruction register.
Next, go to the SHIFT-DR
.....
COR (Configuration Option Register) with the SHUTDOWN bit = 1
.....
]

the described process does not need access to PROG

--------------------

Thanks.
Sergey.

 

[Serg_Y]

1. iMPACT doesn't do this quite easily. You can use the debug bitstream
functionality and start shifting data in with the appropriate JTAG
instructions.

I am sorry for my verbosity. Let me explain.
I did find "TAP debug" dialog in iMPACT. But it is extremely dificult
and time-consuming to enter commands bit-by-bit.
Is there a way to perform the comands in batch mode or place them into
bitstream file? In my prev. message i ask about tools doing this.

BR,
Sergey Yemets
Samsung Software Center (Moscow Branch Office)

 

[Rob Judd]

Marc,

Looking at the AT94K05AL right now ... 5K usable gates, 20K SRAM.

EP1C6 (a better comparison) - 6K LE's (registers), 92K ram

APA150 - 150K gates, 6K registers, 36K ram

Add to that the need for an expensive IAR compiler for the AVR core and
it's pretty average. It's difficult to do a meaningful feature
comparison though, owing to the different architectures. I do know that
the EP1C6 and APA150 are very similar in price (when the config chip is
added into the equation). May check out the Atmel too, just to be sure
I'm not missing out on any bargains.

Rob



Marc Van Riet wrote:

But you are considering the Altera EP1C3 or the Actel APA150. Very hasty
comparison :
- dedicated flip flops : EP1C3 = 2910, APA150 = 0 (well, 6000), FPSLIC =
2800
- ram bits : EP1C3 = 60K, APA150 = 36K, FPSLIC = 128K (?)
Just to say the FPSLIC doesn't seem that small. Don't know how efficient
the architecture is though.

Just a note : the AVR core and peripherals are not implemented in the FPGA,
they are on dedicated silicon. So they are not wasting any space.

But of course it depends on the applications you have in mind. If you
didn't plan to have a microcontroller core, then this is not the device
you're looking for. Otherwise the device seems like a good idea, but didn't
hear of many people using it though. As Rickman mentioned, fear of it being
cancelled after a few years may have to do with this.

Regards,
Marc

"Rob Judd" <judd@ob-wan.com> wrote in message
news:3F2D5868.C49B912E@ob-wan.com...
40K gates is way too small for anything I'm considering, and the "added
value" stuff just wastes internal space. We all know where to find AVR
core and serial if we want it.

Rob


Marc Van Riet wrote:

Anyone any experience with the FPSLIC devices ? They have several
packages
with low pin count (84 PLCC, 100 VQFP, 144 TQFP). Only up to 40Kgates
FPGA
(2800 registers), but you do have a processor core, and several
peripherals,
and 32Kbytes + 16 Kbytes of memory already built-in.

Marc

 

[David Hart]

On Sun, 03 Aug 2003 23:11:50 +0000, Philip Freidin wrote:

On 2 Aug 2003 12:28:58 -0700, sandeep_babel@yahoo.com (Sandeep) wrote:
Hello everyone,


I am new in this field.. i just wanted to ask which development boards
will be best suited for starters.. are there any sites that gives a
comparison of the different development kits from the different
vendors, and some cheap distributor of these kits in the US.
Also wanted to know abt some projects for beginners in fpga design..
please suggest me some and the associated reading that i will have to
do with them.

thnks a lot in advance,

-- sandeep

Have a look at:


http://www.fpga-faq.com/FPGA_Boards.htm

Actually, that's:

http://www.fpga-faq.com/FPGA_Boards.shtml

===================
Philip Freidin
philip@fliptronics.com
Host for WWW.FPGA-FAQ.COM

 

[Jim Granville]

Neeraj Varma wrote:

Cypress is anyway getting out of the PLD business...
http://www.eet.com/semi/news/OEG20030730S0063

Nearly.
They ARE getting out of SPLD, and older process CPLD
devices.

-jg

 

[Rob Judd]

Marc,

By a very strange coincidence, a Belgian friend of mine (well, he's from
Bruges so he's a bit weird who designs very tiny RF and micro boards
(mostly portable stuff using MSP430) happened to have a kit from
www.kanda.com that uses the AT40K chip. He offered it to me - complete
with tool chain - for as long as I need it.

So, it looks like I'm AVR'ing for now, but I'd rather be drinking a nice
cold Orval.

Rob


Marc Van Riet wrote:

But you are considering the Altera EP1C3 or the Actel APA150. Very hasty
comparison :
- dedicated flip flops : EP1C3 = 2910, APA150 = 0 (well, 6000), FPSLIC =
2800
- ram bits : EP1C3 = 60K, APA150 = 36K, FPSLIC = 128K (?)
Just to say the FPSLIC doesn't seem that small. Don't know how efficient
the architecture is though.

Just a note : the AVR core and peripherals are not implemented in the FPGA,
they are on dedicated silicon. So they are not wasting any space.

But of course it depends on the applications you have in mind. If you
didn't plan to have a microcontroller core, then this is not the device
you're looking for. Otherwise the device seems like a good idea, but didn't
hear of many people using it though. As Rickman mentioned, fear of it being
cancelled after a few years may have to do with this.

Regards,
Marc

"Rob Judd" <judd@ob-wan.com> wrote in message
news:3F2D5868.C49B912E@ob-wan.com...
40K gates is way too small for anything I'm considering, and the "added
value" stuff just wastes internal space. We all know where to find AVR
core and serial if we want it.

Rob


Marc Van Riet wrote:

Anyone any experience with the FPSLIC devices ? They have several
packages
with low pin count (84 PLCC, 100 VQFP, 144 TQFP). Only up to 40Kgates
FPGA
(2800 registers), but you do have a processor core, and several
peripherals,
and 32Kbytes + 16 Kbytes of memory already built-in.

Marc

 

[Antti Lukats]

Is there a way to perform the comands in batch mode or place them into
bitstream file? In my prev. message i ask about tools doing this.

get JAM player, write some JAM functions and talk to the JTAG port
anyway you wish.

you can as example
use BSCANVIRTEX and connect it to ICAP and reconfig
or use use normal JTAG config commands or send commands to your
custom JTAG functions/register (USER1, USER2 commands)


antti

 

[EU]

Hi

I achieved only 550kBps, but I didn't do any soft emulation or
negociation. If your port is set to epp/ecp, there's a register in the
ecp configurations that changes the mode of the port to ecp, epp or
spp. If your port is set to epp in the bios, it should allways be
so...

Ricardo

Yash Bansal <yash@boa.ece.ucdavis.edu> wrote in message news:<Pine.HPX.4.21.0307311327130.17547-100000@boa.ece.ucdavis.edu>...

On Thu, 31 Jul 2003, Jon Elson wrote:

Yes, I have 2 commercial products using this. I get about 800 nS/byte
with a short
IEEE-1284 cable. Note that the PC EPP chips don't follow the IEEE-1284
standard,
they don't delay the strobes, but present them about the same time as
the data
port changes. So, you have to apply delays to the strobes in your device.
Then, you have to have the handshake signals bounce back through the cable
twice (once to tell the CPU data is available, then the request from the CPU
has to go away, then the remote device has to un-busy the bus.)
I don't use any overhead software, but map to the port and control it
directly
with inline assembler directives in the C code for x86 INB and OUTB
instructions.

What are the products that you use? 800nsec/byte transfer rate is great
and will solve all my problems. Currently I get about 10usec/byte as I am
emulating the EPP protocol in SW. I have written a State-Machine in the
FPGA for implementing the EPP protocol but have not done the
EPP negotiation part. On the PC side acquisition software, all I did
was to write a user-level program that made use of the libieee1284
functions.

I am hoping that after implementing the negotiation in the FPGA, the EPP
protocol will run directly without having to emulate it in PC.

My aim is to transfer 40KBytes/sec of data from FPGA to PC using parallel
port.

Thanks,-Yash


1 Meg Byte/second is pretty ambitious, given the performance of the chips.
If you have long blocks of data to transfer (several K bytes in one
block) then
the DMA mode of transfer may go a little faster. I haven't done this,
as 20 bytes or
so at a time is the most I can do with my particular device.

What is the rate of data transfer you are getting now? What method are
you using to access the parallel port?

Jon

 

[Paul Leventis]

Hi Rob,

After reading the ProASIC Plus data sheet, I believe you should be comparing
to a Cyclone EP1C3, not a EP1C6.

EP1C6 (a better comparison) - 6K LE's (registers), 92K ram
APA150 - 150K gates, 6K registers, 36K ram

The APA series uses a logic cell that can be either a 3-input LUT or a flop.
Cyclone (EP1Cx) has a 4-input LUT _and_ a register, plus a bunch of
dedicated circuitry for performing asynchronous clear, asynchronous load,
synchronous clear, synchronous load, clock enable, dynamic add/subtract, and
other stuff I'm probably forgetting. The register and LUT can feed one
another, or can be used independently, allowing LUTs and flops to be packed
together into a single cell. So my guess is that a APA150 with 6K cells will
be somewhere in the neighbourhood of the density of a EP1C3.

In addition, the APA devices are manufactured on a .22u technology with
programmable cells, while Cyclone is manufactured on a 0.13u copper process.
My guess is that Cyclone will be signficantly faster.

Of course, your best bet is to get your hands on the CAD tools and push the
big green button . Cyclone is supported in the Web Edition of Quartus II
3.0, available at www.altera.com.

Regards,

Paul Leventis
Altera Corp.

 

[Austin Lesea]

cfk,

Not "all", just one extra per Vcco power/ground pin pair is all that is required
to reduce ground bounce by another 20% (roughly). The IO is set to a strong
standard (ie GTL, PCI, CMOS 24 mA, etc.) and set to a logic '0'. The pin is
connected to the ground plane just like a ground pin. Adding pins past the
first leads to a very small improvement (not worth it).

Making these grounds adjacent to clock inputs, or Vref pins can also aid in the
reduction of user pcb crosstalk. The packages already have 3X spacing for every
Vref, which means that x-talk coupling to/from Vref pins is 1/9 that of the
coupling to any other pin in the package (ie, the package is not the 'problem').

Austin



cfk wrote:

And just to add a little spice to that broth, it was suggested one of the
local Xilinx support folks on our last design to ground all the unused IOB
pins and create more of a "virtual ground" (their term, not mine).

"William LenihanIii" <lenihan3we@earthlink.net> wrote in message
news:5V_Wa.31676$Mc.2501134@newsread1.prod.itd.earthlink.net...
We will be designing with a large (xc2v6000) Virtex-II part in a ball-grid
array package that has maybe ~1000 balls, but we are using fairly few
(~250)
"mission logic" I/O. Add in power & ground, configuration, etc., we will
have 100's of general-purpose I/O balls that are not needed.

What should we do with them? Ground them? Let them float? If we can let
them
float, do we even need a solder pad on the PWB for them to "land on"?

 

[Yevgeny K.]

Or maybe there is a way to configure NIOSes SDRAM controller to support
two NIOS CPUs instead of using that external arbiter?


The second thing I can suggest, and would recommend, is to make use of
our own bus arbitration logic. You can in fact connect two (or more)
masters (two Nios', DMA, your own custom master, another
microprocessor) to any avalon slave, including the SDRAM controller.


I believe that in the end I will use this controller, but for now I just have
to use the "external" arbiter, because this controller/arbiter allows me to
access the SDRAM directly through the PCI (the development board is a PCI card)

I've decided to use Nios'es SDRAM controller, so please disregard my last
question - that third-party arbiter caused too much problems.

So thanks anyway,
Yevgeny

 

[Austin Lesea]

Rick,

My point exactly. If you simulate a TTL driver, you will note it can't pull up enough
to violate our spec, and so no resistor is required.

Of course, it has to be a TTL driver, and not a CMOS driver!

Now given anyone can build a pcb and sell it, I would go with the TI, or Quickswitch
NMOS pass-gate voltage limiter part to be safe (and 100% compatible).

Austin

rickman wrote:

Austin Lesea wrote:

Rick,

Fair enough. If it has to drive all the way to 5.0 V CMOS, then you have outlined
your constraints.

Too bad that they did not choose to be TTL compatible.

Are you talking about the PC/104 bus? That is based on the ISA bus,
which IIRC predates FPGAs. I think you mean too bad it is not limited
to TTL thresholds. Even TTL logic outputs can and will rise above 3.6
volts if lightly loaded. The pullup resistors are there for wire ORing
of a few signals (like ENDXFER- and IOCH16-) which I am sure you are
familiar with. The pullups are stiff to give speed. How else would you
have done that?

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Austin Lesea]

Anything is possible,

But you can't use 90nm for 5V. The minimum size you can use is .35u.

A combo 90 nm/ .35u process is not in the roadmap, so that makes life a bit
tough.

But then again, where is the $?

Peter and I are engineers, not marketeers, so we defer to the marketing folks
who seem to know just how large (small) the 5V market is....

Austin

"B. Joshua Rosen" wrote:

Peter, Austin,

Is it possible to build 5V IOs on a 90nm process? The world is full of
antique buses that aren't going to go away anytime soon. A couple of
medium sized devices targeted at the legacy bus interface market would be
useful. I'd suggest doing two devices, a XC3S1500 and a XC3S400 with
5V/3.3V IOs. You could toss the multipliers, those aren't useful in this
application, as well as all of the fancy modern IO standards which also
aren't needed for this application, block RAM is important because bridges
need large FIFOs. The other thing that you would want to do is modify the
DCM so that it could support lower clock frequencies, 10Mhz -20Mhz is
common in this world.