EDK : FSL macros defined by Xilinx are wrong

[Marc Battyani]

"Allan Herriman" <allan_herriman.hates.spam@agilent.com>

On Tue, 8 Jul 2003 14:33:20 +0200, "Marc Battyani"
Marc.Battyani@fractalconcept.com> wrote:
I want to make a phase measurement at 100MHz with a NCO at 200+ MHz
This NCO will have a 32 bit phase accumulator and a 32 bits phase offset.
The
output will be only one bit.
I will use a phase comparator followed by an integrator (digital or
analogic
if needed).
At 100MHz the NCO output will be very very noisy but if I integrate it for
a
rather long time (10ms) will it have a 0 mean ?
Can I implement this in an FPGA or should I use a DDS chip (AD9854) ?
Where can I find some maths on this subject ?

Do you need to know the spectrum of the noise, or just the peak to
peak value?

The spectrum I think. In fact I need to have a very precise phase lock
(0.1%). The frequency lock is already ok as I have the reference clock.

I sometimes find myself in the situation of having to work out the
spectral characteristics of the phase noise (jitter) of the msb of a
phase accumulator. E.g. if I am using a post-NCO PLL (as Peter A.
suggested) then I only care about the phase noise components at offset
frequencies less than the loop bandwidth of the PLL.

I thought about filtering and integrating the phase error after the phase
comparator. I don't think I need a PLL as I'm not synthesising a frequency.

I don't know of a closed form expression for spectrum of the noise,
but it's trivial to work out the spectrum with a spreadsheet (once you
know how). This is much easier that trying to measure the spectrum in
the lab.
(Reply if you are interested in the method.)

Sure, please explain how to do it, I'm really interested.

BTW, Peter's trick of reducing the jitter by a factor of 4 (I assume)
relies on using a 4 phase clock. This is almost certainly worth the
effort if you are trying to reduce the jitter.
I have a worked example that uses a 2 phase clock (actually it uses
both edges of a single clock) in my free fractional N divider
generator, at this web site:
http://fractional_divider.tripod.com/
(Note: some web proxies don't like domain names with underscores.)

Thanks, I will look at it.

Marc

 

[Marc Battyani]

"Peter Alfke" <peter@xilinx.com> wrote in

I have been playing around with the idea of a 32-bit DDS circuit at 200
MHz ( as a digitally controlled VCO) and I know some tricks to reduce
the timing uncertainty from the obvious 5 ns by a factor of 4. Then I
was going to use an external PLL to reduce it further.
These are just ideas...

I'm trying to have an almost all digital solution. I would rather use a DDS
rather than a PLL as I'm not generatin a frequency.
I just want to lock on the phase. (I have the reference frequency) I'ts a
kind of DLL...

Marc

 

[Jim Granville]

Marc Battyani wrote:

"Peter Alfke" <peter@xilinx.com> wrote in
I have been playing around with the idea of a 32-bit DDS circuit at 200
MHz ( as a digitally controlled VCO) and I know some tricks to reduce
the timing uncertainty from the obvious 5 ns by a factor of 4. Then I
was going to use an external PLL to reduce it further.
These are just ideas...

I'm trying to have an almost all digital solution. I would rather use a DDS
rather than a PLL as I'm not generatin a frequency.
I just want to lock on the phase. (I have the reference frequency) I'ts a
kind of DLL...

Sounds challenging : If I have this right
You have 100MHz 'incomming' (hopefully very clean and phase stable
You want to lock to 0.1%, (or 10ps), nominally 200MHz local Osc
You can tolerate longer lock acquire times

Analog Phase locked loops work because they integrate
the phase-magnitude errors,
- In a digital system, edge resolution of 10ps may be just possible, but
I'm not sure you can get any error-proportional siganl.
Go-right/Go-Left control is likely to be swamped by the phase-noise of
the DDS signal.....
-jg

 

[Liang Yang]

Hi ,

Thanks for your reply.

I even tried to initialize this inout port to all 0, but it still shows "UU"
when I start simulation. During pre-synthesis simulation,
the initial value of DATA is also "UU", but it changes to correct value
after assignment take effect in the test bench.

I try to figure out which one is driving this DATA port when its value
is changed. But I don't know how to do this in Active HDL. The break point
is located in the lsi_10k library and I can't trace it until the program
control
comes back to my program.

Thanks.

Liang


Here is my code:
--design.vhd
library lsi_10k;
use lsi_10k.all;
....
entity DESIGN_UNIT is

port( DATA : inout std_logic_vector (7 downto 0) := "ZZZZZZZZ"; ...);

end DESIGN_UNIT;

--testbench.vhd
entity test_bench is
end entity test_bench;

architecture behav of test_bench is
signal DATA: std_logic_vector(7 downto 0);
signal Clock: bit :='0';
...
begin
DUT: entity DESIGN_UNIT
port map(DATA, ctl_data, ctl_op, Reset, Clock);

simulation: process is
begin
clock <= '0';
wait for 20 ns;

DATA <= "00000001";
Clock <= '1';
wait for 20 ns; -- DATA port will become "XX" at 20+1 ns

wait;
end process;
end architecture behav;

"Mike Treseler" <mike.treseler@flukenetworks.com> wrote in message
news:3F0AF3F7.3010105@flukenetworks.com...

Mike wrote:

I declared a std_logic_vector(7 downto 0) (inout type) entity port
in my VHDL program. In the testbench, I will try
to assign some value to this port. But after synthesis
using Synopsys Design Compiler, I found this port wouldn't
accept the value from signal assignment in the test bench
and the value of this port becomes "XX".


Post your code. Your output enable logic is likely the problem.

-- Mike Treseler

 

[Ed Henciak]

"DK" <dknews@ueidaq.com> wrote in news:3eff173f$1_3@newsfeed:

Hi, All

for the new multichannel filter design I have a choice -
Altera Cyclone EP1C12 ($60) or Xilinx Spartan-3 XC3S1000(???)

$60? What speed grade are you using?

Also, is this low quantity pricing (~<100)?

I could have sworn I was quoted a similar price for something as large as
a EP1C20 in lower quantities (~<100) for a respin/cost reduction project
I was going to do. Don't hold me to that...I'd have to check my notes at
work!

Thanks!

Ed

Xilinx part has a embedded MAC units.

I've used in a past Altera chips and they have a good tech support and
free tools.

Does any one has experience with Xilinx support? And is it possible to
obtain a free tools from Xilinx or they charge for the software?

Any other hidden issues?

Thanks,

Dennis

dknews@ueidaq.com

 

[rickman]

BRANE-NEWS wrote:

"rickman" <spamgoeshere4@yahoo.com> wrote in message

SNIP
I am not looking for champagne on a beer budget, but I would sure like
to be able to pour them both into the same glass.

Isn't that a bit of redneck perspective -champagne in Budweiser glass ? ;o)

That's what we call a Fredneck around here...

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Christian Haase]

Hello Steve,

Thanks for the information.

Christian

 

[Nicholas C. Weaver]

In article <3F0BA49F.2FBCB891@yahoo.com>,
rickman <spamgoeshere4@yahoo.com> wrote:

If there is an Ethernet card in the machine, I can't assure my customers
that it will not be connected in a forgetful manner.

Why not take the ethernet card and attack the connector with
wirecutters? You get a MAC address but the net don't work.
--
Nicholas C. Weaver nweaver@cs.berkeley.edu

 

[Allan Herriman]

On Wed, 9 Jul 2003 01:08:36 +0200, "Marc Battyani"
<Marc.Battyani@fractalconcept.com> wrote:

"Allan Herriman" <allan_herriman.hates.spam@agilent.com
On Tue, 8 Jul 2003 14:33:20 +0200, "Marc Battyani"
Marc.Battyani@fractalconcept.com> wrote:
I want to make a phase measurement at 100MHz with a NCO at 200+ MHz
This NCO will have a 32 bit phase accumulator and a 32 bits phase offset.
The
output will be only one bit.
I will use a phase comparator followed by an integrator (digital or
analogic
if needed).
At 100MHz the NCO output will be very very noisy but if I integrate it for
a
rather long time (10ms) will it have a 0 mean ?
Can I implement this in an FPGA or should I use a DDS chip (AD9854) ?
Where can I find some maths on this subject ?

Do you need to know the spectrum of the noise, or just the peak to
peak value?

The spectrum I think. In fact I need to have a very precise phase lock
(0.1%). The frequency lock is already ok as I have the reference clock.

Hmmm, 0.1% of what? "Phase lock" is usually specified as an angle
(degrees, radians or unit intervals) or as phase noise (dBc/Hz).

What are you actually trying to do?

I sometimes find myself in the situation of having to work out the
spectral characteristics of the phase noise (jitter) of the msb of a
phase accumulator. E.g. if I am using a post-NCO PLL (as Peter A.
suggested) then I only care about the phase noise components at offset
frequencies less than the loop bandwidth of the PLL.

I thought about filtering and integrating the phase error after the phase
comparator. I don't think I need a PLL as I'm not synthesising a frequency.

You are synthesising a frequency with the NCO, even if that wasn't
your intention.

I don't know of a closed form expression for spectrum of the noise,
but it's trivial to work out the spectrum with a spreadsheet (once you
know how). This is much easier that trying to measure the spectrum in
the lab.
(Reply if you are interested in the method.)

Sure, please explain how to do it, I'm really interested.

Rough description here:
http://groups.google.com/groups?threadm=379cf6a6.1375761%40newshost

BTW, Peter's trick of reducing the jitter by a factor of 4 (I assume)
relies on using a 4 phase clock. This is almost certainly worth the
effort if you are trying to reduce the jitter.
I have a worked example that uses a 2 phase clock (actually it uses
both edges of a single clock) in my free fractional N divider
generator, at this web site:
http://fractional_divider.tripod.com/
(Note: some web proxies don't like domain names with underscores.)

Thanks, I will look at it.

Marc

 

[Kolja Sulimma]

1.
Especially if the problem at hand is that easy to solve, altera should
help them out. If a company reacts like that to simple problems I
would get suspicious what happens if something serious goes wrong.
(BTW.: I had very similar problems with Xilinx in germany.)

2.
I always thought that ethernet based protection is particulary useless
as one can
- install the software inside a virtual machine with any virtual MAC
address one likes
- write a dummy driver that tells the system that a deactivated NIC
with the
MAC address of choice is present in the system.

The only protection mechanism that is even more useless is volume-ID
base protection.

Kolja Sulimma


charleybrant@hotmail.com (CB) wrote in message news:<3f0b2099.10419733@news.compuserve.com>...

Geeze .... I'm glad altera doesn't waste valuable time on your problem
, they have real work to do. They have standardized on the ethernet
interface, if you have a desktop spend $15 and buy one,

 

[Allan Herriman]

On 9 Jul 2003 06:08:30 -0700, fpga_uk@yahoo.co.uk (Isaac) wrote

Hi,

I am using singal of 32 bit's lenght in my .vhd file and I am
compiling using Makefile. I have also defined a UCF file. My UCF file
is generating error when run ngd build using Makefile. The error is
given below :

Are you sure your signal is 32 bits? You might have declared it as 32
bits, but the synthesiser may remove bits (such as 31 downto 7) if
they are not used. This could cause the error messages you saw.

For an input port, "not used" means that (after logic reduction) it
doesn't affect any outputs.

Regards,
Allan.

 

[z.karim]

Hi,

There doesn't seem to be an architecture associated with
your DESIGN_UNIT entity.


"Liang Yang" <yangliang_mr@hotmail.com> wrote in message
news:befnvc$4bc$1@news.asu.edu...

Hi ,

Thanks for your reply.

I even tried to initialize this inout port to all 0, but it still shows
"UU"
when I start simulation. During pre-synthesis simulation,
the initial value of DATA is also "UU", but it changes to correct value
after assignment take effect in the test bench.

I try to figure out which one is driving this DATA port when its value
is changed. But I don't know how to do this in Active HDL. The break point
is located in the lsi_10k library and I can't trace it until the program
control
comes back to my program.

Thanks.

Liang


Here is my code:
--design.vhd
library lsi_10k;
use lsi_10k.all;
...
entity DESIGN_UNIT is

port( DATA : inout std_logic_vector (7 downto 0) := "ZZZZZZZZ"; ...);

end DESIGN_UNIT;

--testbench.vhd
entity test_bench is
end entity test_bench;

architecture behav of test_bench is
signal DATA: std_logic_vector(7 downto 0);
signal Clock: bit :='0';
...
begin
DUT: entity DESIGN_UNIT
port map(DATA, ctl_data, ctl_op, Reset, Clock);

simulation: process is
begin
clock <= '0';
wait for 20 ns;

DATA <= "00000001";
Clock <= '1';
wait for 20 ns; -- DATA port will become "XX" at 20+1 ns

wait;
end process;
end architecture behav;

"Mike Treseler" <mike.treseler@flukenetworks.com> wrote in message
news:3F0AF3F7.3010105@flukenetworks.com...
Mike wrote:

I declared a std_logic_vector(7 downto 0) (inout type) entity port
in my VHDL program. In the testbench, I will try
to assign some value to this port. But after synthesis
using Synopsys Design Compiler, I found this port wouldn't
accept the value from signal assignment in the test bench
and the value of this port becomes "XX".


Post your code. Your output enable logic is likely the problem.

-- Mike Treseler

 

[rickman]

"Nicholas C. Weaver" wrote:

In article <3F0BA49F.2FBCB891@yahoo.com>,
rickman <spamgoeshere4@yahoo.com> wrote:
If there is an Ethernet card in the machine, I can't assure my customers
that it will not be connected in a forgetful manner.

Why not take the ethernet card and attack the connector with
wirecutters? You get a MAC address but the net don't work.

At this point there is no reason. Altera has provided a license file
keyed to the HDD SN. I was also told that this will be added to the web
site in the near future just as they have for MaxPlusII.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[rickman]

John wrote:

Hey Rickman,

In article <3F0AE7CC.68F9D9D0@yahoo.com>, spamgoeshere4@yahoo.com
says...
I need to vent a little steam. So at risk of making myself look stupid
(or more stupid) I will do it here.

I have been trying to get the Quartus 3.0 software and a license since
last Thursday. I tried three times over the weekend to download it, but
the slow modem link I have to use would not complete the entire transfer
without a problem. I think I have that licked as my brother tells me he
has downloaded it for me.

You might want to look into a *great* utility called "wget".

It's probably comes standard on every modern FreeBSD/Linux
implementation, but not many people in the Windows world know about
it...

See this for a command-line vanilla Windows version:

http://space.tin.it/computer/hherold/

and see this for a Visual Basic GUI wrap-around:

http://www.jensroesner.de/wgetgui/

If you use the plain-vanilla command-line version, just launch like
this:

wget -c <url

-c tells it to continue if a download is aborted...this way if your
modem drops, when you re-connect, just re-issue wget -c <url> and it'll
continue where the file was chopped off.

Yes, I very much should use a program like that. In the past I have
preferred not to add more and more utilities to do a job. Often it can
cause problems which are hard to pinpoint. But I think this is one case
where it is well worth the effort.


--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[rickman]

Falk Brunner wrote:

"rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag
news:3F0AE7CC.68F9D9D0@yahoo.com...

I have been trying to get the Quartus 3.0 software and a license since
last Thursday. I tried three times over the weekend to download it, but
the slow modem link I have to use would not complete the entire transfer
without a problem. I think I have that licked as my brother tells me he
has downloaded it for me.

Get a download manager like Gozilla or something. The can resume a aboarded
download.

My concern is that once installed, I will have no way to control it if I
don't want to use it for some files. I remember Netscape adding
something like this (or I added some download, I can't remember which).
There were times I did not want it to pop up and could not find a way to
turn it off. It also showed ads while running.

Anyone know of a review of download utilities that would help me pick
one?

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Udayan]

Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:<bef5qm$bq9$1@news.tu-darmstadt.de>...

Udayan <udayan@jhu.edu> wrote:
: Hi,

: I am having trouble with the GCLK feature in my design.

: Basically my code is a 4 way handshaking protocol between my PC and
: the FPGA on one hand and another 4 way handshaking with an
: asynchronous chip on the other.

: I am providing a clock to the system through the GCLK0 pin using an
: oscilltor.

: I further require edge tests on three lines that I receive from the
: computer and the chip - which means they are inferred as clock
: signals.

: A total of 4 clocks.

: However when I try to implement the design the engine complains that
: my design is too large

: Number of GCLKs: 6 out of 4 150%
: Number of GCLKIOBs: 1 out of 4 25%

: I cannot understand why this is so. I take the input from my CLKIOB

Look at the synthesis report (*.syr) and at the graphical representation of
your circuit ("View RTL Schematics"). It will give you a glimpse of what is
going on. Then rethink the way you wrote your HDL implementation. In the
synthesis report, the "Clock information" might be the most important
thingto look at.

Bye

SO I checked my design and removed the extra BUFG that was getting
tagged to my divided clock output. However, since I would like to
buffer my divided clock and the Synthesis engine automatically
attaches a BUFG to the GCLKIOB pin input I am still left with one
extra GCLK in my design being used up. Is there some way to get around
that? Would a divide using the clk_dll still use up the extra GCLK
resource?

Also when I do an edge test with my signal lines that arrive at
regular IOBs and pass them through a BUFG the MAP report gives a
warning that:

WARNING:NgdBuild:483 - Attribute "LOC" on "c_req" is on the wrong type
of
object. Please see the "Attributes, Constraints, and Carry Logic"
section of
the Libraries Guide for more information on this attribute.

What does this mean? I have tried looking up the Libraries Guide but
without success.

Thanks

 

[rickman]

Leon Heller wrote:

"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F0C25FB.7BC1C0C9@yahoo.com...
Falk Brunner wrote:

"rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag
news:3F0AE7CC.68F9D9D0@yahoo.com...

I have been trying to get the Quartus 3.0 software and a license since
last Thursday. I tried three times over the weekend to download it,
but
the slow modem link I have to use would not complete the entire
transfer
without a problem. I think I have that licked as my brother tells me
he
has downloaded it for me.

Get a download manager like Gozilla or something. The can resume a
aboarded
download.

My concern is that once installed, I will have no way to control it if I
don't want to use it for some files. I remember Netscape adding
something like this (or I added some download, I can't remember which).
There were times I did not want it to pop up and could not find a way to
turn it off. It also showed ads while running.

Anyone know of a review of download utilities that would help me pick
one?

I've tried two or three and now use Download Accelerator Plus.

Thanks, I'll look at it.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Aurelian Lazarut]

Udayan,
Maybe you should try a different approach, like: state machine, with the
running CLK some times faster than you fastest input signal, and be
careful to add 2 (3) registers in the pipe for the inputs.
only an idea... (depending how fast you want/need to sample)

Aurash

Udayan wrote:

Hi,

I am having trouble with the GCLK feature in my design.

Basically my code is a 4 way handshaking protocol between my PC and
the FPGA on one hand and another 4 way handshaking with an
asynchronous chip on the other.

I am providing a clock to the system through the GCLK0 pin using an
oscilltor.

I further require edge tests on three lines that I receive from the
computer and the chip - which means they are inferred as clock
signals.

A total of 4 clocks.

However when I try to implement the design the engine complains that
my design is too large

Number of GCLKs: 6 out of 4 150%
Number of GCLKIOBs: 1 out of 4 25%

I cannot understand why this is so. I take the input from my CLKIOB
and pass it through a clock divide routine that I wrote and use that
signal as my global clock. The rest of the three lines go through
BUFGs befor entering the design.
I would loke to pass my divided clock through a BUFG so that it does
not suffer from skew.

To see what the problem might be I implemented another design which
has only one clock - the global clock that I divide and pass through a
BUFG but still the engine reports

Number of GCLKs: 3 out of 4 75%
Number of GCLKIOBs: 1 out of 4 25%

I was not clear on how this inference is taking place - possibly
because of IOB placements that are hardwired and result from clock
test or bad clock management.

Could someone advice on how to remedy the situation. Would a Clkdll
help? I am not very clear on how it will solve the problem with the
multiple clock lines or even how it broadly works.

Thanks

Udayan

--

 

[Leon Heller]

"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F0C25FB.7BC1C0C9@yahoo.com...

Falk Brunner wrote:

"rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag
news:3F0AE7CC.68F9D9D0@yahoo.com...

I have been trying to get the Quartus 3.0 software and a license since
last Thursday. I tried three times over the weekend to download it,
but
the slow modem link I have to use would not complete the entire
transfer
without a problem. I think I have that licked as my brother tells me
he
has downloaded it for me.

Get a download manager like Gozilla or something. The can resume a
aboarded
download.

My concern is that once installed, I will have no way to control it if I
don't want to use it for some files. I remember Netscape adding
something like this (or I added some download, I can't remember which).
There were times I did not want it to pop up and could not find a way to
turn it off. It also showed ads while running.

Anyone know of a review of download utilities that would help me pick
one?

I've tried two or three and now use Download Accelerator Plus.

Leon
--
Leon Heller, G1HSM
leon_heller@hotmail.com
http://www.geocities.com/leon_heller

 

[Uwe Bonnes]

Udayan <udayan@jhu.edu> wrote:
....
: SO I checked my design and removed the extra BUFG that was getting
: tagged to my divided clock output. However, since I would like to
: buffer my divided clock and the Synthesis engine automatically
: attaches a BUFG to the GCLKIOB pin input I am still left with one
: extra GCLK in my design being used up. Is there some way to get around
: that?

Can't you use a Clock Enable and the original clock instead of the divided
clock?

: Would a divide using the clk_dll still use up the extra GCLK
: resource?

The DLL output will use a GCLK too, to my knowledge.

: Also when I do an edge test with my signal lines that arrive at
: regular IOBs and pass them through a BUFG the MAP report gives a
: warning that:

: WARNING:NgdBuild:483 - Attribute "LOC" on "c_req" is on the wrong type
: of
: object. Please see the "Attributes, Constraints, and Carry Logic"
: section of
: the Libraries Guide for more information on this attribute.

: What does this mean? I have tried looking up the Libraries Guide but
: without success.

Perhaps you have an Output pin on a dedicated input or such. Recheck with
the data sheet.

Bye

--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------