EDK : FSL macros defined by Xilinx are wrong

so good that Xilinx sent you the example
i'm interested in it, can u send me (email: h0013252@eee.hku.hk) a copy ?

i'm now finding out how to build (glue all the IP cores needed) an embedded
system environment for the MontaVista Linx (Pro 3.0) to work on, do you
know any reference about that (so as to build an embedded Linux similar
to the one on ML300) ?


I can ping from ml300/linux, start FTP to location outside our network
but thats not very comfortable using commandline ftp on ml300 and 3rd
party ftp server as intermediate mailbox to copy files is not fun.
for my case, it's rather convenient for me, i just mount a network drive
from
other Linux PC on ML300/Linux

seems that thare are programs running under M$ Windows can access
Linux partition

but i will suggest you put the files in the FAT partition, then access the
files
in Linux by mounting the FAT partition (it's "/dev/xsysace/disc0/part1" in
my
case)

cheers,

tk


"Antti Lukats" <antti@case2000.com> wrote in message
news:80a3aea5.0307040614.743f3071@posting.google.com...
hi antti,

seems good for you : )

i just download compiled programs from a Linux PC to the ML300
(microdrive)
through network

i'm sure the built-in embedded Linux demo has full network support
just plug in the network cable and it will be ok !!


lucky you! there are no linux PCs in our office and a corporate router
may filter some stuff out, so plugging in, doesnt work 100%

I can ping from ml300/linux, start FTP to location outside our network
but thats not very comfortable using commandline ftp on ml300 and 3rd
party ftp server as intermediate mailbox to copy files is not fun.

our network gurus know almost nothing about linux etc, well work in
progress

what is good news that I did receive a working example for EDK incl

DDR (and ethernet) - so web server from that example does work and
I can access it from corporate network also.

too bad the microdrive linux partition is not accessible at all :(
it is there I know, 800MB are vanished (drive properties says 200MB
for 1GB microdrive)

tnx for help
antti
 
"juice28" <jstancliff@mchsi.com> wrote in message
news:GaZMa.29717$fG.15119@sccrnsc01...
Version 5.2 only works on windows 2000. I am using 3.2 as it seems to be
the only one that works on my setup. I have also assigned the input and
outputs to pins using the user constraints, but I did not use the ibuf and
obuf (it seemed to compile alright though) so maybe that is my problem.
Still wondering what is up with Q/ on the flip flops too.
You have to add an inverter.

Leon
--
Leon Heller, G1HSM
leon_heller@hotmail.com
http://www.geocities.com/leon_heller
 
A follow up:

Someone sent this solution to me and said it would provide no assymetrical
delays and would be better than a long elsif chain. Does anyone else have
any experience with this? It seems to me that a good fitter would render the
same solution.

Hi,

A clean way of doing this is:

CASE fastclkcnt IS
WHEN 2 =>
mrasnext <= '0';
mcasnext <= '1';
mwenext <= '0';
mdqmnext <= '1';
WHEN 4 =>
mrasnext <= '0';
mcasnext <= '1';
mwenext <= '0';
mdqmnext <= '1';
WHEN 12 =>
mrasnext <= '0';
mcasnext <= '1';
mwenext <= '0';
mdqmnext <= '1';
WHEN OTHERS =>
END CASE;

like this you make a decoder-mux arrangement
equal to all signals, so no strugle with assimetric
delays. (a long elseif chain is not a good solution).
 
Vaughn Betz <vbetz@altera.com> wrote:
Sander Vesik <sander@haldjas.folklore.ee> wrote in message news:<1054761767.988243@haldjas.folklore.ee>...
Anybody know of Cyclone EP1C12 (preferably) or EP1C20
(also ok) based PCI development boards? Do such things
even exist - or in other words, what is the approximate
timline after chip availability that one can expect such
to be around?

Altera will be shipping a Cyclone, 1C20-based PCI development kit
soon. Introduction is slated for late August. Cost will be under
$1000, and it will include DDR ram and be in a short board form
factor. Watch the Altera development kits page
(http://www.altera.com/products/devkits/kit-dev_platforms.jsp) for
details.
yay! cool! :cool: thanx.

--
Sander

+++ Out of cheese error +++
 
Followup to: <be2jpo$gtp$1@naig.caltech.edu>
By author: "Daniel Lang" <dblx@xtyrvos.caltech.edu>
In newsgroup: comp.arch.fpga
Hello,

NRZ (Non-Return to Zero) has only two signalling levels. NRZI is a
non-return to zero code where a 0 is represented by a transition in
the signal and a 1 is represented by no transition. Note that the
NRZ codes are not inherently self clocking, either an external clock
or some method of limiting the number of bit intervals with no
transitions is needed. See
My apologies; I was confusing it with AMI (Alternate Mark Inversion).

-hpa
--
<hpa@transmeta.com> at work, <hpa@zytor.com> in private!
"Unix gives you enough rope to shoot yourself in the foot."
Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64
 
Hi,
As I did have some strange experiences with SOPC_BUILDER that look like
a problem you actually have.
My first mistake was to place the SOPC_BUILDER at some place where it
would have make sence. Don't do that. Keep the suggested directory.
Second mistake was, I uninstalled the SOPC_BUILDER and reinstalled it to
different directories... There ist somewhere a file where the path to
SOPC_BUILDER must be set correctly. Unfortunatly I don't rember which
file it was.
Third mistake, Cygwin was not installed. There is an cygwin enviroment
delivered with SOPC_BUILDER but it did not work for some reason on my
computer.
Fourth mistake, I did not install the perl program delivered with
cygwin. The one delivered with SOPC_BUILDER was not working.
Fifth mistake, when installing cygwin, always select that your files are
in DOS LF mode. Otherwise you'll get compilation errors... I did get
them anyway but that's a different story.
Last hint, make sure your enviroment variables are all correctly set.

Good luck,
Karsten
 
Chris_S wrote:
Looking at the Lattice parts, the Mach 4A3 or Mach 4000 would be
candidates. I like the 4000, but there is almost no stock in the supply
chain yet. Arrow has only a couple parts moving and Avnet has virtually
none. Does not seem to have many designs going with it yet.

Another problem with the 4000 is lack of packages. I really need a PQ208
but there are none in the 4000 at all. Very few choices and little or no
stock even on those.

The 4A3 is a possibility. There are 10 times as many parts moving through
the dists and the family has 8 different devices with lots of packages. But
the Icc is much higher on that series than the 4000. The factory tells me
that the 4000 will be more expensive than the 4A as well.

I guess if you want to design for the long term future it's probably best to
pick a new family like the 4000. But you never know until later if that new
family makes it or not in the market.
Exactly which new families did not "make it" in the market? I don't see
any reason to expect the LC4000 (which is what I believe you are calling
Mach 4000) will not be here as long as any other PLD family. This is a
sound part and has some very good features. As to price, I have gotten
much better pricing on the Lattice parts than I have on the Xilinx CR
ones. Once the size gets up a bit, the CR parts get very, very
expensive.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
rickman wrote:
Jim Granville wrote:

Not entirely - the new Lattice devices offer 5V tolerance, but they
also spec 'no more than 32 IO' at a time.
Strange spec, how does one IO 'know' the state of another ?!

That is 64 IOs at once and each one sinks current. Seems the total
current sets the limit. I tried to get more detail on this to find a
way to use it with the PC/104 bus, but they kept telling me to consider
a different family.
snip

Where did you find the sink current info/value - from the FAE ?

I get this info from their Data:

#5. Maximum of 64 I/Os per device with VIN > 3.6V is allowed.
#
#IIH 2 Input High Leakage Current
# 3.6V < VIN = 5.5V, Tj = 105°C <= 20 ľA
# 3.6V < VIN = 5.5V, Tj = 130°C <= 50 ľA

So that does not look to me like a clamping diode, which is how
some others get their '5V tolerance' (just add a resistor :)

Still leaves open the question of why a finite limit on the
NUMBER of IO's that can have > 3.6V applied.

It sounds tempting to get a device, and take 65 IO's to > 3.6V, and
watch what happens :))

-jg
 
"tk" <tokwok@hotmail.com> wrote in message news:<be454t$62s$1@www.csis.hku.hk>...
so good that Xilinx sent you the example
i'm interested in it, can u send me (email: h0013252@eee.hku.hk) a copy ?
I will forward your request to the person I got it from (at least)

i'm now finding out how to build (glue all the IP cores needed) an embedded
system environment for the MontaVista Linx (Pro 3.0) to work on, do you
know any reference about that (so as to build an embedded Linux similar
to the one on ML300) ?
just ask (again) xilinx support, there have been promises that a EDK 3.2
project capable to boot linux will be made available, maybe its wiser to
wait :)

FYI I glued the obsoleted (in EDK) LCD TFT core to the DDR example and
well I think I get it working well I had wrong clock (100MHz!) , wrong
start address (0) and wasnt yet able to compile use the tft library,
but after fixinf those problems I think it does work - with memory
test i did see 'visual picture of memory fill' :)

in Linux by mounting the FAT partition (it's "/dev/xsysace/disc0/part1" in
tnx, it would have taken me long tofigure this out !!!!
 
Steven K. Knapp <steve.knappNO#SPAM@xilinx.com> wrote:
For high-performance applications, you would want to use two outputs from
the Digital Clock Manager, one being the de-skewed, non-shifted clock output
and the de-skewed, 180 degrees phase-shifted clock output. This technique
minimizes any potential duty-cycle distortion and gives you most of the
entire half-period for your logic application.
.... but takes twice as many BUFGs.

Feature request: more BUFGs.

Grip: differential clocks take two global clock pins. It would be better
if they took one global clock pin and the other pin in the differential
pair was a standard I/O pin. I don't know if that is feasible, but
differential clocks chew IBUFGs quickly.

On the project I'm currently working on we ran out of global clock pins
this way and put one of our clocks on a non-global pin. Works fine.
Our experience shows that it's preferable to have differential clocks
even on non-clock pins than to use single-ended clocks.


Hamish
--
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>
 
Jim Granville wrote:
rickman wrote:

Jim Granville wrote:

Not entirely - the new Lattice devices offer 5V tolerance, but they
also spec 'no more than 32 IO' at a time.
Strange spec, how does one IO 'know' the state of another ?!

That is 64 IOs at once and each one sinks current. Seems the total
current sets the limit. I tried to get more detail on this to find a
way to use it with the PC/104 bus, but they kept telling me to consider
a different family.
snip

Where did you find the sink current info/value - from the FAE ?

I get this info from their Data:

#5. Maximum of 64 I/Os per device with VIN > 3.6V is allowed.
#
#IIH 2 Input High Leakage Current
# 3.6V < VIN = 5.5V, Tj = 105°C <= 20 ľA
# 3.6V < VIN = 5.5V, Tj = 130°C <= 50 ľA

So that does not look to me like a clamping diode, which is how
some others get their '5V tolerance' (just add a resistor :)

Still leaves open the question of why a finite limit on the
NUMBER of IO's that can have > 3.6V applied.

It sounds tempting to get a device, and take 65 IO's to > 3.6V, and
watch what happens :))
I was told this by both an FAE and support by email. I am sure both are
just parroting whatever is the original source of the info. I could not
get them to give me any more detail, such as what effect a series
resistance or other source impedance would have on the spec.


From the FAE...
"You are correct, the 5512MB does have a limit of 64 IOs that can be
driven above 3.6V. This is due to the leakage current that appears when
an input is biased above VCCio. They need to keep the total amount of
this leakage current below a certain number and that worked out to 64
IOs."

From support...
"The 64 IOs 5V restriction is a reliability requirement for EE9
technology to ensure that we meet oxide FIT rate requirement."


You could do your own testing on a device, but how would you know that
this will be consistant across future versions of the device? It is not
at all uncommon for a company to alter their process while keeping the
original published spec. Xilinx has discussed this recently on the
SpartanXL. While they maintained all the publised specs (and improved
some), anything that you have tested in the past may no longer function
that way.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
rickman wrote:
Jim Granville wrote:

rickman wrote:

Jim Granville wrote:

Not entirely - the new Lattice devices offer 5V tolerance, but they
also spec 'no more than 32 IO' at a time.
Strange spec, how does one IO 'know' the state of another ?!

That is 64 IOs at once and each one sinks current. Seems the total
current sets the limit. I tried to get more detail on this to find a
way to use it with the PC/104 bus, but they kept telling me to consider
a different family.
snip

Where did you find the sink current info/value - from the FAE ?

I get this info from their Data:

#5. Maximum of 64 I/Os per device with VIN > 3.6V is allowed.
#
#IIH 2 Input High Leakage Current
# 3.6V < VIN = 5.5V, Tj = 105°C <= 20 ľA
# 3.6V < VIN = 5.5V, Tj = 130°C <= 50 ľA

So that does not look to me like a clamping diode, which is how
some others get their '5V tolerance' (just add a resistor :)

Still leaves open the question of why a finite limit on the
NUMBER of IO's that can have > 3.6V applied.

It sounds tempting to get a device, and take 65 IO's to > 3.6V, and
watch what happens :))

I was told this by both an FAE and support by email. I am sure both are
just parroting whatever is the original source of the info. I could not
get them to give me any more detail, such as what effect a series
resistance or other source impedance would have on the spec.

From the FAE...
"You are correct, the 5512MB does have a limit of 64 IOs that can be
driven above 3.6V. This is due to the leakage current that appears when
an input is biased above VCCio. They need to keep the total amount of
this leakage current below a certain number and that worked out to 64
IOs."

From support...
"The 64 IOs 5V restriction is a reliability requirement for EE9
technology to ensure that we meet oxide FIT rate requirement."

snip

Thanks - Now, that support reply makes sense, the first one is a
mangled version of the second one.

If it is actually an oxide stress FIT parameter, then the 64 is an
arbitary
number, and failures are related to IP * Time products.
The Oxide stress FIT of a single IP is finite, with more IPs you just
ramp
the statistical chances of ONE having a failure.

It would be nice if they published more info on this, like the
voltage/FIT slope, and just what the actual FIT value is, so
in design you can decide on additional clamping, or if other measures
are needed.

There are processs where the gate-oxide thickness can be varied across
the
die ( and even thresholds, within a gate oxide ),
but perhaps they have not made it to PLDs yet ?

-jg
 
"Josh Model" <model@ll.mit.edu> wrote in message news:<hr4Fa.51$Du1.40@llnews.ll.mit.edu>...
Hi all,

Sorry to echo the common call on this group, but I've added a little twist.
I was looking for FPGA prototype boards that fit the PC/104 form factor and
standard. I've checked out the optimagic site, but most of the companies
listed there either don't the newer fpga's. Closest I came was Nova
Engineering's Altera boards, but Xilinx is much more in my comfort zone.

Any suggestions? Thanks.

--Josh Model
MIT/LL
Check out Jacyl Technology at www.jacyltechnology.com. There is a
Xilinx CPLD based PC104 board (RP-3200) and we have a Spartan IIe 300K
PC104 comming out in the next month (XG-300K).
 
Hey Rickman,

In article <3F0AE7CC.68F9D9D0@yahoo.com>, spamgoeshere4@yahoo.com
says...
I need to vent a little steam. So at risk of making myself look stupid
(or more stupid) I will do it here.

I have been trying to get the Quartus 3.0 software and a license since
last Thursday. I tried three times over the weekend to download it, but
the slow modem link I have to use would not complete the entire transfer
without a problem. I think I have that licked as my brother tells me he
has downloaded it for me.
You might want to look into a *great* utility called "wget".

It's probably comes standard on every modern FreeBSD/Linux
implementation, but not many people in the Windows world know about
it...

See this for a command-line vanilla Windows version:

http://space.tin.it/computer/hherold/

and see this for a Visual Basic GUI wrap-around:

http://www.jensroesner.de/wgetgui/

If you use the plain-vanilla command-line version, just launch like
this:

wget -c <url>

-c tells it to continue if a download is aborted...this way if your
modem drops, when you re-connect, just re-issue wget -c <url> and it'll
continue where the file was chopped off.

Also, as other people have suggested, the path of least resistance
really is to get an el-cheapo NIC and stick it in. It's not elegant,
it's not "right" but it's the fastest way to get what you want.

Thanks!
TR.
 
"rickman" <spamgoeshere4@yahoo.com> wrote in message

<SNIP>
I am not looking for champagne on a beer budget, but I would sure like
to be able to pour them both into the same glass.
Isn't that a bit of redneck perspective -champagne in Budweiser glass ? ;o)
 
Geeze .... I'm glad altera doesn't waste valuable time on your problem
, they have real work to do. They have standardized on the ethernet
interface, if you have a desktop spend $15 and buy one, if you have a
laptop without one you may have to spend twice that on a USB version
or something. You must have lots of time and little work.




On Tue, 08 Jul 2003 11:48:28 -0400, rickman <spamgoeshere4@yahoo.com>
wrote:

I need to vent a little steam. So at risk of making myself look stupid
(or more stupid) I will do it here.

I have been trying to get the Quartus 3.0 software and a license since
last Thursday. I tried three times over the weekend to download it, but
the slow modem link I have to use would not complete the entire transfer
without a problem. I think I have that licked as my brother tells me he
has downloaded it for me.

But I have been trying to get a license file that does not require an
Ethernet interface and am getting nowhere. I have received several
emails from Altera people who say that they support this and I need to
contact my local FAE or the main office. I have tried to do both. All
of the FAEs I know are either on vacation or in California at training.
Calling both 800 numbers has gotten me nowhere since I reach people who
are the "first line" and always have to refer it to someone else. I
have left about half a dozen voice mails, sent easily a dozen emails,
spoken with two types of support and still I have not heard back from
anyone at Altera about this.

Right now I have been holding for about 15 minutes waiting for a third
number to connect me with a person. I know that if I was this hard to
get ahold of no one would *ever* buy any of my products!

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
"rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag
news:3F0AE7CC.68F9D9D0@yahoo.com...

I have been trying to get the Quartus 3.0 software and a license since
last Thursday. I tried three times over the weekend to download it, but
the slow modem link I have to use would not complete the entire transfer
without a problem. I think I have that licked as my brother tells me he
has downloaded it for me.
Get a download manager like Gozilla or something. The can resume a aboarded
download.

--
Regards
Falk
 
You didn't mention the radix of each stage. Divide by 4 is too much if
it is a radix2 butterfly. If it is radix 2, the gain is at most 2, not
4. The max output from an FFT occurs when all the input energy falls
into one output bin, which implies the input is a pure sinusoid with a
frequency that is an integer multiple of the sample time. If the input
is white noise, the output signal energy is going to be spread evenly
among all the output bins, in effect dividing the input signal by N. As
you can see, this results in a fairly wide dynamic range. If you know
the nature of your input, you can scale accordingly. If not, you need
to either carry extra bits or you can use dynamic scaling such as a
block floating point scheme.

Bob wrote:

Hello,

I have constructed a 256 pt complex fft. My scaling is causing
problems as the outputs from each stage are divided by 4 to avoid
overflow. The input data and the twiddle factor coeffs are 16 bits
wide (Q15). My problem is that when the data arrives at the last two
butterfly stages of the FFT, it is non-existant, due to all the
scaling beforehand. All inputs to these stages are zero. Thus I get
nothing at the output.

How can I work around this?

Many thanks

Bob
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
 
Udayan <udayan@jhu.edu> wrote:
: Hi,

: I am having trouble with the GCLK feature in my design.

: Basically my code is a 4 way handshaking protocol between my PC and
: the FPGA on one hand and another 4 way handshaking with an
: asynchronous chip on the other.

: I am providing a clock to the system through the GCLK0 pin using an
: oscilltor.

: I further require edge tests on three lines that I receive from the
: computer and the chip - which means they are inferred as clock
: signals.

: A total of 4 clocks.

: However when I try to implement the design the engine complains that
: my design is too large

: Number of GCLKs: 6 out of 4 150%
: Number of GCLKIOBs: 1 out of 4 25%

: I cannot understand why this is so. I take the input from my CLKIOB

Look at the synthesis report (*.syr) and at the graphical representation of
your circuit ("View RTL Schematics"). It will give you a glimpse of what is
going on. Then rethink the way you wrote your HDL implementation. In the
synthesis report, the "Clock information" might be the most important
thingto look at.

Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
 
This is an FPGA question; I removed comp.lang.vhdl from this followup.

If you put your clock signal on a GCK pin, and ISE recognizes it as a
clock signal, the GBUF gets added automatically. (ISE adds a GBUF to
almost everything it recognizes as a clock)

At 30 MHz, the only constraints you will (probably) need is to lock
down the pin numbers.

Typically, the 2nd constrain you add is the clock speed (the 1st being
the pinout). Other constraints are added to help the software meet
the speed constraint. (pre-assigning locations, that kind of stuff)

Hope that helps,
SH7


On Thu, 3 Jul 2003 22:13:22 -0400, "Jason Berringer"
<look_at_bottom_of@email.com> wrote:

Hello all,

I would like to know a couple of things if anyone could help or point me to
a file etc. I'm using Webpack from Xilinx, and a Spartan XC2S100 and I've
been messing around with writing simple project to get familiar with VHDL
and programming the board. I'm curious to know if I have to instantiate a
global clock buffer each time I sythesis my design, or if I simply make sure
that my clock goes to a GCK pin is that enough? Also I'm a little confused
as to what constraints are and how they might help my designs. For example
if I have a 30 MHz clock going to a GCK pin do I have to put constraints on
it or are constraints primarily used for very complex designs?

Sorry if this seems like small question, but it is somewhat confusing from
the documents that I have read, and since I haven't had any problems with
any of my projects (without using any constraints) I was not all that
worried. Now that I'm getting into bigger designs I figured that it was time
to start figuring this out.

Any and all help is greatly appreciated.

Thanks

Jason
 

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