EDK : FSL macros defined by Xilinx are wrong

[Jim Granville]

Steven K. Knapp wrote:

"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F00FDD2.C74022BD@yahoo.com...
"Nicholas C. Weaver" wrote:
That is a good point about the tools. I forget that the XC3S is only
supported in webpack in the XC3S50 now and I think only up to the
XC3S400 in the next release. I honestly don't get the idea of selling
very low cost chips and not adding them to the free tools.

Personally, I agree with your statement and have been trying to convince the
powers that be to add additional Spartan-3 devices to WebPack. The folks
responsible for WebPack are concerned about the total download size. The
larger devices have multi-MB support files.

You could always shock them with the 'left field' concept of selective
downloading just the device library files you need ?

-jg

 

[rickman]

Peter Alfke wrote:

rickman wrote:


Except that I often am contacted by Altera directly rather than here in
public. I can understand why they would do that.

I cannot understand that at all. If the question is ventilated in
public, it should be answered in public. Unless the answer is very embarrassing...

Peter Alfke, Xilinx

Often vendors don't want to seem like they are hawking their wares
here. So I see nothing wrong with contact on a more personal level in
order to get a good answer to a question. When your sales people make
calls on customers, they don't invite the competition to come along do
they? Support is no different. Why should the open the door for
kibitzing from the competition? And maybe they will be revealing some
information that they don't want the competition to have. I know that
Xilinx has been pretty tightlipped about their product schedules. At
least I have had a very hard time getting that info until a couple of
weeks ago when I insisted that I needed it on the Spartan 3s.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[rickman]

Luiz Carlos wrote:

You can feel how you wish about your designs, but even the loss of the
64 bit dual ports and the 128 bit single port rams is not signficant.
To make a 64 bit dual port RAM requires 8 LUTs for ram (same as in VII)
and one LUT for the read mux and possibly two more LUTs for the WEs.
But if this is part of a larger ram block you are making half of the WEs
would have been required anyway. So it is not a "large" amount of
logic, just a bit more.

Ok, I agree with you, it´s not to much logic. But because these extra
delays maybe I have to duplicate the circuits.

If you are making really large blocks where the longer runs on the
address and data can slow it down significantly, then you likely are
better off with the block rams.

No, they are not large blocks, but I have 128 to 512 FIR filters (256
coefs) running in parallel, and the sampling rate is 2 megaHertz.
Throughput!

Considering the much lower price of the XC3S parts, all this sounds to
me like a benefit, not a liability. Think of it as paying for the LUTs
that have RAM and getting the other LUTs for free

I'm not complaining, and I know that Xilinx wil not make a special
Spartan3 just for me. But I have the right to express what I think,
and maybe I'm not alone. Maybe there are a lot of Luizes and Rays,
maybe Xilinx will hear us and maybe, at these nanometer scales where
the pads are so big, to have all the CLBs configurable as memory is
not so significant in silicon area.

Yes, certainly you have the right to express your views and to let
Xilinx know what you need. But I think you are responding to the idea
that "something" is missing without knowing for sure if it is really an
issue. When you say above that adding the level of logic may slow down
the design, you first need to know how fast these parts run. After all,
you are comparing 90 nm Spartan 3s to 150 nm VirtexIIs. It is very
possible that the S3s will run faster even with the added delays.

I am sorry if my "nagging" is annoying. But I have watched a lot of
changes in FPGAs and have often felt they were not for the better. But
somewhere around the Virtex or VirtexII parts I started to realize that
I needed to forget about how the parts were different and focus on how
to solve my design problems using them. With that I have come to
understand that often what I saw as a limitation is more than made up
for in other areas. I am sure that Xilinx does not remove functionality
without considering the trade offs very seriously.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[rickman]

Peter Alfke wrote:

Xilinx has two major product lines. Virtex is for performance and
features, Spartan is for low cost. Otherwise, the architectures are very similar.

That gives us a chance to really optimize each line. The Spartan
developers reduce the cost, accepting that this makes their devices
non-optimal for certain applications, but there is always Virtex to
deliver higher functionality and performance (at a higher price).
The Virtex designers can optimize functionality and speed, knowing that
this might increase the cost, but there is always Spartan to satisfy
less performance-critical, but more cost-sensitive applications.

There is no free lunch, in engineering almost everything is a trade-off.
But everybody still asks for champagne on a beer budget
Peter Alfke

I am not looking for champagne on a beer budget, but I would sure like
to be able to pour them both into the same glass. That is I would like
to have one footprint that I an put a Spartan into for low cost or a
Virtex when I need high performance and large size.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[rickman]

"Steven K. Knapp" wrote:

"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F00FDD2.C74022BD@yahoo.com...
"Nicholas C. Weaver" wrote:
That is a good point about the tools. I forget that the XC3S is only
supported in webpack in the XC3S50 now and I think only up to the
XC3S400 in the next release. I honestly don't get the idea of selling
very low cost chips and not adding them to the free tools.

Personally, I agree with your statement and have been trying to convince the
powers that be to add additional Spartan-3 devices to WebPack. The folks
responsible for WebPack are concerned about the total download size. The
larger devices have multi-MB support files.

If the size of the download is the issue, there are very simple ways to
address that. One is to split the download into two parts, one for the
current configuration and one for the added support for the larger
devices. The other is just to ship the CD as you already do. I don't
think adding all the chips will blow away a CD will it? As it is, I
don't think it is very practical to ask a user to download a 150 MB
file. At least it is not practical for me to download it.

But good luck getting a price on the XC3S1000 at this point. The
XC3S1000 parts have been pushed back due to design problems and will not
be out until Q1 or perhaps later. The XC3S400 and one of the larger
parts will be out in 4Q03 according to their schedule.

Hmm. Engineering samples of the XC3S1000 and XC3S50 are available today.
The engineering samples have the part number XC3S1000J and XC3S50J to
distinguish them from the production devices. This may be the reason you
were quoted longer delivery. The non-'J' devices are due out in 4Q2003.
The non-'J' version of the XC3S50 also includes block RAM, embedded
multipliers, and 2 Digital Clock Managers (DCMs), which the XC3S50J does
not.

I have been told that the 50 and 1000 have a design problem with 3 volt
tolerance and have been pushed back from late Q3 or early Q4 to 1Q04.
The other two or three chips due out in Q4 (including the XC3S400) are
now the first chips to be available in full production.

I am having a lot of trouble getting straight information and this is
what I currently have in print! If this is not correct, I really need
to know now!

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Paul Leventis]

Hi Marc,

I love competitive comparisons, and I love Altera for continuing to
push the level of competition higher, but PLEASE, could you keep this
FUD free?

Interesting... I thought my posting was relatively FUD free. Have I have
been on the dark side for too long?

Xilinx tells everybody that the speed files that are released for the
Spartan-3 are very preliminary and quite conservative, and I'm sure
your tech people know that.

I am a tech person... I assure you that we're the last customer of ISE that
Xilinx cares to inform about future performance!

The software is the silicon -- it doesn't matter how fast the chip is if you
don't know how fast your design will run on it. I would be leary of relying
on a nebulous future performance improvement; I think the performance
reported *today* is very relevant for people making decisions today.
Besides, in postings to this newsgroup at least, Xilinx has indicated that
they sacked performance in order to reduce costs. So how conservative is
the timing? 5%? 10%? 100%? I don't know. Do you?

This is bordering on the same level of
FUD that I got from my Altera rep about some Virtex II availability or
yield or some such nonsense early this year.

Hmm... I'd go listen to some Xilinx conference calls from the same time
period, and look at recent dielectric decisions on VIIPro, and look at when
products shipped vs. dates indicated in announcements before proclaiming
that FUD.

All of these would be better talking points than some nebulous claim of
being
30% faster than a part that is nowhere near released and whose claimed
speed is known to be artificially low.

I guess it's not that fair for me to compare a released, available, fully
characterized product with a final timing model against a product that is
barely sampling. But that is what the original poster was asking for, and
that's all I can compare against. And the "nebulous" claim was 20% faster
(slowest Cyclone to only Spartan 3 speed grade), or ~55% for the fastest
Cyclone speed grade. These are not "up to" numbers -- they are geometric
averages over 50+ user designs.

Have yourself a great long weekend,

Paul Leventis
Altera Corp.

 

[Greg Steinke]

Rick,
On your question on startup current - I don't know this offhand but
will track this down with the hotline guy, as we don't want to
duplicate effort.

The other question about quiescent current:
Your interpretation is correct. The 5 mA value applies to -2 and -3
commercial-temp devices and -3 industrial/extended-temp devices, while
the 10 mA value applies to -1 commercial-temp devices and -2, -3
industrial/extended-temp devices. The spec applies to a configured
part with no toggling inputs. We do not have a spec for the
unconfigured part. In reality it may be slightly higher, but not much
more.

Greg Steinke
Altera Applications
gregs@altera.com


rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F047811.D824824C@yahoo.com>...

Since Altera seems to be active in this group, I will ask the question
here. I have finally gotten an acceptable price on the EP1K30 part (5
volt tolerant) and will be using it in my design provided I don't step
on any landmines looking at the data sheet in fine detail. One item
that is missing is the startup current. I called support and got a
number of 194 mA. But I asked if this was over temp and voltage and he
didn't know. He said he would dig up the answer and get back to me
which never happened.

So who can tell me the power-up current for the EP1K10, EP1K30, EP1K50
and EP1K100 in both commercial and industrial temp grade over
temperature and voltage?

Also, I am not certain I understand the quiescent current spec on this
part. There are two values, one has a footnote...

ICC0 VCC supply current (standby)

(12) This parameter applies to -1 speed grade commercial temperature
devices and -2 speed grade industrial and extended temperature devices.

Does this mean the lower value (5 mA) without the footnote applies to
all other devices?

Am I correct in assuming that this spec is for a configured part with no
clock as well as an unconfigured part?

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Jim Granville]

Chris_S wrote:
<snip>

The Altera people told me that a new CPLD family is coming out soon. It
will be lower power. Sounds like Altera has gotten very sick of hearing
their parts are current hogs.

Can they elaborate on the 'out soon', in this industry, that can reach
to the end of 2004

Xilinx says that they also have a new CR (2.5V) part coming out, but it will
probably replace the XC2 line, not XPLA3. They say XPLA3 is not going to be
obsolete.

This sounds a little mangled, and someone from Xilinx may enlighten us.
It may be that the 'new' CoolRunner is the XC2 family ?

The XC2 is so new, only the XC2C256 gives web supply hits.

Once released, a device will only go obsolete if volumes get too small,
or the FAB line closes. The latter happened to Lattice and Xilinx, but
only affected design lines they purchased.

-jg

 

[Jim Granville]

rickman wrote:

Chris_S wrote:
snip> > The Altera people told me that a new CPLD family is coming out

soon. It

will be lower power. Sounds like Altera has gotten very sick of hearing
their parts are current hogs.

Did they give you a schedule by any chance? If they don't have a
schedule then you shouldn't expect it within the year. Oh, yeah, don't
expect it to be 5 volt tolerant. If you only need LVTTL, then you
should be ok, but all newer devices are 5 volt phobic.

Not entirely - the new Lattice devices offer 5V tolerance, but they
also spec 'no more than 32 IO' at a time.
Strange spec, how does one IO 'know' the state of another ?!

On some devices the IO tolerance is spec'd also CORE relative, so
you can get caught if your IO power is present, and the core
voltage is not!

Lattice appear to be using on-chip regulators, so the multi-rail dance
is showing signs of simplifying. The regulator is a bit 'ordinary', so
the
Icc goes up on those variants.
There are uC being released with regulated core voltages (eg
AT89C51ED2)
so that is a sensible solution, esp for the smaller CPLD's

-jg

 

[Daniel Lang]

Hello,

NRZ (Non-Return to Zero) has only two signalling levels. NRZI is a
non-return to zero code where a 0 is represented by a transition in
the signal and a 1 is represented by no transition. Note that the
NRZ codes are not inherently self clocking, either an external clock
or some method of limiting the number of bit intervals with no
transitions is needed. See
http://wombat.doc.ic.ac.uk/foldoc/foldoc.cgi?Non+Return+To+Zero

Return to Zero (RZ)
http://wombat.doc.ic.ac.uk/foldoc/foldoc.cgi?Return+To+Zero
often used bipolar + and - voltages for 1 and 0, returning to zero volts
between bits (3 level signalling).

Daniel Lang

guest> wrote in message news:ee7e625.2@WebX.sUN8CHnE...
Dear Falk & Peter,
Thanks for replying, As Iam basic to this information, Please correct me
if iam wromg
NRZ coding say it doesn't return to 0v. For transmitting '1' +V is used
and for transmitting '0' -V volt is used.
we have signalling standards like LVTTL, TTL, CMOS they represent '1' as +V
and '0' as 0V .
What do i say the chip, which provides the NRZ interface,
1) Its signalling varies from +v to -v doesn't return to 0V
2) Or it has used NRZ coding over Some (say CMOS) signalling standard
then one is represented by + Vdd and zero is represented by 0V, am I

wright..?

3) what is NRZ, is it not an line coding, i.e how to represent the 1 and 0
across the physical link ?
Thanks in Advance

 

[Jay]

You mean the warning is a suggestion for the simulation process.
and nothing wrong with the model ISE generated.

"Sandeep Kulkarni" <sandeep@insight.memec.co.in> Đ´ČëĎűϢĐÂÎĹ
:be15fd$27q4$1@ID-199516.news.dfncis.de...

Hello,
The "glbl.v" module connects the global signals to the design, which makes
it necessary to compile this module with the other design files and to
load
it along with the "toplevel.v" file or the "testbench.v" file for
simulation.

You need to compile it in the simulator, with the timing netlist.

Sandeep
"Jay" <yuhaiwen@hotmail.com> wrote in message
news:be0h4j$117mq8$1@ID-195883.news.dfncis.de...
in ISE project navigator, when I run the 'generate post-PAR simulation
model' process, I get a warning below:

WARNING:NetListWriters:108 - In order to compile this verilog file
successfully, please add $XILINX/verilog/src/glbl.v to your compile
command.

I'm using a GUI software, how can I change its default command line
under
the button?

 

[Jay]

Really good idea.
but it can't cover all the situation, when I want to divide the clock by 4,
8...
maybe use glbl.GSR is a common solution.
"jetmarc" <jetmarc@hotmail.com>
??????:af3f5bb5.0307021455.6db3d07e@posting.google.com...

I know the reason. without a reset signal to give it a initial value of
'0'
or '1', the clkout will keep the value 'x' during simulation.

In VHDL you can write:

process (clkin)
begin
if rising_edge(clkin) then
if clkout='0' then
clkout <= '1';
else
clkout <= '0';
end if;
end if;
end process;

That works both in the chip, and in the simulator. The trick is that
the ELSE statement covers both '1' and 'x'.

Marc

 

[Bill]

Lasse Langwadt Christensen <langwadt@ieee.org> wrote in message news:<3F0371D7.30906@ieee.org>...

Bill wrote:
"Leon Heller" <leon_heller@hotmail.com> wrote in message news:<bdv712$oki$1@hercules.btinternet.com>...

eholbrook@austin.rr.com> wrote in message
news:874r24dalp.fsf@vole.holby-net...

I'm looking for a DIMM format FPGA board like Pilchard or the AcB from
(now defunct?) Nuron. I've done several web searches, but found
nothing that both fits the bill, and is from a company that is
apparently alive. I've found a couple of things that are close to what
i want (from mite.cz, and sunrise-systems.de), but they don't return
emails, so i figure they're dead, too.

Has anyone heard of something like this, or do i need to design/build
it myself?

I was thinking of developing one. How about us collaborating?

Leon



From what I hear, SRC Computers holds patents in this area and is not
licensing to anyone right now.

www.srccomp.com

What!

maybe I read it too fast maybe I just can't read patents or maybe
I just don't understand, but don't they basically claim that they
have patented programble logic memory mapped on a microprocessor?

I would have guessed that that is widely used and has been for some
time

-Lasse

I think your reading it right, I would have thought it was widely used as well.

 

[Yu Haiwen]

"John_H" <johnhandwork@mail.com> wrote in message news:<1GEKa.20$%E1.13818@news-west.eli.net>...

"Jay" <yuhaiwen@hotmail.com> wrote in message
news:bde3rr$rs8gp$1@ID-195883.news.dfncis.de...
snip
How can I simulate this modules? in testbench I tried to initiate the
clkout, but failed.
/snip

If you're doing RTL simulation from your original code, you need to
initialize all your variables for simulation such as

initial
mydesign.clkout <= 1'b0;

Alternatively, post place and route simulation can give you proper
initializations as long as you bring out the global set/reset signal (.GSR)
when generating the verilog file from the Xilinx tool. Then, the "initial"
block doesn't initialize the individual RTL registers but is used to drive
the .GSR for a short time at the start of the simulation, initializing all
the register primitives to the power-on values. I don't recall if memories
still need manual initialization or not (since they aren't cleared by a
reset but are loaded with the programming file).

The advantage to post place and route simulation is that some of your
registers may power up logic high (when an FDS or FDSE primitive is used to
implement the synthesized logic) and an incorrect initial state can alter
your device's performance.

I change the code to
reg clkout;
wire GSR;

always@(posedge clkin)
begin
if(GSR == 1)
clkout <= 0;
else
clkout <= ~clkout;
end

thus in testbench I can give the clkout a initial value.
the simulation can work now.

but I still a little confuse about what you say:
the .GSR can "initializing all the register primitives to the power-on values."
how can it achieve this?
Do I miss someting important?

 

[Antti Lukats]

Thanks Peter,

and sorry xilinx, affiliates, etc, my first comments on ml300,
well I am little to fast to get critical when things dont work.

I found some linux stuff (.h files, .so files, python, etc) still looking
for the c compiler, (on the microdrive).

if the EDK 'obsoleted' TFT is 'supposed' to work, I will give it a try.
no problems.

and montavista, guess it makes sense to ask for ver 3.0
ml300 microdrive has 2.1 Professional installed.

thanks,
and I do my homework better now
e.g. when attempt to start c compiler on linux I will not yiell
that C compiler isnt there (in 5 minutes) but keep searching
for the compiler. ok, search is in progress


Peter Ryser <ryserp@xilinx.com> wrote in message news:<3F036954.D30250BE@xilinx.com>...

Antti,

the Linux demo shipping with ML300 comes with X Windows and a ton of servers
and applications. If for some reason your board came with just a very simple
command line version of Linux you can get the full MicroDrive image from the
ML300 lounge accessible from http://www.xilinx.com/ml300.

If you want to start your own development with Linux on Virtex-II Pro please
contact MontaVista and ask them for MontaVista Linux 3.0 for ML300. They will
be able to give you more information on the content and the pricing of their
product.

V2PDK is still supported by Xilinx. However, it is in the process of being
replaced with EDK. The V2PDK design for the ML300 is currently ported over to
V2PDK and you should be able to download it from the ML300 lounge in the near
future. A first version of the port will not support all peripherals that
have been available in V2PDK but will give enough functionality to boot
Linux.

The TFT in EDK works as it is the same as in V2PDK.

 

[tk]

hi antti,

seems good for you : )

i just download compiled programs from a Linux PC to the ML300 (microdrive)
through network

i'm sure the built-in embedded Linux demo has full network support
just plug in the network cable and it will be ok !!

cheers,

tk

"Antti Lukats" <antti@case2000.com> wrote in message
news:80a3aea5.0307040020.222ea437@posting.google.com...

"tk" <tokwok@hotmail.com> wrote in message
news:<be09aq$804$1@hkueee5.eee.hku.hk>...
Hi,

I've written a very simple application (hello world for the Linux in
ML300 using
ELDK's ppc_4xx cross compiler.

http://lists.linuxppc.org/linuxppc-embedded/200305/msg00033.html

I think it will be great if Xilinx can issuse some reference about how
the
Linux demonstrating platform can be built. It will be useful for
building
a customerized embedded Linux platform.

hi tk,

well xilinx just promised that an EDK project capable of minimal
linux boot will be made (available) - so at least there is hope.

I read your posting, but,,, I have no problems writing C programs
for ML300 and merging them with reference bitstreams, the results
also work

but to compile for the linux on microdrive, i would need to
1) get the header files
2) compile
3) copy the executable back
but the linux file system is so far unaccesible for me, eg
the microdrive seems to have hidden linux partition (not visible
on w2k host computer) and I havent managed to get the enet networking
so the microdrive linux works, but I have no means to get a compiled
program into it. ok, I need to plug in the network cable and see if
I get it running

antti

 

[Kari Runk]

Mark Sandford wrote:

Try http://www.Google.com

SP <nowhere@nowhere.com> wrote in message news:<Xns93ADB437CEF1nowherenowherecom@216.109.160.14>...

Hello,

I am looking for an ARM (preferably StrongARM) w/ FPGA development board.
StrongARM preference is for mainly for Linux. Any other supported processor
will do as well.

Thanks a lot!
-Sumeet

Take a look at Altera's Excalibur, it has ARM9 hard core + peripherals
and FPGA on the same die.

http://www.altera.com/products/devices/arm/kits/exc-dev_kits_boards.html

-KR-

 

[Manfred Kraus]

I got a call from Insight. Of course I can get samples of the ESJ-part
immediately.
The Problem was, that I didn't ask for ESJ-Parts. They assumed I know what
to ask for.

Thanks to Peter for clarifying this.

-Manfred Kraus

mkraus_at_cesys_dot_com

 

[Uwe Bonnes]

Manfred Kraus <news@cesys.com> wrote:
: I got a call from Insight. Of course I can get samples of the ESJ-part
: immediately.
: The Problem was, that I didn't ask for ESJ-Parts. They assumed I know what
: to ask for.

The problem is also, that distributors often ask for an exact number, while
the user mostly needs _any_ part with only few constraints. That way, you
have to prepare a lot of fallback fits, and ask the distributor for each.

If they could cope with wildcards in the part number, things would be
easier...

Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

 

[Rene Tschaggelar]

Rene Tschaggelar wrote:

There is no SOPCBuilder as it should be according to the pdf.
I browswed the SOPC Builder solutions in the knowledge base.

Thanks this far for the messages.

The SOPC builder appears to be correctly installed.
There is no java running, at least it was not detectable.
The is no other cygwin either.

From the taskmanager it appears the perl.exe is somehow failing.
It comes upon the SOPC button and goes right away.

Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net