EDK : FSL macros defined by Xilinx are wrong

"black" <mini_monkey@163.net> writes:

hi Jonathan Bromley:
The reason for using FPGA's dedicated clock distribution resources is
that there is no clock skew in these resources,is that right?

There is skew even in dedicated clock lines. Because clock nets are
dedicated for just for clock signals skew is much smaller and can
(more easily) be accounted for in place and route. Most FPGA tools
warn about gated clocks because then your skew is no longer well known
parameter of global clock net but depends heavily on your design.


--
Keijo Länsikunnas

 

[Luiz Carlos]

but these are SIMD, not-GP, registers.

As far as I know, its the same core of the Toshiba TX7901 micro
processor, and it has 32 (of course, it´s a MIPS) 128 bit registers,
although the two integer units are 64 bits wide. Only the SIMD
intructions use all 128 bits (32bitx4, 16 bitX8 or 8bitx16 data
types). There are no special porpouse SIMD registers.

Luiz Carlos.

 

[Jonathan Bromley]

"black" <mini_monkey@163.net> wrote in message
news:bdrkmo$vq2ne$1@ID-199450.news.dfncis.de...

The reason for using FPGA's dedicated
clock distribution resources is
that there is no clock skew in these resources,is that right?

There is always *some* skew, but whatever it is, the FPGA
manufacturer guarantees that if you use the dedicated clock
network then you will never suffer from the skew-related
race condition that we discussed.

When designing ASICs and custom ICs, you achieve the same
result by using specialised clock tree insertion software.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Christian Haase]

Hi tk,

thanks for your reply.

I had to get more familiar with the the buff-stuff. An ibufg is just a
dedicated input buffer
for connecting to the clock buffer BUFG or CLKDLL.The clock problem was
solved
with the insertion of a BUFG.

Actually, my dwarfish design is routed on a Virtex-II device using the
Xilinx xapp290
example bus-macro. Maybe the format of that macro (created with a former
FPGA-Editor
version) differs slightly from the format of the self-made macros?

Christian

 

[rickman]

Luiz Carlos wrote:

Again, I don't think you are reading what I am posting. In the XC3S400
there are almost 7200 FFs and LUTs. So there are nearly 3600 LUTs
capable of being RAMs and SRs. How many do you really need??? That is
56,000 bits of distributed RAM, almost a quarter as much as the block
rams! Don't you need some LUTs to use as logic???

The wider address rams will require external muxing/control to
implement with only 4 LUTs/CLB usable as ram rather than 8.

That is my poit of view. I don´t care (not much) of having just half
of the LUTs confurable as memory (I´ve read what you wrote, Rick), but
I didn´t like loosing those dual ported bigger blocks (you didn´t read
carefully what I wrote). To have the same function I'll need a lot of
additional logic and/or a clock two times faster. So, my DSP designs
need a lot of more CLBs in Spartan3 than in Virtex2, and I'm not Ray.

Luiz Carlos Oenning Martins
KHOMP Solutions

You can feel how you wish about your designs, but even the loss of the
64 bit dual ports and the 128 bit single port rams is not signficant.
To make a 64 bit dual port RAM requires 8 LUTs for ram (same as in VII)
and one LUT for the read mux and possibly two more LUTs for the WEs.
But if this is part of a larger ram block you are making half of the WEs
would have been required anyway. So it is not a "large" amount of
logic, just a bit more.

If you are making really large blocks where the longer runs on the
address and data can slow it down significantly, then you likely are
better off with the block rams.

Considering the much lower price of the XC3S parts, all this sounds to
me like a benefit, not a liability. Think of it as paying for the LUTs
that have RAM and getting the other LUTs for free

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Colm Clancy]

Thomas,

Ngdbuild is warning that what it thinks is a clock (but is actually a reset) is
not connected to clock pins of various components. When I have seen this
warning it was usually as a result of having some non clock nets driven by a
clock buffer, i.e. a bufg.

Colm.

Thomas wrote:

I get the following warning:

WARNING:NgdBuild:477 - clock net 'resetlogic_local_reset' has non-clock
connections. These problematic connections include: pin clr on block
resetlogic_resettimer_3 with type FDCE, pin pre on block
resetlogic_resettimer_0 with type FDPE, pin pre on block
resetlogic_logicreset with type FDPE, pin pre on block
resetlogic_resettimer_1 with type FDPE, pin pre on block
resetlogic_cpureset
with type FDPE, pin pre on block resetlogic_resettimer0_1 with type
FDPE, pin
pre on block resetlogic_resettimer0_0 with type FDPE, pin pre on block
resetlogic_resettimer_2 with type FDPE, pin pre on block
resetlogic_resettimer_4 with type FDPE

... that signal is a reset signal that stays low for a few clocks then goes
high. What does this message mean?
the xilinx doc, is (once again | as usual | as expected ) useless at
describing what it is.

 

[Peter Alfke]

rickman wrote:

Except that I often am contacted by Altera directly rather than here in
public. I can understand why they would do that.

I cannot understand that at all. If the question is ventilated in
public, it should be answered in public. Unless the answer is very embarrassing...

Peter Alfke, Xilinx

 

[Peter Alfke]

Perhaps I did not explain well enough:
Use the asynchronous reset the way you want to.
Then generate a synchronous signal that lasts a little longer than the
asynchronous reset, and use this synchronous reset signal to either
drive Clock Enable inactive, or to force D Low. This overrides the
trailing end of the asynchronous Resst, and lets the flip-flop "wake up"
in a synchronous fashion, which is easy to simulate...
Peter Alfke
===================
Nial Stewart wrote:

Peter Alfke <peter@xilinx.com> wrote in message
news:3F00A341.650BCCA4@xilinx.com...
My approach would be to generate a synchronous CE (clock disable) signal
and distribute it. Now I have a synchronous signal distribution problem
that I can analyze the conventional way. If the prop delay is less than
a clock period, there is no problem. Otherwise I can resort to
pipelining...
That means, you are in charge and not at the mercy of some loosely
specified asynchronous delay

Peter, do you recommend using these synchronised resets with the asynch
reset
input of your flip-flops, or do they then become part of the
synchronous inputs?

Nial.
------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk

 

[Peter Alfke]

Sorry, this was meant to be a personal reply, and it says that I have
Spartan3-50s here in my drawer. They do exist !
(BTW, don't use your German dictionary, it starts with some colloquialisms...)
Peter
===============
Peter Alfke wrote:

Willste nen S3-50 haben? Die liegen hier in meiner Schublade...
Darmstadt ist ja nicht so sehr "out in the wild"
Gruss
Peter
======================
Uwe Bonnes wrote:

DK <dknews@ueidaq.com> wrote:
: Hi, All

: for the new multichannel filter design I have a choice -
: Altera Cyclone EP1C12 ($60) or Xilinx Spartan-3 XC3S1000(???)

: Xilinx part has a embedded MAC units.

: I've used in a past Altera chips and they have a good tech support and free
: tools.

: Does any one has experience with Xilinx support? And is it possible to
: obtain a free tools from Xilinx or they charge for the software?

: Any other hidden issues?

Don't expect the Spartan III out in the wild any soon...

Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

 

[Antti Lukats]

"tk" <tokwok@hotmail.com> wrote in message news:<bde307$j68$1@www.csis.hku.hk>...

Hi all,

I have problem in configuring the xc2vp7 on the ML300 board. The
problem is described in the previous thread "ERROR:iMPACT:583".

I doubt that I have omitted some settings on the ML300 board during
programming (or have done sth wrong in iMPACT). There is a button
called "FPGA PROG" on the ML300 board. I've searched through the
documentation but I couldn't find out what's it for.

Does anyone have the experience on using ML300 that can share with me ?

Thanks very much.

tk

there is not much I can share (yet) but:

the impact/xps download to ML300 freezes some times, problem has been
fixed by restarting rebooting, sometimes pressing the "fpga prog" button.

the fpga prog button I guess simply forces the fpga to not-init state
waiting for config, as sysace is not reset, it stays in non-configured
state until you configure with impact.

there are no settings on ML300 that could prevent the jtag re-config
it should always work (but does not)

in my case I had started v2pdk shells, debug server debugger, killed
them and then tryied impact, and was freeting, not sure why.

antti

 

[Mike Randelzhofer]

"Peter Alfke" <peter@xilinx.com> wrote in message
news:3F01ACDB.D6932AAE@xilinx.com...

Willste nen S3-50 haben? Die liegen hier in meiner Schublade...
Darmstadt ist ja nicht so sehr "out in the wild"
Gruss
Peter
======================
Uwe Bonnes wrote:

DK <dknews@ueidaq.com> wrote:
: Hi, All

: for the new multichannel filter design I have a choice -
: Altera Cyclone EP1C12 ($60) or Xilinx Spartan-3 XC3S1000(???)

: Xilinx part has a embedded MAC units.

: I've used in a past Altera chips and they have a good tech support and
free
: tools.

: Does any one has experience with Xilinx support? And is it possible to
: obtain a free tools from Xilinx or they charge for the software?

: Any other hidden issues?

Don't expect the Spartan III out in the wild any soon...

Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Hab auch ein paar S3-50 in der Schublade...
Weiss aber immer noch nicht ob die Blockrams und DLL's haben oder nicht ?

Gruss MIKE

for our english readers:
I also have some spartan3-50 devices, but don't know if they have blockrams
and dll's ?

regards MIKE

 

[Antonio Pasini]

"Jun" <free_y2003@yahoo.com> ha scritto nel messaggio
news:vc32gvkddvihro1o7ukstsqu6ue6l9bhdv@4ax.com...

I am now designing a FPGA based video processing board for my own use.
The board has standard NTSC/PAL, HD and DVI input., a VirtexII FPGA,
64 bit DDR-SDAM interface, DVI/RGB/YPbPr output, I2C and UART
communication port. Recently, I heard some interests from others

I'd purchase one myself, should that contains also:

- a strip for piggy back modules, with at least 8 bit + clock + 3 ctrl
lines, to test different decoders, or different receivers.
- an NTSC/PAL encoder
- a Firewire port ? or maybe pushing up a bit the "piggy back" interface...
- the HD input can scale down to SDI ?

Keep us informed, seems really interesting.

 

[Eric Crabill]

Hi,

There are a number of boards available. You should look
for a server class motherboard, one that supports PCI-X
or at least PCI at 66 MHz. A board that supports either
of those will be (by requirement) at 3.3v slot, not a 5.0v
slot.

If you are looking for a cheap machine that will do the
job, you may consider the HP Kayak XU800. I see a number
of them available on Ebay from time to time.

Eric

Colin Hall wrote:

Dear All,

Apologies if this is slightly off-topic but I hope there may be
someone reading who has faced a similar problem.

I have a prototype 33/32 PCI peripheral. The PCI bus interface is
implemented in a Spartan-IIE device, which is not +5V tolerant. Design
verification of the hardware is underway on this new design.

I would like to make progress on software development while we wait
for the hardware to be finished. To that end, I am looking for a
PC-architecture motherboard into which I can plug our prototype card
without blowing the Spartan-IIE device.

I tried searching for suitable commodity motherboards. There are
plently of boards but none of them specified that their PCI bus
interfaces were 3.3V only.

If anyone can suggest a suitable board I would be most grateful.

Regards,
Colin.

 

[M.Randelzhofer]

"Peter Alfke" <peter@xilinx.com> schrieb im Newsbeitrag
news:3F01C8E9.9E79F922@xilinx.com...

Let's stick with English, otherwise we have ro rename this the
"FPGAinformationsaustauschzentralverteilungsstelle".

OK, but i didn't know that this NG is called
"FPGAinformationexchangecentraldistributioncenter".

All presently existing S3-50s lack the BlockRAM and therefore the DLLs (
BlockRAM and DLL share a column. When we took out one, we had to take
out the other). The decision was made in order to speed up the design,
and was then reversed, so all future production 50's will have BlockRAMs
and DLLs.

So the present s3-50 devices without blockrams are the fastest s3 90nm chips
forever ?

MIKE

 

[Luiz Carlos]

You can feel how you wish about your designs, but even the loss of the
64 bit dual ports and the 128 bit single port rams is not signficant.
To make a 64 bit dual port RAM requires 8 LUTs for ram (same as in VII)
and one LUT for the read mux and possibly two more LUTs for the WEs.
But if this is part of a larger ram block you are making half of the WEs
would have been required anyway. So it is not a "large" amount of
logic, just a bit more.

Ok, I agree with you, it´s not to much logic. But because these extra
delays maybe I have to duplicate the circuits.

If you are making really large blocks where the longer runs on the
address and data can slow it down significantly, then you likely are
better off with the block rams.

No, they are not large blocks, but I have 128 to 512 FIR filters (256
coefs) running in parallel, and the sampling rate is 2 megaHertz.
Throughput!

Considering the much lower price of the XC3S parts, all this sounds to
me like a benefit, not a liability. Think of it as paying for the LUTs
that have RAM and getting the other LUTs for free

I'm not complaining, and I know that Xilinx wil not make a special
Spartan3 just for me. But I have the right to express what I think,
and maybe I'm not alone. Maybe there are a lot of Luizes and Rays,
maybe Xilinx will hear us and maybe, at these nanometer scales where
the pads are so big, to have all the CLBs configurable as memory is
not so significant in silicon area.

Luiz Carlos Oenning Martins
KHOMP Solutions

 

[Subroto Datta]

already5chosen@yahoo.com (Michael S) wrote in message news:<f881b862.0307010229.563153f@posting.google.com>...

sdatta@altera.com (Subroto Datta) wrote in message news:<ca4d800d.0306301212.1cd9be9c@posting.google.com>...
already5chosen@yahoo.com (Michael S) wrote in message news:<f881b862.0306300619.58b3f8a5@posting.google.com>...
Following PLL was generated with MegaWizard Plug In Manager and
compiled (for Stratix) under Quartus 2.2:
Input Frequency: 36MHz
Dynamic reconfiguration is in use.
c0 Clock Multiplication Factor = 158
c0 Clock Division Factor = 36
Other counters are not in use.
The compilation report shows:
M value = 79
N value = 3
VCO frequency = 948MHz !!!!
It looks like Quartus design team is not aware of limitations of the
Stratix PLL as listed in the respective datasheet (300 to 800MHz for
-5 and -6 grades, 300 to 600MHz for -7 grade). They live under
impression that everything up to 1000MHz is o.k.
The Stratix Fast PLL can go up to 1GHz for certain speedgrades, which
is why the Megawizard allows this (only the Enhanced PLL is limited to
800Mhz). A design that needs a VCO at 1GHz will work in Stratix. The
PLL will then be placed on the Fast PLL and be used as a general
purpose PLL. However a Fast PLL cannot be used for dynamic
reconfiguration, and this should have been reported during fitting.

For Quartus II version 3.0, the Megawizard has been enhanced to
recognize that only an Enhanced PLL can be used when dynamic
reconfiguration is selected, and as a result it will ensure that the
VCO is valid for an Enhanced PLL in the Megawizard itself. The
Megawizard will become speedgrade aware in a future release of
Quartus. In the meantime all calculations are based on the fastest
speedgrade.

- Subroto Datta
Altera Corp.



I don't have Quartus II version 3.0 (BTW, is it already available ?)
so can't comment about it. What I do know - Quartus II version 2.2
Megawizard doesn't emit "enhanced" set of PLL parameters, so the
Megawizard has no direct control of the VCO frequency. Unless it was
changed in the 3.0, I can't see how improvements in the Megawizard
would fix the problem. IMHO, the bug is in the compiler and it's where
it should be fixed.
In the mean time, the only reliable solution I can think of is:
1. Don't use the Megawizard.
2. Manually set enhanced parameters for the altpll().
It would work, of coarse, but it's a PITA...

Regards,
Michael

In Stratix devices there are two types of PLLs - Enhanced PLLs and
Fast PLLs. The Megawizard performs a feasibility check to make sure
the resulting parameters the compiler will compute (including the VCO
frequency) will be valid for at least one of these PLL types. For
Quartus II 3.0, the Megawizard is aware of the restriction that forces
the use of Enhanced PLLs when using reconfiguration, and as a result
will make sure all parameters can be implemented in an Enhanced PLL
earlier on in the flow.

But even in Quartus II 2.2, the compiler will give an error if the PLL
cannot be implemented in either of the PLL types, including if no set
of internal parameters could achieve the requested PLL settings and a
legal VCO for the speed grade selected. If a legal set of internal
parameters did exist that could achieve the requested PLL settings,
then the compiler will implement those parameters.

Quartus II 3.0 was released to production/manufacturing on June 27th
so you should be seeing it real soon.

- Subroto Datta
Altera Corp.

 

[Uwe Bonnes]

Mike Randelzhofer <michael.randelzhofer@mchf.siemens.de> wrote:

: Hab auch ein paar S3-50 in der Schublade...
: Weiss aber immer noch nicht ob die Blockrams und DLL's haben oder nicht ?

: Gruss MIKE

: for our english readers:
: I also have some spartan3-50 devices, but don't know if they have blockrams
: and dll's ?

To my knowledge, the first batch of 3S50 was made without BRAM and DLLs. Try
to decipher the Date Code and you probably you'll find information on the
Xilinx webpage ( and you probably will get feedback here).

Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

 

[Peter Alfke]

"M.Randelzhofer" wrote:

So the present s3-50 devices without blockrams are the fastest s3 90nm chips
forever ?

No, when I wrote "speed up", I meant weeks in design, not picoseconds in operation.
Spartan3 is not the fastest, in some areas it is slower than Virtex-II,
since the priorities for Spartan3 were: 1. low cost, 2. low cost, and 3.
low cost. We don't throw away speed, but we did not increase the chip
size to gain performance.
Deleting BRAM and DLL does nothing to the performance, but it reduced
the design effort, and it made the chip smaller. But this is all history now.

"FPGAinformationsaustauschzentralverteilungsstelle" was meant as a joke,
referring to the American fascination with the German capability to
concatenate words ad infinitum. Donaudampfschifffartgesellschaftskapitaen....

Peter Alfke



Peter Alfke

 

[Peter Ryser]

Please make sure that you are using the latest Xilinx Implementation tools.
From the previous message I can see that you are using 5.1. The latest
tools are 5.2i with service pack 3.

When looking at the schematics for the ML300 you will see that the FPGA
PROG button goes to the corresponding pin on the FPGA, i.e. pushing the
button will clear out the contents of the FPGA.

- Peter




tk wrote:

Hi all,

I have problem in configuring the xc2vp7 on the ML300 board. The
problem is described in the previous thread "ERROR:iMPACT:583".

I doubt that I have omitted some settings on the ML300 board during
programming (or have done sth wrong in iMPACT). There is a button
called "FPGA PROG" on the ML300 board. I've searched through the
documentation but I couldn't find out what's it for.

Does anyone have the experience on using ML300 that can share with me ?

Thanks very much.

tk

 

[Steven K. Knapp]

"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F00FDD2.C74022BD@yahoo.com...

"Nicholas C. Weaver" wrote:
That is a good point about the tools. I forget that the XC3S is only
supported in webpack in the XC3S50 now and I think only up to the
XC3S400 in the next release. I honestly don't get the idea of selling
very low cost chips and not adding them to the free tools.

Personally, I agree with your statement and have been trying to convince the
powers that be to add additional Spartan-3 devices to WebPack. The folks
responsible for WebPack are concerned about the total download size. The
larger devices have multi-MB support files.

But good luck getting a price on the XC3S1000 at this point. The
XC3S1000 parts have been pushed back due to design problems and will not
be out until Q1 or perhaps later. The XC3S400 and one of the larger
parts will be out in 4Q03 according to their schedule.

Hmm. Engineering samples of the XC3S1000 and XC3S50 are available today.
The engineering samples have the part number XC3S1000J and XC3S50J to
distinguish them from the production devices. This may be the reason you
were quoted longer delivery. The non-'J' devices are due out in 4Q2003.
The non-'J' version of the XC3S50 also includes block RAM, embedded
multipliers, and 2 Digital Clock Managers (DCMs), which the XC3S50J does
not.


--
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Spartan-3
Tel: (408) 626-7447
E-mail: steve.knapp@xilinx.com
---------------------------------