EDK : FSL macros defined by Xilinx are wrong

[RCIngham]

HI everyone, i'm starting in the world of DSP, i have a project its a
security system by voice patter recognition, and i have used
pic16f877a in others projects, but it seems not enough for dsp, thou
it has a ADC converter 10 bit - fmax = 20mhz, and i was thinking to
combine with fpga spartan 3a (sending the digital signal to spartan
and then maybe do some fft and filter processing ) ... but i friend of
mine has a TMS320 C6713 dsk and he told to me that is better with it,
i new in all of this, i dont know how to use C6713 dsk ...so i need
some advice, baby steps that i could take to do this project, please
someone...

Have you tried asking on an appropriate forum, such as 'comp.dsp'?

http://www.dsprelated.com/compdsp.php

 

[Symon]

<t.bartzick@gmx.net> wrote in message
news:b21088bb-cb93-4e0a-8789-934157d6aa62@k7g2000hsd.googlegroups.com...

Slow-Encoder-Signal -> FF-BASED-EDGE-DETECTOR -> CE of COUNTER.

^ ^

----Is the clock for this ^ FF the same clock as this ^ counter?

Cheers, Syms.

 

[Mike Lewis]

<t.bartzick@gmx.net> wrote in message
news:9094dad7-fac6-47f8-b672-a12038d33355@59g2000hsb.googlegroups.com...
On 18 Sep., 18:45, "Symon" <symon_bre...@hotmail.com> wrote:

t.bartz...@gmx.net> wrote in message

news:b21088bb-cb93-4e0a-8789-934157d6aa62@k7g2000hsd.googlegroups.com...

Slow-Encoder-Signal -> FF-BASED-EDGE-DETECTOR -> CE of COUNTER.

^ ^
----Is the clock for this ^ FF the same clock as this ^ counter?

Cheers, Syms.

Hi!

Yes, it is!

Thomas.



Then it won't be glitchy when it matters.
Mike

 

[Tony Burch]

"KJ" <lkjrsy@gmail.com> wrote in message
news:8f945df8-f4b2-4ed7-9fe8-b991348eb1f7@z11g2000prl.googlegroups.com...

Hello everyone.

I'm a very beginner wiht FPGA board like following.
http://hitechglobal.com/catalog/product_info.php?cPath=1&products_id=199

This board contains Virtex5 FXT. I think that I need a ISE 10.1 to
support it.
Following is what I'm think of the development procedure.

(1) Make VHDL codes for Virtex5 FXT in ISE 10.1 (?)
(2) Synthesis/Translate/Palce&Part and Simulation
(3) Download bitstream into the Chip (?)
(4) Testing

In (1), someone told me that I don't need ISE and usually if I
purchase the FPGA board, software comes along with that. is this
right?

In (3), How to configure the chip? I have never done this before.
Could you explanin the procedure of configuration?
This board has the
flash memory for FPGA configuration and storage.
But, I don't know
how to use it.

Hi KJ,

Since you are just getting started, perhaps you could have a look at some of
the videos at http://www.burched.com

Click on Free_Videos to see the first 6 (very informative) and then it's
less than $20 to view more.

Best regards,
Tony Burch

 

[HT-Lab]

"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message
news:88e7d4lvorohjdnkbrf3j91khq520fm250@4ax.com...

On Fri, 19 Sep 2008 04:06:51 -0700 (PDT), "psihodelia@googlemail.com"
psihodelia@googlemail.com> wrote:

...snip

Recently, Synopsys acquired Synplicity. That's interesting.

Or perhaps worrying...

According to a statement by Aart de Geus they purchased Synplicity for the
Hardi line:

"Because we are stressing the systems, embedded software and related
sectors. We acquired Virtio Corp of the US in August 2006, picking up its
Innovator software for virtual hardware prototyping. We acquired Synplicity
for its HAPS, which is the FPGA board for hardware prototyping. Now we can
provide software developers with both software and hardware prototyping
methods."

http://techon.nikkeibp.co.jp/article/HONSHI/20080826/156958/

Lets hope Synplify is not going the same way as FPGA Express/FPGA
Compiler/DC-FPGA......

Hans
www.ht-lab.com

 

[Krzysztof Kepa]

"Tony Burch" <tony@burched.com.au> wrote in message
news:48d3beb4$0$4451$afc38c87@news.optusnet.com.au...

Since you are just getting started, perhaps you could have a look at some
of the videos at http://www.burched.com

KJ,

You could also have a look at online course at http://www.appliedvhdl.com.

It contains number of free videos and design templates. Also the virtual
FPGA lab facility is on the way...

Topics covered:

Module 1: VHDL capture to hardware (basic combinational logic system)
1.1 > Introduction, Hardware Demonstration, Project Files 11 mins
1.2 > Invoking ISE tools, creating ISE Project, Viewing RTL and Technology
Schematic 11 mins
1.3 > VHDL Testbench creation and VHDL Simulation. Creation of simulator
macro files.
Viewing Placed & Routed Design 11 mins
1.4 > Structural VHDL 6 mins
1.5 > Top (FPGA) Level VHDL Simulation 10 mins
1.6 > VHDL Synthesis & FPGA H/W Implementation. Viewing P&R Design in FPGA.


Module 2: VHDL capture to hardware for synchronous (register-based) system
2.1 > VHDL Capture to Hardware Implementation for synchronous /
register-based systems 4 mins
2.2 > Register-based system block diagram. Project files. Xilnx ISE Project
creation 4 mins
2.3 > D Flip Flop VHDL Model. Synthesising VHDL and Viewing RTL Schematic.
7 mins
2.4 > DFF VHDL testbench and simulation 8 mins
2.5 > FPGA Top level VHDL model. FPGA Top level simulation / VHDL testbench
11 mins
2.6 > FPGA Implementation, FPGA pinout, generating FPGA configuration
bitstream. 10 mins
2.7 > VHDL coding recommendations

Module 3: VHDL for 'above gate-level' combinational model description
3.1 > Introduction, Overview of application, overview of laboratory files 6
mins
3.2 > Multiplexer function, Entity declaration, MUX using if-then-else, VHDL
and concurrency 8 mins
3.3 > if-then-else statement syntax, inferring latches (often incorrectly)
and flip flops 6 mins
3.4 > Mux using Case & Concurrent statements 7 mins
3.5 > Simulation of muxAndDecEx1, sensitivity list rules, top level VHDL
models and simulation 8 mins
3.6 > FPGA hardware implementation and demonstration of hardware operation
4 mins

Module 4: VHDL for efficient testbenches
4.1 > Applying TB stimulus using: For Loop, Stimulus Array, Text Stimulus
File

Regards,
Krzysztof

 

[Nico Coesel]

Darol Klawetter <darol.klawetter@l-3com.com> wrote:

On Sep 19, 3:48=A0pm, Marlboro <cco...@netscape.net> wrote:
Remember back in the old days, the Xlnx sw can detect your ucf syntax
error almost immediately and point out which error whih c line.. blah
blah..

But in the 10.1 (dont know what happened to the others), it take like
10 minnutes or so to do some blah blah translate then it ends up to
tell that your ucf got a problem. =A0Then you have fix the ucf file then
re-run everything.. then take another 10 minutes to find out your ucf
has another syntax error, what's the progress here?

I typically don't update a software tool unless there is a pressing
need to do so. This is especially true of a synthesis tool. I'm still
running ISE 8.1 - it's currently meeting my area and timing
requirements.

I have been using ISE8.2 for a project but it is terribly slow. IIRC
the older versions are more faster. But then again; writing an IDE is
not Xilinx's core business. They really should wake-up and write an
Eclipse plugin instead of keep on doing something they obviously know
nothing about.

--
Programmeren in Almere?
E-mail naar nico@nctdevpuntnl (punt=.)

 

[Tony Burch]

"Peter Alfke" <peter@xilinx.com> wrote in message
news:83321799-204c-47e6-8c7b-0ac53ceab040@b2g2000prf.googlegroups.com...

After 13 years and >2000 postings I will retire from comp.arch.fpga.
I think I have helped some, informed many, and irritated only a few.
It has been a significant part of my life, and I will miss it. (But I
will keep lurking from home).
Xilinx asked me to organize the user documentation for the next
generations of Virtex and Spartan devices.
That keeps me real busy, and I hope you will appreciate the results in
due course.
Cheers, Good-Bye und Auf Wiedersehen !
Peter Alfke

Thank you Peter for all your care and effort with this group over the years.

You will be sorely missed and affeectionately remembered.

It was highlight for me when I met you in person once and shook your hand at
a Xilinx seminar in Sydney Australia.

Best wishes for your new roles and kindest regards,

Tony Burch

 

[Joseph H Allen]

If you have slow slew rate selected, I would just connect the pin right to
the coax- it will work fine. If you have fast slew rate selected, series
terminate with a 33 - 50 own resistor.

You can put the DC blocking capacitor right at the FPGA pin as well.

In article <b494fffb-34a2-4872-8b3b-d2618b6af742@k37g2000hsf.googlegroups.com>,
<heilig@iname.com> wrote:

I recently purchased a Xilinx Spartan II development kit from www.easyfpga.com.
My intention is to use the board to generate a BPSK modulated
intermediate frequency. I want to connect an output pin directly to a
lowpass filter (e.g. this one: http://www.mini-circuits.com/pdfs/BLP-10.7+.pdf
) that has a 50 ohm input.

Let's say I generate a sequence of 1's and 0's at a sample rate of 20
MHz. If I consider this an analog signal it is a 10 MHz square wave.
This square wave has frequency components at 10, 30, 50, 70 etc. MHz.
If the output voltage is +3.3 VDC for a 1, and 0 for VDC for a 0 then
there is also a DC bias. If I lowpass filter this signal I should end
up with a 10 MHz sine wave plus the DC bias. If I then block the DC
with a capacitor I should have a 10 MHz sine wave centered at 0
volts...right?

The Xilinx documentation says I can choose from a variety digital
outputs, for example LVTTL. My question is can I just connect the
center pin of my coax to the output pin of the FPGA board, and ground
the shield conductor? Do I need some sort of impedence matching? How
do I do that?

Thank you,
Brian

--
/* jhallen@world.std.com AB1GO */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0%79-77?1:0<1659?79:0>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

 

[MM]

Hi Peter!

As others have already pointed out, your and Austin's presense here was
important not only for us, your customers, but also for Xilinx. It's too bad
you both have now left... But let's look at the bright side:

"Peter Alfke" <peter@xilinx.com> wrote

(But I will keep lurking from home).

This is our hope for the X future

All the best,
/Mikhail

 

[MM]

It's not clear from your post whether you are talking about the same PHY
used differently or different PHYs. PHY output drivers can be either voltage
or current mode. Current mode drivers require pullup to a voltage source.
Some PHYs have different dirvers in different modes of operation (e.g.
10BaseT vs. 100 or 1000BaseT). Also, there are a few different types of
magnetics used, which might require different termination schemes. Try to
find appnotes relevant to the PHY you are using.

/Mikhail



"Roger" <rogerwilson@hotmail.com> wrote in message
news:xP6dnerrZZ6bakrVnZ2dnUVZ8sDinZ2d@posted.plusnet...

The paired MDI signals from the PHY to the magnetics in a GbE application
are each terminated by a 50R resistor and then together to a 10nF
capacitor
to GND. However some applications connect the 2 resistors to Vcc (2.5V) as
well. Can anyone explain why some configurations are like this and others
aren't? Is it something specific to the magnetics?

TIA,

Rog.

 

[Andreas Ehliar]

On 2008-09-23, glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote:

The Intel 8086 and 8088 use a 33% duty cycle clock for maximum
clock speed. Something strange in that design.

My guess would be that this is caused by a latch based design.

I guess that a structure as the one below might cause non
50% duty-cycle clocks to be more optimal although I don't have
any personal experience in designing such latch based designs:

Logic (with delay t)
|
V
Latch (Enabled by positive clk)
|
V
Logic (with delay 2*t)
|
V
Latch (Enabled by negative clk)

/Andreas

 

[MM]

Companies making Ethernet PHYs are very secretive for whatever reason. You
need to talk to them to get access to even the most basic information. An
NDA might be required, which is difficult to arrange if you don't work for a
business. However, if you manage to get access, you will find that there is
a lot of information available. A while ago I chose a different vendor
because Marvell was slower to respond to my requests for nformation.

/Mikhail



"Roger" <rogerwilson@hotmail.com> wrote in message
news:VZ-dndx23qW1v0fVRVnyvgA@posted.plusnet...

Thanks for the reply. I've tried very hard to find something definite
regarding the PHY I'm using (Marvell 88E1112) but can't. In my original
post I meant different PHYs seem to be connected differently. From what
you say, IF the 88E1112 is a current mode driver, connecting to 2.5V could
be the correct thing to do.

Roger.

 

[MM]

Since you are posting on c.a.f. you are probably following one of the FPGA
eval board reference designs, right? Xilinx ML403 board uses a Marvell chip.
I don't remember the exact P/N, but it is something similar to yours. Newer
V5 boards might be using newer chips... If you follow one of these examples
you should be pretty safe even if you don't understand all the details of
the circuit...

Also, why don't you post a link to the circuit in question and someone might
be able to give you a better advice....


/Mikhail


"Roger" <rogerwilson@hotmail.com> wrote in message
news:B6OdnSCVGb3LHkfVnZ2dnUVZ8q_inZ2d@posted.plusnet...

Thanks for your reply. I have an NDA with Marvell and there is a fair bit
of information to be had but I still can't find the answer. I've asked for
help from them but they're not very responsive! I don't know why they're
so secretive.

Rog.

 

[Kappasm]

Hi Jerzy Gbur.

Thanks for your replay.

You can design new OFDM symbol, without part of carriers. I did not
understand it anyway as achieve it. you might be more accurate ?

I sincerely not thought I had at this solution.

I have an IFFT of 2048 point. Mapping pilot at input of IFFT for +/-DC
offset, [0 - 852 Data pilot] [853 - 1194 Null pilot] [1195 - 2047 Data
pilot]. Process IFFT and i obtain a time domain data, with sample time of
7/64e6 I obtain 8 MHz band.

Keeping the same IFFT point to 2048 as carriers can remove ?

Regards,

Kappasm.

 

[Andreas Ehliar]

On 2008-09-25, Steve Knapp <steveD.O.TknappA.Tprevailing-technologyD.O.Tcom> wrote:

Peter, thank you again for being "progressive" and championing the "old"
customer-centric Xilinx ways.

Informed customer + responsive, communicative vendor = Long-time
customer and successful vendor.

Agreed. Another point that is not immediately obvious is the fact that a posting
from comp.arch.fpga is often the first hit you get when you search for some kind
of FPGA related issue. So many people beside Usenet readers will benefit from
vendor participation on comp.arch.fpga.

While I understand that Peter have other things to do with his time, I hope
that at least some people from Xilinx will continue their presence here.

The response from Xilinx here is probably the biggest issue why I landed in
Xilinx-land and haven't yet bothered to look deeply at Altera, Actel or Lattice.
Although I must admit that I'm probably not the biggest customer that Xilinx
have

/Andreas

 

[Andreas Ehliar]

On 2008-09-26, Mark McDougall <markm@vl.com.au> wrote:

You probably should read O'Reilly's "Linux Device Drivers". IIRC there is
some way to map PCI memory into user space without writing a driver, but
it's been a long time...

I wrote a post about this on comp.arch.fpga some time ago:

http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/5171491963302b63/daf1deb1296c46eb?lnk=st&q=group%3Acomp.arch.fpga+linux+ehliar#daf1deb1296c46eb

Essentially what you do is that you open /dev/mem and mmap it at the
appropriate location.

/Andreas

 

[Symon]

Andy wrote:

On Sep 23, 11:42 am, Gael Paul <gael.p...@gmail.com> wrote:
5. Once you have converted your generated clock, you will probably
need to add multi-cycle paths constraints to avoid false critical
paths.

Avoid using multi-cycle path constraints unless you absolutely have to
use them, or are getting unacceptably long run-times trying to meet
single cycle timing on those paths. The reason is that multi-cycle and
false path constraints can be tricky to specify correctly, and make
sure that only those paths that are truly multi-cycle or false are
constrained (actually relaxed) as such.

Andy

Hi Andy,

I've noticed that a lot of people on this newsgroup have a morbid fear of
mutli-cycle clock constraints.

Personally, I use them all the time and have few problems; certainly fewer
problems than I would have if I tried to do the same thing with multiple
clocks. In a situation where a block of logic can run at (say) half the
clock rate, I give it an enable and set the constraints accordingly using
the
NET "clock_enable_signal*" TNM=TS1;
thing in the Xilinx tools. (BTW, The asterisk is useful if the enable gets
replicated by the synthesis tools) This lets the P&R tools concentrate
effort where it's needed.

Of course, avoiding multi-cycle constraints by using a divided clock would
be bad.

Can you give an example where you've run into problems?

Thanks, Symon.

 

[Symon]

Andy wrote:

Using the clock_enable_signal as the defining constraint only works if
all the INPUTS to those register come from registers that were also
(and always) disabled by the same signal. If the source or destination
registers are ever enabled at other times when clock_enable_signal is
false, look out.

Andy

Hi Andy,

Absolutely. However, the tools (are meant to) take care of all that.

If you see a problem with constraints like this one below, I really would
like to know about it.

NET "clock_enable_signal*" TNM=FFS "enabled_ffs";
TIMESPEC TS1 = FROM : enabled_ffs : TO : enabled_ffs : 20ns;

Thanks, Symon.

p.s. Here a link to the TNM documentation.

 

[Symon]

Gael Paul wrote:

Symon,

My two cents...

Multi-cycle paths constraints (as well as false paths constraints) are
inherently fine. However, they should be used only when necessary as
they dramatically increase the complexity of timing analysis, which
can lead to increased runtime and memory usage, and even QoR
degradation in extreme cases.

Indeed, timing-driven tools (synthesis, placement, routing) spend a
lot of time running timing analysis to select the next critical path
to work on, and to evaluate the impact of a given optimization (logic
optimization for synthesis, placement update, routing update). The
more exceptions they have to handle (and the more complex they are, in
particular -through points) the harder it is to handle them.

My advice is thus to only add the timing exceptions that apply to
critical paths (negative slack) as you really don't want your tool to
needlessly work on these paths (often at the expense of other -truly-
critical paths). At synthesis, I also suggest adding exceptions for
near-critical paths (e.g. slack < worst slack + ~0.5ns). Indeed, the
best synthesis tools (like Synplify Pro) actually work a little beyond
the most critical paths, in an attempt to compensate for estimation
errors. Getting these off the road is thus a good idea to help P&R
meeting timing.

Cheers,

- gael


Hi Gael,

I may or may not agree with you! I'd be grateful to know what you think
about this...

Say I have a block which is clocked at 200MHz, but only actually needs to
run at 100MHz, and I use a clock enable to control the block. Now let's look
at some scenarios.

1) The block can easily run at 200MHz. Thus there seems no point in using a
multi-cycle path.

2) The block can only just run at 200MHz. In this case I would use the
multi-cycle constraint for the whole block as experience has shown me that
this dramatically improves P&R times. My suspicion is that the tool has to
analyse every path anyway. Adding extra exceptions isn't a big deal for it,
and the slacker requirements reduce the time needed to P&R.

3) The most of the block will run at 200MHz, but there are a few critical
paths which will not. However these critical paths will easily run at
100MHz. In this case I would again use multi-cycle enable, and I'd put it on
the whole block as it's easier to do that than specifying just the critical
path.

4) Large parts of the block barely run at 100MHz. Clearly the multi-cycle
constraint is necessary.

OK, I think we agree on (1) and (4). What would you do for (2) and (3)?

Thanks, Symon.