EDK : FSL macros defined by Xilinx are wrong

lordsathish <lordsathish@gmail.com> wrote:

Hi all....
Can Soft microprocessor like microblaze, nios replace DSP
processors...?
Or is there any soft DSP processor...?
Thanks
Click to expand...
That depends on what you want to do (performance). I've used Xlinx's
picoblaze for DSP functions several times. Some dedicated logic for
stuff like linear to a-law conversion and multiplication helps a lot.

--
Programmeren in Almere?
E-mail naar nico@nctdevpuntnl (punt=.)
 
"woko" <wkopp@gmx.net> wrote in message
news:f5eda5fe-e895-4b72-8894-5a96007bdc58@d77g2000hsb.googlegroups.com...
On 8 Sep., 18:59, "Symon" <symon_bre...@hotmail.com> wrote:


Hi Symon,
I had a look at XAPP224 and XAPP250 (for a recovered clock). At this
state I think we can not fully replace the LV1023A and LV1224B for the
full speed.
Because we transmit the signal over cable the input sensitivity could
also be an issue. I read that the FPGA inputs have more input capacity
than dedicated LVDS inputs.
The transmitter at relative low speed (24Mhz clock; 288Mbs) would be
possible, I think.

Thanks for your answers!

Best regards,

Wolfgang

Hi Wolfgang,
Click to expand...
Agreed, if your data rate is over 500Mbps, I think you need to use the
external serdes solution or maybe RocketI/O as the other poster suggested.If
you had double the LVDS channels, so half the rate, then you would probably
be able to do it in the FPGA.
Cheers, Syms.
 
"aleksa" <aleksaZR@gmail.com> schrieb im Newsbeitrag
news:7ba65a41-e819-4d58-aefe-e4e01684f2df@25g2000hsx.googlegroups.com...
Are PROGRAM, CCLK, CS and DIN 5V tolerant, during configuration?

The CS pin, according to the docs, should be connected to high logic
level.

I have connected all VCCO to 3.3V.

Anyone?
Click to expand...
Xilinx Spartan II has 5V tolerant inputs, see page 9@
http://www.xilinx.com/support/documentation/data_sheets/ds001.pdf

"In a bank, inputs requiring VREF can be mixed with those

that do not but only one VREF voltage may be used within a

bank. Input buffers that use VREF are not 5V tolerant.

LVTTL, LVCMOS2, and PCI are 5V tolerant. The VCCO and

VREF pins for each bank appear in the device pinout tables.

Also see page2@

http://www.xilinx.com/support/documentation/application_notes/xapp079.pdf

Search for "tolerant" or "5V" in the Acrobat reader to get all relevant
information concerning 5V tolerance.

For SPARTAN II or VIRTEX only:

5V tolerance means, that FPGA I/O inputs (also configuration pins) can
handle 5V levels (in LVTTL I/O Standard), but I/O outputs cannot drive to
5V, since VCCO must be below 4V.

If vou pullup an Spartan-II I/O to 5V, with tristating output, you can
measure 5V at the I/O pin. If you enable the tristate buffer for outputting
a '1' at the I/O, the voltage goes down to the VCCO level of (mostly) 3,3V,
driving VCCO with the current through the pullup. If your pullup to 5V is 0
Ohms, and you output a '1', the chip will be damaged.

For configuration issues, see also XAPP 176:

http://www.xilinx.com/support/documentation/application_notes/xapp176.pdf



MIKE

--
www.oho-elektronik.de
OHO-Elektronik
Michael Randelzhofer
FPGA und CPLD Mini Module
Klein aber oho !
Kontakt:
Tel: 08131 339230
mr@oho-elektronik.de
Usst.ID: DE130097310
 
That is what I was looking for!
A confirmation that configuration pins are also 5V tolerant.

Danke!

Bitte!

Spartan-II is rather outdated, yet beeing an interesting solution together
with 5V parts.
I remember weekly that your question was answered years ago, but since
google is used in Xilinx answer database, it's impossible to find rare
requested information :-(
If you search for e.g. a microblaze manual, you get the link to the oldest
manuals, because these are requested mostly. But you look for the newest
revision. This is BS.

The datasheet really doesn't say anything about the special config pins
concerning 5V tolerance.
(The newer docs about Spartan3 etc. are really better in many ways !)
If the configuration pins would not be 5V tolerant, Xilinx wouls say that
clearly in the datasheet.

MIKE

--
www.oho-elektronik.de
OHO-Elektronik
Michael Randelzhofer
FPGA und CPLD Mini Module
Klein aber oho !
Kontakt:
Tel: 08131 339230
mr@oho-elektronik.de
Usst.ID: DE130097310
 
<sureshbabu.payauala@gmail.com> wrote in message
news:16697b45-a499-4416-afb9-382e097471ad@n38g2000prl.googlegroups.com...
i am working on orcad 9.1 in my schematics after design rules check i
came 28 errors.1. net has fewer than two connections 2.no matching off
page connectors. these are the major error. can any one one give
suggestions
Click to expand...
Do you disagree with the assessment? Does/do the nets have only one
connection? If deliberate, you can get this error by placing a wire on a
pin and not connecting to another pin. If this is the case, remove the wire
and place a NC (X) on the pin.

--
Greg
 
Here are the system specs for old machine:
2 Intel Xeon CPU model 4, stepping 3 at 3.2 GHz
4GB DDR PC2700
FSB speed 800 MHz.
The motherboard is a Supermicro X6DAT-G

Here are the system specs for the new machine:
Intel Core2 Extreme CPU QX9770 @3.2 GHz (quad core)
OCZ Platinum 4GB (2 x 2GB) 240-Pin DDR3 SDRAM DDR3 2000 (PC3 16000)
Dual Channel
FSB speed 1600 MHz.
The motherboard is a ASUS P5E3 PREMIUM/WIFI-AP @n LGA 775
Click to expand...
Computer "old":
3.2 GHz 2 MB cache
2700 MB/s
FSB 800 MHz
Processing time: 33 minutes

Computer "new":
3.2 GHz 2x6 MB L2
16000 MB/s dual channel => 25600 MB/s
FSB 1600 MHz
Processing time: 12 minutes

Considering the data I think that mainly the onchip cache is responsible and
the fact that the cpu<->memory bandwidth is increased by a factor of 3.2x

The current software doesn't give any advantage of having multiple cpus asfaik.

I think you could possible improve the speed by getting a cpu with even larger
onchip cache. And maybe 1 GHz faster clock. An more efficient OS can also help.
 
Wow, that's quite an impressive speed-up. I wish I could convince my
company to buy a beast like that. My current design takes about 45
minutes for the PAR, on a 3.0 GHz Core 2 Duo.

Show them the numbers to illustrate how much more productive you could
be.

No doubt your time is much more expensive than a new PC.
Click to expand...
Let's not forget that the change->process->upload->test cycle is repeated many
times throughout a day. Multiplied by the sallary. And that deadlines may
be reached faster it should be a no brainer.
 
Wow, that's quite an impressive speed-up. I wish I could convince my
company to buy a beast like that. My current design takes about 45
minutes for the PAR, on a 3.0 GHz Core 2 Duo.

-Patrick
Click to expand...
Why?1? Your machine is already near the top of the heap.

Even if it's the oldest 3 GHz Core 2 Duo (E6850, or X6800), it's
only 10-20% slower than the top-of-the-line E8600 (3.33GHz.)

Aside from the larger L2-cache (6MB vs 4MB) on the E8xxx
series, you're not going to see the leapfrog improvement that
the original-poster did -- the Pentium4 architecture suffered
pretty badly when executing 'random-code' (compile-tasks.)
 
<edwin.gobain@gmail.com> wrote in message
news:60b74245-542b-4eb5-a859-aa74e152179f@s28g2000prd.googlegroups.com...
Hi

I am new to ASIC prototyping approaches. I know it concept wise but
want to know more about how popular is it among designers.
Click to expand...
A Dataquest survey from 2005 showed that 40% of all ASIC's are prototyped on
FPGA's. However, given the current cost and size of modern FPGA's I wouldn't
be surprised if that number is now doubled.

In other
words, is it a commonly taken path for verification or is more of a
concpet than having practical applictaions.

I also want to know if there are any tools specifically designed for
ASIC prototyping and how mature they are about the hanlding of issues
that will come up during the interfaces of different FPGA on boards.
Click to expand...
You need a synthesis tool that can handle an ASIC netlist (gated clocks,
Synopsys Design Constraint, Designware support) examples are Mentor's
Precision and Synplicity's Synplify. You also need a partitioner that can
map your large synthesised netlist onto multiple FPGA's. Examples are ACE
from Auspy, Chipit Manager from Prodesign, Certify from Synplicity). To get
more info check out the top 3 (?) prototyping vendors Hardi, Prodesign and
Dini.

http://www.uchipit.com/ce/index.htm
http://www.dinigroup.com/DN5000k10.php
http://www.synplicity.com/products/haps/

Hans
www.ht-lab.com


--
Edwin Gobain
Click to expand...
 
I guess that people in this group might be interested in
hearing about this years FPL conference.

* All of the keynotes were interesting, especially the
SETI and CERN keynotes.
* The CERN keynotes contained lots of details about the LHC which I hadn't
heard before. One interesting detail: The FPGAs close to one of the
detectors could not be cooled using fans because of the insane magnetic
field.
* The SETI talk partly described the FPGA based infrastructure used by
the "Center for Astronomy Signal Processing and Electronics Research".
casper.berkeley.edu has more information, including source code and board
schematics/layouts.

* Some other interesting presentations I attended:
* Martin Langhammer from Altera presented a very interesting paper about a
floating point datapath compiler. By removing parts of the normalization
and denormalization it is possible to reduce the area and latency of the
datapath. Unfortunately the tool is not available yet...
* Simulating neural networks (the application was the processing of
sensor data from whiskers)
* It was very interesting to listen to all papers in the financial
section as I know very little about this kind of area but would
like to know more.
* Also, for similar reasons, the paper on molecule docking code was
interesting as I know very little about this area.
* Tom van Court of Altera gave a nice overview of the various tools
that try to convert some form of C to hardware.

* I also got to meet a few people from comp.arch.fpga :)

* Finally, I got a nice book from the Synopsys representative.
"Advanced FPGA Design" by Steve Kilts. It contains a nice writeup
of some important details which are typically ignored or glossed over
in many textbooks. (Such as clock domain crossings.)



/Andreas
 
I guess that people in this group might be interested in
hearing about this years FPL conference.

* All of the keynotes were interesting, especially the
SETI and CERN keynotes.
* The CERN keynotes contained lots of details about the LHC which I hadn't
heard before. One interesting detail: The FPGAs close to one of the
detectors could not be cooled using fans because of the insane magnetic
field.
* The SETI talk partly described the FPGA based infrastructure used by
the "Center for Astronomy Signal Processing and Electronics Research".
casper.berkeley.edu has more information, including source code and board
schematics/layouts.

* Some other interesting presentations I attended:
* Martin Langhammer from Altera presented a very interesting paper about a
floating point datapath compiler. By removing parts of the normalization
and denormalization it is possible to reduce the area and latency of the
datapath. Unfortunately the tool is not available yet...
* Simulating neural networks (the application was the processing of
sensor data from whiskers)
* It was very interesting to listen to all papers in the financial
section as I know very little about this kind of area but would
like to know more.
* Also, for similar reasons, the paper on molecule docking code was
interesting as I know very little about this area.
* Tom van Court of Altera gave a nice overview of the various tools
that try to convert some form of C to hardware.

* I also got to meet a few people from comp.arch.fpga :)

* Finally, I got a nice book from the Synopsys representative.
"Advanced FPGA Design" by Steve Kilts. It contains a nice writeup
of some important details which are typically ignored or glossed over
in many textbooks. (Such as clock domain crossings.)



/Andreas
 
I guess that people in this group might be interested in
hearing about this years FPL conference.

* All of the keynotes were interesting, especially the
SETI and CERN keynotes.
* The CERN keynotes contained lots of details about the LHC which I hadn't
heard before. One interesting detail: The FPGAs close to one of the
detectors could not be cooled using fans because of the insane magnetic
field.
* The SETI talk partly described the FPGA based infrastructure used by
the "Center for Astronomy Signal Processing and Electronics Research".
casper.berkeley.edu has more information, including source code and board
schematics/layouts.

* Some other interesting presentations I attended:
* Martin Langhammer from Altera presented a very interesting paper about a
floating point datapath compiler. By removing parts of the normalization
and denormalization it is possible to reduce the area and latency of the
datapath. Unfortunately the tool is not available yet...
* Simulating neural networks (the application was the processing of
sensor data from whiskers)
* It was very interesting to listen to all papers in the financial
section as I know very little about this kind of area but would
like to know more.
* Also, for similar reasons, the paper on molecule docking code was
interesting as I know very little about this area.
* Tom van Court of Altera gave a nice overview of the various tools
that try to convert some form of C to hardware.

* I also got to meet a few people from comp.arch.fpga :)

* Finally, I got a nice book from the Synopsys representative.
"Advanced FPGA Design" by Steve Kilts. It contains a nice writeup
of some important details which are typically ignored or glossed over
in many textbooks. (Such as clock domain crossings.)



/Andreas
 
I guess that people in this group might be interested in
hearing about this years FPL conference.

* All of the keynotes were interesting, especially the
SETI and CERN keynotes.
* The CERN keynotes contained lots of details about the LHC which I hadn't
heard before. One interesting detail: The FPGAs close to one of the
detectors could not be cooled using fans because of the insane magnetic
field.
* The SETI talk partly described the FPGA based infrastructure used by
the "Center for Astronomy Signal Processing and Electronics Research".
casper.berkeley.edu has more information, including source code and board
schematics/layouts.

* Some other interesting presentations I attended:
* Martin Langhammer from Altera presented a very interesting paper about a
floating point datapath compiler. By removing parts of the normalization
and denormalization it is possible to reduce the area and latency of the
datapath. Unfortunately the tool is not available yet...
* Simulating neural networks (the application was the processing of
sensor data from whiskers)
* It was very interesting to listen to all papers in the financial
section as I know very little about this kind of area but would
like to know more.
* Also, for similar reasons, the paper on molecule docking code was
interesting as I know very little about this area.
* Tom van Court of Altera gave a nice overview of the various tools
that try to convert some form of C to hardware.

* I also got to meet a few people from comp.arch.fpga :)

* Finally, I got a nice book from the Synopsys representative.
"Advanced FPGA Design" by Steve Kilts. It contains a nice writeup
of some important details which are typically ignored or glossed over
in many textbooks. (Such as clock domain crossings.)



/Andreas
 
I guess that people in this group might be interested in
hearing about this years FPL conference.

* All of the keynotes were interesting, especially the
SETI and CERN keynotes.
* The CERN keynotes contained lots of details about the LHC which I hadn't
heard before. One interesting detail: The FPGAs close to one of the
detectors could not be cooled using fans because of the insane magnetic
field.
* The SETI talk partly described the FPGA based infrastructure used by
the "Center for Astronomy Signal Processing and Electronics Research".
casper.berkeley.edu has more information, including source code and board
schematics/layouts.

* Some other interesting presentations I attended:
* Martin Langhammer from Altera presented a very interesting paper about a
floating point datapath compiler. By removing parts of the normalization
and denormalization it is possible to reduce the area and latency of the
datapath. Unfortunately the tool is not available yet...
* Simulating neural networks (the application was the processing of
sensor data from whiskers)
* It was very interesting to listen to all papers in the financial
section as I know very little about this kind of area but would
like to know more.
* Also, for similar reasons, the paper on molecule docking code was
interesting as I know very little about this area.
* Tom van Court of Altera gave a nice overview of the various tools
that try to convert some form of C to hardware.

* I also got to meet a few people from comp.arch.fpga :)

* Finally, I got a nice book from the Synopsys representative.
"Advanced FPGA Design" by Steve Kilts. It contains a nice writeup
of some important details which are typically ignored or glossed over
in many textbooks. (Such as clock domain crossings.)



/Andreas
 
I guess that people in this group might be interested in
hearing about this years FPL conference.

* All of the keynotes were interesting, especially the
SETI and CERN keynotes.
* The CERN keynotes contained lots of details about the LHC which I hadn't
heard before. One interesting detail: The FPGAs close to one of the
detectors could not be cooled using fans because of the insane magnetic
field.
* The SETI talk partly described the FPGA based infrastructure used by
the "Center for Astronomy Signal Processing and Electronics Research".
casper.berkeley.edu has more information, including source code and board
schematics/layouts.

* Some other interesting presentations I attended:
* Martin Langhammer from Altera presented a very interesting paper about a
floating point datapath compiler. By removing parts of the normalization
and denormalization it is possible to reduce the area and latency of the
datapath. Unfortunately the tool is not available yet...
* Simulating neural networks (the application was the processing of
sensor data from whiskers)
* It was very interesting to listen to all papers in the financial
section as I know very little about this kind of area but would
like to know more.
* Also, for similar reasons, the paper on molecule docking code was
interesting as I know very little about this area.
* Tom van Court of Altera gave a nice overview of the various tools
that try to convert some form of C to hardware.

* I also got to meet a few people from comp.arch.fpga :)

* Finally, I got a nice book from the Synopsys representative.
"Advanced FPGA Design" by Steve Kilts. It contains a nice writeup
of some important details which are typically ignored or glossed over
in many textbooks. (Such as clock domain crossings.)



/Andreas
 
I guess that people in this group might be interested in
hearing about this years FPL conference.

* All of the keynotes were interesting, especially the
SETI and CERN keynotes.
* The CERN keynotes contained lots of details about the LHC which I hadn't
heard before. One interesting detail: The FPGAs close to one of the
detectors could not be cooled using fans because of the insane magnetic
field.
* The SETI talk partly described the FPGA based infrastructure used by
the "Center for Astronomy Signal Processing and Electronics Research".
casper.berkeley.edu has more information, including source code and board
schematics/layouts.

* Some other interesting presentations I attended:
* Martin Langhammer from Altera presented a very interesting paper about a
floating point datapath compiler. By removing parts of the normalization
and denormalization it is possible to reduce the area and latency of the
datapath. Unfortunately the tool is not available yet...
* Simulating neural networks (the application was the processing of
sensor data from whiskers)
* It was very interesting to listen to all papers in the financial
section as I know very little about this kind of area but would
like to know more.
* Also, for similar reasons, the paper on molecule docking code was
interesting as I know very little about this area.
* Tom van Court of Altera gave a nice overview of the various tools
that try to convert some form of C to hardware.

* I also got to meet a few people from comp.arch.fpga :)

* Finally, I got a nice book from the Synopsys representative.
"Advanced FPGA Design" by Steve Kilts. It contains a nice writeup
of some important details which are typically ignored or glossed over
in many textbooks. (Such as clock domain crossings.)



/Andreas
 
I guess that people in this group might be interested in
hearing about this years FPL conference.

* All of the keynotes were interesting, especially the
SETI and CERN keynotes.
* The CERN keynotes contained lots of details about the LHC which I hadn't
heard before. One interesting detail: The FPGAs close to one of the
detectors could not be cooled using fans because of the insane magnetic
field.
* The SETI talk partly described the FPGA based infrastructure used by
the "Center for Astronomy Signal Processing and Electronics Research".
casper.berkeley.edu has more information, including source code and board
schematics/layouts.

* Some other interesting presentations I attended:
* Martin Langhammer from Altera presented a very interesting paper about a
floating point datapath compiler. By removing parts of the normalization
and denormalization it is possible to reduce the area and latency of the
datapath. Unfortunately the tool is not available yet...
* Simulating neural networks (the application was the processing of
sensor data from whiskers)
* It was very interesting to listen to all papers in the financial
section as I know very little about this kind of area but would
like to know more.
* Also, for similar reasons, the paper on molecule docking code was
interesting as I know very little about this area.
* Tom van Court of Altera gave a nice overview of the various tools
that try to convert some form of C to hardware.

* I also got to meet a few people from comp.arch.fpga :)

* Finally, I got a nice book from the Synopsys representative.
"Advanced FPGA Design" by Steve Kilts. It contains a nice writeup
of some important details which are typically ignored or glossed over
in many textbooks. (Such as clock domain crossings.)



/Andreas
 
I guess that people in this group might be interested in
hearing about this years FPL conference.

* All of the keynotes were interesting, especially the
SETI and CERN keynotes.
* The CERN keynotes contained lots of details about the LHC which I hadn't
heard before. One interesting detail: The FPGAs close to one of the
detectors could not be cooled using fans because of the insane magnetic
field.
* The SETI talk partly described the FPGA based infrastructure used by
the "Center for Astronomy Signal Processing and Electronics Research".
casper.berkeley.edu has more information, including source code and board
schematics/layouts.

* Some other interesting presentations I attended:
* Martin Langhammer from Altera presented a very interesting paper about a
floating point datapath compiler. By removing parts of the normalization
and denormalization it is possible to reduce the area and latency of the
datapath. Unfortunately the tool is not available yet...
* Simulating neural networks (the application was the processing of
sensor data from whiskers)
* It was very interesting to listen to all papers in the financial
section as I know very little about this kind of area but would
like to know more.
* Also, for similar reasons, the paper on molecule docking code was
interesting as I know very little about this area.
* Tom van Court of Altera gave a nice overview of the various tools
that try to convert some form of C to hardware.

* I also got to meet a few people from comp.arch.fpga :)

* Finally, I got a nice book from the Synopsys representative.
"Advanced FPGA Design" by Steve Kilts. It contains a nice writeup
of some important details which are typically ignored or glossed over
in many textbooks. (Such as clock domain crossings.)



/Andreas
 
I guess that people in this group might be interested in
hearing about this years FPL conference.

* All of the keynotes were interesting, especially the
SETI and CERN keynotes.
* The CERN keynotes contained lots of details about the LHC which I hadn't
heard before. One interesting detail: The FPGAs close to one of the
detectors could not be cooled using fans because of the insane magnetic
field.
* The SETI talk partly described the FPGA based infrastructure used by
the "Center for Astronomy Signal Processing and Electronics Research".
casper.berkeley.edu has more information, including source code and board
schematics/layouts.

* Some other interesting presentations I attended:
* Martin Langhammer from Altera presented a very interesting paper about a
floating point datapath compiler. By removing parts of the normalization
and denormalization it is possible to reduce the area and latency of the
datapath. Unfortunately the tool is not available yet...
* Simulating neural networks (the application was the processing of
sensor data from whiskers)
* It was very interesting to listen to all papers in the financial
section as I know very little about this kind of area but would
like to know more.
* Also, for similar reasons, the paper on molecule docking code was
interesting as I know very little about this area.
* Tom van Court of Altera gave a nice overview of the various tools
that try to convert some form of C to hardware.

* I also got to meet a few people from comp.arch.fpga :)

* Finally, I got a nice book from the Synopsys representative.
"Advanced FPGA Design" by Steve Kilts. It contains a nice writeup
of some important details which are typically ignored or glossed over
in many textbooks. (Such as clock domain crossings.)



/Andreas
 
I guess that people in this group might be interested in
hearing about this years FPL conference.

* All of the keynotes were interesting, especially the
SETI and CERN keynotes.
* The CERN keynotes contained lots of details about the LHC which I hadn't
heard before. One interesting detail: The FPGAs close to one of the
detectors could not be cooled using fans because of the insane magnetic
field.
* The SETI talk partly described the FPGA based infrastructure used by
the "Center for Astronomy Signal Processing and Electronics Research".
casper.berkeley.edu has more information, including source code and board
schematics/layouts.

* Some other interesting presentations I attended:
* Martin Langhammer from Altera presented a very interesting paper about a
floating point datapath compiler. By removing parts of the normalization
and denormalization it is possible to reduce the area and latency of the
datapath. Unfortunately the tool is not available yet...
* Simulating neural networks (the application was the processing of
sensor data from whiskers)
* It was very interesting to listen to all papers in the financial
section as I know very little about this kind of area but would
like to know more.
* Also, for similar reasons, the paper on molecule docking code was
interesting as I know very little about this area.
* Tom van Court of Altera gave a nice overview of the various tools
that try to convert some form of C to hardware.

* I also got to meet a few people from comp.arch.fpga :)

* Finally, I got a nice book from the Synopsys representative.
"Advanced FPGA Design" by Steve Kilts. It contains a nice writeup
of some important details which are typically ignored or glossed over
in many textbooks. (Such as clock domain crossings.)



/Andreas
 
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