EDK : FSL macros defined by Xilinx are wrong

I guess that people in this group might be interested in
hearing about this years FPL conference.

* All of the keynotes were interesting, especially the
SETI and CERN keynotes.
* The CERN keynotes contained lots of details about the LHC which I hadn't
heard before. One interesting detail: The FPGAs close to one of the
detectors could not be cooled using fans because of the insane magnetic
field.
* The SETI talk partly described the FPGA based infrastructure used by
the "Center for Astronomy Signal Processing and Electronics Research".
casper.berkeley.edu has more information, including source code and board
schematics/layouts.

* Some other interesting presentations I attended:
* Martin Langhammer from Altera presented a very interesting paper about a
floating point datapath compiler. By removing parts of the normalization
and denormalization it is possible to reduce the area and latency of the
datapath. Unfortunately the tool is not available yet...
* Simulating neural networks (the application was the processing of
sensor data from whiskers)
* It was very interesting to listen to all papers in the financial
section as I know very little about this kind of area but would
like to know more.
* Also, for similar reasons, the paper on molecule docking code was
interesting as I know very little about this area.
* Tom van Court of Altera gave a nice overview of the various tools
that try to convert some form of C to hardware.

* I also got to meet a few people from comp.arch.fpga :)

* Finally, I got a nice book from the Synopsys representative.
"Advanced FPGA Design" by Steve Kilts. It contains a nice writeup
of some important details which are typically ignored or glossed over
in many textbooks. (Such as clock domain crossings.)



/Andreas
 
I guess that people in this group might be interested in
hearing about this years FPL conference.

* All of the keynotes were interesting, especially the
SETI and CERN keynotes.
* The CERN keynotes contained lots of details about the LHC which I hadn't
heard before. One interesting detail: The FPGAs close to one of the
detectors could not be cooled using fans because of the insane magnetic
field.
* The SETI talk partly described the FPGA based infrastructure used by
the "Center for Astronomy Signal Processing and Electronics Research".
casper.berkeley.edu has more information, including source code and board
schematics/layouts.

* Some other interesting presentations I attended:
* Martin Langhammer from Altera presented a very interesting paper about a
floating point datapath compiler. By removing parts of the normalization
and denormalization it is possible to reduce the area and latency of the
datapath. Unfortunately the tool is not available yet...
* Simulating neural networks (the application was the processing of
sensor data from whiskers)
* It was very interesting to listen to all papers in the financial
section as I know very little about this kind of area but would
like to know more.
* Also, for similar reasons, the paper on molecule docking code was
interesting as I know very little about this area.
* Tom van Court of Altera gave a nice overview of the various tools
that try to convert some form of C to hardware.

* I also got to meet a few people from comp.arch.fpga :)

* Finally, I got a nice book from the Synopsys representative.
"Advanced FPGA Design" by Steve Kilts. It contains a nice writeup
of some important details which are typically ignored or glossed over
in many textbooks. (Such as clock domain crossings.)



/Andreas
 
I guess that people in this group might be interested in
hearing about this years FPL conference.

* All of the keynotes were interesting, especially the
SETI and CERN keynotes.
* The CERN keynotes contained lots of details about the LHC which I hadn't
heard before. One interesting detail: The FPGAs close to one of the
detectors could not be cooled using fans because of the insane magnetic
field.
* The SETI talk partly described the FPGA based infrastructure used by
the "Center for Astronomy Signal Processing and Electronics Research".
casper.berkeley.edu has more information, including source code and board
schematics/layouts.

* Some other interesting presentations I attended:
* Martin Langhammer from Altera presented a very interesting paper about a
floating point datapath compiler. By removing parts of the normalization
and denormalization it is possible to reduce the area and latency of the
datapath. Unfortunately the tool is not available yet...
* Simulating neural networks (the application was the processing of
sensor data from whiskers)
* It was very interesting to listen to all papers in the financial
section as I know very little about this kind of area but would
like to know more.
* Also, for similar reasons, the paper on molecule docking code was
interesting as I know very little about this area.
* Tom van Court of Altera gave a nice overview of the various tools
that try to convert some form of C to hardware.

* I also got to meet a few people from comp.arch.fpga :)

* Finally, I got a nice book from the Synopsys representative.
"Advanced FPGA Design" by Steve Kilts. It contains a nice writeup
of some important details which are typically ignored or glossed over
in many textbooks. (Such as clock domain crossings.)



/Andreas
 
I guess that people in this group might be interested in
hearing about this years FPL conference.

* All of the keynotes were interesting, especially the
SETI and CERN keynotes.
* The CERN keynotes contained lots of details about the LHC which I hadn't
heard before. One interesting detail: The FPGAs close to one of the
detectors could not be cooled using fans because of the insane magnetic
field.
* The SETI talk partly described the FPGA based infrastructure used by
the "Center for Astronomy Signal Processing and Electronics Research".
casper.berkeley.edu has more information, including source code and board
schematics/layouts.

* Some other interesting presentations I attended:
* Martin Langhammer from Altera presented a very interesting paper about a
floating point datapath compiler. By removing parts of the normalization
and denormalization it is possible to reduce the area and latency of the
datapath. Unfortunately the tool is not available yet...
* Simulating neural networks (the application was the processing of
sensor data from whiskers)
* It was very interesting to listen to all papers in the financial
section as I know very little about this kind of area but would
like to know more.
* Also, for similar reasons, the paper on molecule docking code was
interesting as I know very little about this area.
* Tom van Court of Altera gave a nice overview of the various tools
that try to convert some form of C to hardware.

* I also got to meet a few people from comp.arch.fpga :)

* Finally, I got a nice book from the Synopsys representative.
"Advanced FPGA Design" by Steve Kilts. It contains a nice writeup
of some important details which are typically ignored or glossed over
in many textbooks. (Such as clock domain crossings.)



/Andreas
 
I guess that people in this group might be interested in
hearing about this years FPL conference.

* All of the keynotes were interesting, especially the
SETI and CERN keynotes.
* The CERN keynotes contained lots of details about the LHC which I hadn't
heard before. One interesting detail: The FPGAs close to one of the
detectors could not be cooled using fans because of the insane magnetic
field.
* The SETI talk partly described the FPGA based infrastructure used by
the "Center for Astronomy Signal Processing and Electronics Research".
casper.berkeley.edu has more information, including source code and board
schematics/layouts.

* Some other interesting presentations I attended:
* Martin Langhammer from Altera presented a very interesting paper about a
floating point datapath compiler. By removing parts of the normalization
and denormalization it is possible to reduce the area and latency of the
datapath. Unfortunately the tool is not available yet...
* Simulating neural networks (the application was the processing of
sensor data from whiskers)
* It was very interesting to listen to all papers in the financial
section as I know very little about this kind of area but would
like to know more.
* Also, for similar reasons, the paper on molecule docking code was
interesting as I know very little about this area.
* Tom van Court of Altera gave a nice overview of the various tools
that try to convert some form of C to hardware.

* I also got to meet a few people from comp.arch.fpga :)

* Finally, I got a nice book from the Synopsys representative.
"Advanced FPGA Design" by Steve Kilts. It contains a nice writeup
of some important details which are typically ignored or glossed over
in many textbooks. (Such as clock domain crossings.)



/Andreas
 
I guess that people in this group might be interested in
hearing about this years FPL conference.

* All of the keynotes were interesting, especially the
SETI and CERN keynotes.
* The CERN keynotes contained lots of details about the LHC which I hadn't
heard before. One interesting detail: The FPGAs close to one of the
detectors could not be cooled using fans because of the insane magnetic
field.
* The SETI talk partly described the FPGA based infrastructure used by
the "Center for Astronomy Signal Processing and Electronics Research".
casper.berkeley.edu has more information, including source code and board
schematics/layouts.

* Some other interesting presentations I attended:
* Martin Langhammer from Altera presented a very interesting paper about a
floating point datapath compiler. By removing parts of the normalization
and denormalization it is possible to reduce the area and latency of the
datapath. Unfortunately the tool is not available yet...
* Simulating neural networks (the application was the processing of
sensor data from whiskers)
* It was very interesting to listen to all papers in the financial
section as I know very little about this kind of area but would
like to know more.
* Also, for similar reasons, the paper on molecule docking code was
interesting as I know very little about this area.
* Tom van Court of Altera gave a nice overview of the various tools
that try to convert some form of C to hardware.

* I also got to meet a few people from comp.arch.fpga :)

* Finally, I got a nice book from the Synopsys representative.
"Advanced FPGA Design" by Steve Kilts. It contains a nice writeup
of some important details which are typically ignored or glossed over
in many textbooks. (Such as clock domain crossings.)



/Andreas
 
I guess that people in this group might be interested in
hearing about this years FPL conference.

* All of the keynotes were interesting, especially the
SETI and CERN keynotes.
* The CERN keynotes contained lots of details about the LHC which I hadn't
heard before. One interesting detail: The FPGAs close to one of the
detectors could not be cooled using fans because of the insane magnetic
field.
* The SETI talk partly described the FPGA based infrastructure used by
the "Center for Astronomy Signal Processing and Electronics Research".
casper.berkeley.edu has more information, including source code and board
schematics/layouts.

* Some other interesting presentations I attended:
* Martin Langhammer from Altera presented a very interesting paper about a
floating point datapath compiler. By removing parts of the normalization
and denormalization it is possible to reduce the area and latency of the
datapath. Unfortunately the tool is not available yet...
* Simulating neural networks (the application was the processing of
sensor data from whiskers)
* It was very interesting to listen to all papers in the financial
section as I know very little about this kind of area but would
like to know more.
* Also, for similar reasons, the paper on molecule docking code was
interesting as I know very little about this area.
* Tom van Court of Altera gave a nice overview of the various tools
that try to convert some form of C to hardware.

* I also got to meet a few people from comp.arch.fpga :)

* Finally, I got a nice book from the Synopsys representative.
"Advanced FPGA Design" by Steve Kilts. It contains a nice writeup
of some important details which are typically ignored or glossed over
in many textbooks. (Such as clock domain crossings.)



/Andreas
 
I guess that people in this group might be interested in
hearing about this years FPL conference.

* All of the keynotes were interesting, especially the
SETI and CERN keynotes.
* The CERN keynotes contained lots of details about the LHC which I hadn't
heard before. One interesting detail: The FPGAs close to one of the
detectors could not be cooled using fans because of the insane magnetic
field.
* The SETI talk partly described the FPGA based infrastructure used by
the "Center for Astronomy Signal Processing and Electronics Research".
casper.berkeley.edu has more information, including source code and board
schematics/layouts.

* Some other interesting presentations I attended:
* Martin Langhammer from Altera presented a very interesting paper about a
floating point datapath compiler. By removing parts of the normalization
and denormalization it is possible to reduce the area and latency of the
datapath. Unfortunately the tool is not available yet...
* Simulating neural networks (the application was the processing of
sensor data from whiskers)
* It was very interesting to listen to all papers in the financial
section as I know very little about this kind of area but would
like to know more.
* Also, for similar reasons, the paper on molecule docking code was
interesting as I know very little about this area.
* Tom van Court of Altera gave a nice overview of the various tools
that try to convert some form of C to hardware.

* I also got to meet a few people from comp.arch.fpga :)

* Finally, I got a nice book from the Synopsys representative.
"Advanced FPGA Design" by Steve Kilts. It contains a nice writeup
of some important details which are typically ignored or glossed over
in many textbooks. (Such as clock domain crossings.)



/Andreas
 
I guess that people in this group might be interested in
hearing about this years FPL conference.

* All of the keynotes were interesting, especially the
SETI and CERN keynotes.
* The CERN keynotes contained lots of details about the LHC which I hadn't
heard before. One interesting detail: The FPGAs close to one of the
detectors could not be cooled using fans because of the insane magnetic
field.
* The SETI talk partly described the FPGA based infrastructure used by
the "Center for Astronomy Signal Processing and Electronics Research".
casper.berkeley.edu has more information, including source code and board
schematics/layouts.

* Some other interesting presentations I attended:
* Martin Langhammer from Altera presented a very interesting paper about a
floating point datapath compiler. By removing parts of the normalization
and denormalization it is possible to reduce the area and latency of the
datapath. Unfortunately the tool is not available yet...
* Simulating neural networks (the application was the processing of
sensor data from whiskers)
* It was very interesting to listen to all papers in the financial
section as I know very little about this kind of area but would
like to know more.
* Also, for similar reasons, the paper on molecule docking code was
interesting as I know very little about this area.
* Tom van Court of Altera gave a nice overview of the various tools
that try to convert some form of C to hardware.

* I also got to meet a few people from comp.arch.fpga :)

* Finally, I got a nice book from the Synopsys representative.
"Advanced FPGA Design" by Steve Kilts. It contains a nice writeup
of some important details which are typically ignored or glossed over
in many textbooks. (Such as clock domain crossings.)



/Andreas
 
I guess that people in this group might be interested in
hearing about this years FPL conference.

* All of the keynotes were interesting, especially the
SETI and CERN keynotes.
* The CERN keynotes contained lots of details about the LHC which I hadn't
heard before. One interesting detail: The FPGAs close to one of the
detectors could not be cooled using fans because of the insane magnetic
field.
* The SETI talk partly described the FPGA based infrastructure used by
the "Center for Astronomy Signal Processing and Electronics Research".
casper.berkeley.edu has more information, including source code and board
schematics/layouts.

* Some other interesting presentations I attended:
* Martin Langhammer from Altera presented a very interesting paper about a
floating point datapath compiler. By removing parts of the normalization
and denormalization it is possible to reduce the area and latency of the
datapath. Unfortunately the tool is not available yet...
* Simulating neural networks (the application was the processing of
sensor data from whiskers)
* It was very interesting to listen to all papers in the financial
section as I know very little about this kind of area but would
like to know more.
* Also, for similar reasons, the paper on molecule docking code was
interesting as I know very little about this area.
* Tom van Court of Altera gave a nice overview of the various tools
that try to convert some form of C to hardware.

* I also got to meet a few people from comp.arch.fpga :)

* Finally, I got a nice book from the Synopsys representative.
"Advanced FPGA Design" by Steve Kilts. It contains a nice writeup
of some important details which are typically ignored or glossed over
in many textbooks. (Such as clock domain crossings.)



/Andreas
 
I guess that people in this group might be interested in
hearing about this years FPL conference.

* All of the keynotes were interesting, especially the
SETI and CERN keynotes.
* The CERN keynotes contained lots of details about the LHC which I hadn't
heard before. One interesting detail: The FPGAs close to one of the
detectors could not be cooled using fans because of the insane magnetic
field.
* The SETI talk partly described the FPGA based infrastructure used by
the "Center for Astronomy Signal Processing and Electronics Research".
casper.berkeley.edu has more information, including source code and board
schematics/layouts.

* Some other interesting presentations I attended:
* Martin Langhammer from Altera presented a very interesting paper about a
floating point datapath compiler. By removing parts of the normalization
and denormalization it is possible to reduce the area and latency of the
datapath. Unfortunately the tool is not available yet...
* Simulating neural networks (the application was the processing of
sensor data from whiskers)
* It was very interesting to listen to all papers in the financial
section as I know very little about this kind of area but would
like to know more.
* Also, for similar reasons, the paper on molecule docking code was
interesting as I know very little about this area.
* Tom van Court of Altera gave a nice overview of the various tools
that try to convert some form of C to hardware.

* I also got to meet a few people from comp.arch.fpga :)

* Finally, I got a nice book from the Synopsys representative.
"Advanced FPGA Design" by Steve Kilts. It contains a nice writeup
of some important details which are typically ignored or glossed over
in many textbooks. (Such as clock domain crossings.)



/Andreas
 
Structural simulation of FFT core reveal the frequency to bin (XK_IDX)
mapping are bit reversed when the FFT core is configured to output in
streaming, natural order. Real time swapping of the frequency needs
FIFO of 2^N deep. Can anyone help me to implement a more optimized
freq swap method.
Click to expand...
FFTs are - as a result of the nature of the Cooley-Tukey algorithm -
either natural-in+reversed-out or reversed-in+natural-out. To design an
architecture that does natural-in+natural-out without a buffer memory is
distinctly non-trivial. Try asking on a DSP newsgroup...
 
Rob <BertyBooster@googlemail.com> wrote:
Hi fellow forumers,

We currently have lots of designs implemented with different versions
of ISE. Often when a bug needs to be fixed on an old design the
engineer will check out the code and find that it was last compiled
with an older version of ISE. The user will therefore usually migrate
to the latest version they have installed on their computer. In the
past some designs have simply not built because of things like syntax
changes with UCF files, but I am also worried about more subtle
problems that might arise from using the newer ISE version.
Also, when compiling large designs, a user's computer is utilised
quite heavily (especially memory) limiting what can be done on that PC
until the build finishes.

For these reasons I was thinking of having an "ISE build PC" which has
all of the versions of ISE we use installed on it. Then, using build
scripts (tcl??), the build process can be automated and the process
will be 100% repeatable and can be performed on an expensive behemoth
PC rather than the user's work station.
Click to expand...
* Virtualized pc with a drive image for each "setup" like xen, kvm etc..
http://en.wikipedia.org/wiki/Kernel-based_Virtual_Machine

* Network boot with different setups (PXE).

This way all the software instances will think they have the machine for
themselfes.
 
* Virtualized pc with a drive image for each "setup" like xen, kvm etc..
http://en.wikipedia.org/wiki/Kernel-based_Virtual_Machine
Click to expand...
Definitely -- Eventually the different ISEs will require different OS
releases or at least different versions of cygwin.

PCs in general are hostile to supporting more than one version of
anything.

--
mac the naďf
 
If it were me, I'd use one parallel, and one USB. Or two USB. Two
parallel adapters on one PC is asking for trouble...
Click to expand...
Two USB cables are not supported as far as I know. I am not sure about 2
parallel. I did try using 1 USB and 1 parallel in the past and it worked.


/Mikhail
 
Alex Colvin <alexc@theworld.com> wrote:
* Virtualized pc with a drive image for each "setup" like xen, kvm etc..
http://en.wikipedia.org/wiki/Kernel-based_Virtual_Machine

Definitely -- Eventually the different ISEs will require different OS
releases or at least different versions of cygwin.

PCs in general are hostile to supporting more than one version of
anything.
Click to expand...
Things PC lacks solid support for:
* Serial or ethernet boot console.
* Efficient instruction set (compare to mips/arm).
* Virtualisation.

As for the default software side it tend to be single minded in all respects.

But it's cheap, and there was a saying in the 80's:
.. No one got fired for buying IBM.
Which the decision makers seem to subscribe to.
 
"knight" <krsheshu@gmail.com> wrote in message
news:9435ad0e-1a3b-4397-96e3-02d522d01268@e39g2000hsf.googlegroups.com...
Hi

how can i represent any number in 32 bit signed 1QN format..
Let the number be 1.5


From web search...
Click to expand...
http://www.actel.com/ipdocs/CoreCORDIC_DS.pdf
Table 3
HTH., Syms.
 
Rob <BertyBooster@googlemail.com> wrote:

Hi fellow forumers,

We currently have lots of designs implemented with different versions
of ISE. Often when a bug needs to be fixed on an old design the
engineer will check out the code and find that it was last compiled
with an older version of ISE. The user will therefore usually migrate
to the latest version they have installed on their computer. In the
past some designs have simply not built because of things like syntax
changes with UCF files, but I am also worried about more subtle
problems that might arise from using the newer ISE version.
Also, when compiling large designs, a user's computer is utilised
quite heavily (especially memory) limiting what can be done on that PC
until the build finishes.

For these reasons I was thinking of having an "ISE build PC" which has
all of the versions of ISE we use installed on it. Then, using build
scripts (tcl??), the build process can be automated and the process
will be 100% repeatable and can be performed on an expensive behemoth
PC rather than the user's work station.

The thing is, I'm not sure how to implement such a thing, or indeed
whether it is a sensible plan. I've had a look through the Xilinx Tcl
stuff and there doesn't seem to be a way of getting a version for the
tools that are being invoked.
Has anyone implemented anything like this? Is it sensible??
Click to expand...
This is not difficult. Setting the 'Xilinx' environment variable is
enough to select the proper build tools. When using a batch file to
build a design this is fairly easy. If you use terminal server, you
could create a user for each ISE version and set the environment
variable accordingly.

--
Programmeren in Almere?
E-mail naar nico@nctdevpuntnl (punt=.)
 
50 000 is really a small number, typical for a 16-bit LFSR. Nothing
stops you from making the LFSR much longer, like 40 to 100 bits, which
pushes the repetition out millions and trillions of times.
Peter Alfke
Click to expand...
Try the Mersenne Twistor for a really long LFSR-type sequence.

Note that such pseudo-randum number generators are not, in fact, random.
And not suitable for use in cryptography.

--
mac the naďf
 
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