EDK : FSL macros defined by Xilinx are wrong

[KJ]

"fazulu deen" <fazulu.vlsi@gmail.com> wrote in message
news:795cb9ce-b5b6-4659-9c8e-dc4cb1b27b1b@v26g2000prm.googlegroups.com...
Hai,

Do u mean to say that for communication and multimedia application i
can design a FIR low pass or High pass or band pass or band reject
filter with cutoff frequency fall anywhere inbetween 0.0001hz to
100Ghz?

I highly doubt it.

KJ

 

[Andreas Ehliar]

On 2008-06-03, Ambreen Ashfaq Afridi <amboafridi@gmail.com> wrote:

hi all,
Im working on a project in FPGAs called "network Traffic Manager" in
verilog implemented in virtex 4. Im using trimode ethernet MAC core in
it. Now i have to send a packet via ethernet to the other machine and
recalculate the checksum. For that i have to first calculate the
cheksum. Now the problem is that im a bit confused as to which
algorithm should I use to calculate the cheksum. I started to work on
TCP/IP checksum algo but now im totally confused b/w TCP/IP checksum
and CRC. So can anyone tell me which algo shud i use?

Normally the ethernet MAC will take care of the CRC, so you will only
need to care about the TCP/IP checksums.

/Andreas

 

[Andreas Ehliar]

On 2008-06-03, Ambreen Ashfaq Afridi <amboafridi@gmail.com> wrote:

hi all,
Im working on a project in FPGAs called "network Traffic Manager" in
verilog implemented in virtex 4. Im using trimode ethernet MAC core in
it. Now i have to send a packet via ethernet to the other machine and
recalculate the checksum. For that i have to first calculate the
cheksum. Now the problem is that im a bit confused as to which
algorithm should I use to calculate the cheksum. I started to work on
TCP/IP checksum algo but now im totally confused b/w TCP/IP checksum
and CRC. So can anyone tell me which algo shud i use?

Normally the ethernet MAC will take care of the CRC, so you will only
need to care about the TCP/IP checksums.

/Andreas

 

[HT-Lab]

<ghuardian@gmail.com> wrote in message
news:81f41ef2-8141-4126-8cb5-8e663854d1f9@e53g2000hsa.googlegroups.com...

Hi, I`m trying to make a temporal simulation ( Post place & route
model ) of a FPGA designed in Xilinx 9.2i in Modelsim 6.0, but the
Modelsim gives me an error of type Error - (vsim 3193), refered from a
library called swifpli_mti.dll wich Modelsim doesn´t find.

I suspect that Modelsim 6.0 (released in 2004) PLI is incompatible with
ISE9.2i (released in 2007?), is there any reason why you have to use 6.0?

The manual described how to setup the swift interface, search the manual for
Smartmodel.

Hans
www.ht-lab.com

 

[HT-Lab]

"whygee" <whygee@yg.yg> wrote in message
news:4845edb4$0$21147$7a628cd7@news.club-internet.fr...

Hello,
I'm sorry for this post but I don't want to rant for nothing,
being the optimistic guy that some people know...

I have finally got the ProAsic3 kit that I ordered in december.
When powered up, it displays some stuff on a 1x8 LCD
and blinks LEDs. Wow, I can do the same with a dumb PIC.

Now, I see that the kit has a 250K IC, and not a 1500K one.
I just looked at the invoice and it was never clear
what version was ordered (just "A3P-EVAL-KIT").
I feel really dumb, part one.

Yes, the Actel webpage clearly states the A3P-EVAL-KIT comes with a soldered
A3P250 which is not particular big. However, the good news is that they use
the PQ208 package so you might be able to change it for a A3P1000.

The huge box contains boxes, air, foam...
they could have spared 2x the volume, hence shipping,
as well as a CDROM : i get Libero 8.1 and 8.2.
Thanks...... Anyway I'm sure that the 8.2 will be
forced into me by Actel, while 8.1 will work
on the Win2K that I reserve for EDA.
Pleaaaaaaaaase don't make me install XP !

I had the same problem last year with ISE, so I am afraid that you have to
go to XP which is becoming more expensive and difficult to get.
Unfortunately Linux is still not a low-cost option.

Now, what if I built a prototype board
on top of the .1mil headers ?
Well, Actel decided that a specific board must
be done "the hard way", not using cheap and
easily soldered 0.1mil pitch predrilled boards.
They have shifted the headers 0.05 or 0.025mil
so a predrilled board can't fit. Or was it a
beginner's mistake ? (I know, I did it once).
And don't tell me it's a measure of precaution
because there are better ways to prevent a board
from being inserted the wrong way.
I feel stupid, part two.

I can stand the delay, or hack connectors.
But now how do I register the software ?
http://register.actel.com/ asks me for
"a unique software ID number [that] is located on the CD jacket".
I find it nowhere. I have looked everywhere in vain.
I feel really annoyed, part three.

Mine was on the CD carrier, I suspect you have one without a label. Speak to
your local FAE/Distributor

I think that my patience has reached the limits.
And nobody will buy this kit back, as it has already cost
me almost 400 Euros.

That is indeed quite expensive, although comparing boards/fpga's is always
difficult an equivalent S100 Spartan board can be had for as little as 45
Euros (Enterpoint Drigmorn1).

I thought that paying "the price"
would provide me with something serious. Now all I got
is a late, useless board with only 6,144 FlipFlop.

It is not that small, a 6805 + UART + simple timer (System05) only takes 40%
(50% of an 3S100),

http://members.optushome.com.au/jekent/FPGA.htm

Alternatively, you can turn it into a very simple ping-pong game

http://www.ht-lab.com/freecores/pingpong/pingpong.html

I'm sure that there are countless better Xilinx/Actel
boards, either by the makers or 3rd parties, cheaper
and immediately available. I made a choice and I stand
by it, but it's going to end soon if it does not get better.
It's not a disapointment anymore, it's deception.

Can anyone help me ?

I would suggest you speak to your Actel FAE and see if he can change it for
a Cortex-M1 board. It is a much better board and I got mine within 2 weeks
so I assume they have some in stock (at least in the UK).

Of course there is always eBay....

Hans
www.ht-lab.com



> YG

 

[KJ]

"PFC" <lists@peufeu.com> wrote in message
newsp.ub8qcrlocigqcu@apollo13.peufeu.com...

I have a few questions about Xilinx and Altera (actually Spartan-3E
versus Cyclone III) which relate to a particular project, so here are the
specifics.

snip
Also this board will be used as part of an open source project. We'll
make a board fab run and sell them so people can hack them.
I would really prefer if those guys could use free (as in beer) software
and EDK is a problem there. But, so is the small collection of free Altera
cores...

So, from my project description above, what could I do ?...

1. Benchmark both with something resembling the final design. You should
have all the logic connected to at least drive all of the external
output/inout pins and use all of the input to at least do 'something'. For
the IP that you'll be developing you'll need to generate it in a vendor
neutral way, which can usually be done (except for non-inferrable things
like PLL/DLLs). Try out the vendor specific cores for things you're missing
even if they won't necessarily be in the final design.

1a. Try not to get too wrapped around the axle about having everything
functional before moving on. There is a bit of a risk but as long nothing
is getting totally optomized away, you should be able to make a reasonable
benchmark.

2. Run the designs through place and route. Pay attention to the reports
about unneeded I/O, make sure nothing gets optomized away, make sure that IP
blocks are consuming resources (an unconnected input or output in an
internal block can make the whole thing disappear).

3. Decide on what metrics are important for your project (i.e. device cost,
clock speed, packaging, bigger parts in the same package, tool hassles,
etc.) and evaluate all the FPGA vendors based on those metrics...also may
not necessarily want to exclude the 'other guys' beside brand A and X.
They're the two biggest, not the only ones.

Kevin Jennings

 

[KJ]

"PFC" <lists@peufeu.com> wrote in message
newsp.ub8qcrlocigqcu@apollo13.peufeu.com...

I have a few questions about Xilinx and Altera (actually Spartan-3E
versus Cyclone III) which relate to a particular project, so here are the
specifics.

snip
Also this board will be used as part of an open source project. We'll
make a board fab run and sell them so people can hack them.
I would really prefer if those guys could use free (as in beer) software
and EDK is a problem there. But, so is the small collection of free Altera
cores...

So, from my project description above, what could I do ?...

1. Benchmark both with something resembling the final design. You should
have all the logic connected to at least drive all of the external
output/inout pins and use all of the input to at least do 'something'. For
the IP that you'll be developing you'll need to generate it in a vendor
neutral way, which can usually be done (except for non-inferrable things
like PLL/DLLs). Try out the vendor specific cores for things you're missing
even if they won't necessarily be in the final design.

1a. Try not to get too wrapped around the axle about having everything
functional before moving on. There is a bit of a risk but as long nothing
is getting totally optomized away, you should be able to make a reasonable
benchmark.

2. Run the designs through place and route. Pay attention to the reports
about unneeded I/O, make sure nothing gets optomized away, make sure that IP
blocks are consuming resources (an unconnected input or output in an
internal block can make the whole thing disappear).

3. Decide on what metrics are important for your project (i.e. device cost,
clock speed, packaging, bigger parts in the same package, tool hassles,
etc.) and evaluate all the FPGA vendors based on those metrics...also may
not necessarily want to exclude the 'other guys' beside brand A and X.
They're the two biggest, not the only ones.

Kevin Jennings

 

[Andreas Ehliar]

On 2008-06-04, AchatesAVC <AchatesAVC@gmail.com> wrote:

To try to test his out I thought I would plug my computer and the
board into a router. I have a C program that I wrote which picks up
and prints UDP packets sent to the appropriate port. I put the IP
address of my computer as when plugged into the router and tried to
send the packets there. However, no data seems to be getting through.
Furthermore, the absence of link up lights on both the router and the
board seem to indicate that the bord is not able to link to the
router.

At a first guess this seems like the PHY is still in reset.
Doublecheck that you have setup the reset signal correctly in
your design. (UCF file and polarity respectively.)

If that seems ok you can try to talk to the PHY via the MII as
another poster suggested.

/Andreas

 

[Symon]

"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message
news:jtif4418p6c196kebpq0d7r3rfk1n4ja3j@4ax.com...

On Thu, 5 Jun 2008 01:21:39 -0700 (PDT), fazulu deen wrote:

can i implement a FIR filter of 256-taps(all the taps clocked
synchronously),1Ghz cutoff frequency,2.5GS/s

Can you spell "surface acoustic wave"?

Hi Jonathan,

Ha, that reminds me of a DSP course some of us attended in the mid-eighties.
The lecturer chap tried to convince us that DSP was the only way to make
linear phase filters. Sadly for him, several of us knew how our colour
tellys extracted the chrominace signal!
Cheers, Syms.

 

[Nico Coesel]

PFC <lists@peufeu.com> wrote:

So I thought about Spartan-3A DSP but it has a packaging problem :
0.8mm BGA ! No way. 1mm is fine but not 0.8mm.

What's the big deal? I'm no expert, but is 0.8mm that much more
difficult to deal with than 1.0?

It adds a lot to board cost. This is a hobby project, lol.

Also this board will be used as part of an open source project.
We'll make a board fab run and sell them so people can hack them.

Interesting. Are you planning to sell blank boards or stuffed ones? Will
the PCB database be open source, or just gerber files? What particular
audio applications do you think people would use it for?

Stuffed, I doubt people would want to solder the BGA...
Open source,
And multichannel remote audio soundcard with DSP capabilities.
One of the guys is more interested in recording capabilities and I'm more

If you are going to do multi-channel audio, Xilinx may have the
advantage that you can use the LUTs as 16x1 memory instead of
flipflops. If you want to process up to 16 channels, you can use luts
as temporary storage for filter results etc. The space savings can be
huge.

--
Programmeren in Almere?
E-mail naar nico@nctdevpuntnl (punt=.)

 

[Nico Coesel]

PFC <lists@peufeu.com> wrote:

So I thought about Spartan-3A DSP but it has a packaging problem :
0.8mm BGA ! No way. 1mm is fine but not 0.8mm.

What's the big deal? I'm no expert, but is 0.8mm that much more
difficult to deal with than 1.0?

It adds a lot to board cost. This is a hobby project, lol.

Also this board will be used as part of an open source project.
We'll make a board fab run and sell them so people can hack them.

Interesting. Are you planning to sell blank boards or stuffed ones? Will
the PCB database be open source, or just gerber files? What particular
audio applications do you think people would use it for?

Stuffed, I doubt people would want to solder the BGA...
Open source,
And multichannel remote audio soundcard with DSP capabilities.
One of the guys is more interested in recording capabilities and I'm more

If you are going to do multi-channel audio, Xilinx may have the
advantage that you can use the LUTs as 16x1 memory instead of
flipflops. If you want to process up to 16 channels, you can use luts
as temporary storage for filter results etc. The space savings can be
huge.

--
Programmeren in Almere?
E-mail naar nico@nctdevpuntnl (punt=.)

 

[Symon]

"FP" <FPGA.unknown@gmail.com> wrote in message
news:c1b1e317-7bf9-48ad-af6f-4d46444e4c7a@a1g2000hsb.googlegroups.com...

I would like some suggestions on interfacing the Xilinx Spartan3
device with a DDR SDRAM. The idea is to build a controller that will
set up the DDR-SDRAM so that I can do a burst read of a page of data
into a block of internal SRAM (dual port).

Your help is appreciated

STW or at least Xilinx's website.

http://www.xilinx.com/products/devkits/HW-SPAR3ADDR2-DK-UNI-G.htm

 

[Symon]

"FP" <FPGA.unknown@gmail.com> wrote in message
news:c1b1e317-7bf9-48ad-af6f-4d46444e4c7a@a1g2000hsb.googlegroups.com...

I would like some suggestions on interfacing the Xilinx Spartan3
device with a DDR SDRAM. The idea is to build a controller that will
set up the DDR-SDRAM so that I can do a burst read of a page of data
into a block of internal SRAM (dual port).

Your help is appreciated

STW or at least Xilinx's website.

http://www.xilinx.com/products/devkits/HW-SPAR3ADDR2-DK-UNI-G.htm

 

[KJ]

"JeDi" <jaydev.shelat@gmail.com> wrote in message
news:5927360c-b4ca-488f-9019-cee1a0ed569f@a9g2000prl.googlegroups.com...

So, my question is regarding Verilog HDL coding - Is there any
recommended coding style which improves timing closure (or in other
words makes it easier for the tools to meet timing ) ??

No, there are no 'coding styles' in any language that will do anything to
improve clock cycle performance.

To improve timing you change your design to pipeline the processing. To
pipeline you break up a 'big' computation (i.e. one that takes a long time
and therefore becomes a critical timing path) into smaller ones that take
multiple clock cycles.

Kevin Jennings

 

[KJ]

"JeDi" <jaydev.shelat@gmail.com> wrote in message
news:5927360c-b4ca-488f-9019-cee1a0ed569f@a9g2000prl.googlegroups.com...

So, my question is regarding Verilog HDL coding - Is there any
recommended coding style which improves timing closure (or in other
words makes it easier for the tools to meet timing ) ??

No, there are no 'coding styles' in any language that will do anything to
improve clock cycle performance.

To improve timing you change your design to pipeline the processing. To
pipeline you break up a 'big' computation (i.e. one that takes a long time
and therefore becomes a critical timing path) into smaller ones that take
multiple clock cycles.

Kevin Jennings

 

[Andrew Smallshaw]

On 2008-06-05, Randy Yates <yates@ieee.org> wrote:

Andrew Smallshaw <andrews@sdf.lonestar.org> writes:
[...]
For all the talk of enhancing the user's experience it seems obvious
to me that MS don't give a shit about users.

Have you ever met Tux?

I prefer Beastie myself. Shackleton had the right idea about
penguins. ;-)

Seriously though the situation on Unix platforms is getting worse
by the minute. 10-15 years the toolkit wars were over and Motif
was the winner. Most apps were shifting to Motif and CDE was coming
to further standardise the UI.

However, as soon as Linux started to gain traction things started
to deteriorate again, quite probably becasue Motif wasn't free.
Now you need any number of different toolkits to cover a broad
range of apps and things like Gnome and KDE are far more substantial
bits of code than anything that went before. The net result is
that each app has a completely different appearance, works in a
different way, and the whole assembly is one great waste of memory
and processor time.

--
Andrew Smallshaw
andrews@sdf.lonestar.org

 

[jtw]

I disagree; however, I would include 'pipelining' as part of the coding
style/trick. You can also try to code such that the critical path(s) with
have small enough blocks of logic between flip-flops to enable timing
closure. You may add attributes to signals to try to coerce the synthesizer
into doing 'the right thing'; if it doesn't come automatically, you might do
some low-level coding, synthesize that, and then use the resultant edif file
as a black box to the the next level up.

Before troubling with all that, though, do some bottom-up evaluations,
particularly of things you feel will have trouble meeting timing. The tools
will often produce sub-optimal solutions when trying to solve many
simultaneous, conflicting requirements (resource location, timing, ...), and
thus have trouble for the total design. Generally, the timing performance
achieved at the chip level is less optimal that at the block level, so make
sure your blocks will meet timing. If they do, and the whole doesn't, you
might try incremental design techniques, where you solve one problem, build
on it for the next, etc... If they don't, you can try re-coding and/or
re-architecting to get the block(s) to meet timing, and then try the whole.
Solve the relatively simple problems first... and sometimes the big problems
become simple.

Other (non-coding) tricks: location constraints, multi-cycle constraints,
....

JTW

"KJ" <kkjennings@sbcglobal.net> wrote in message
news:kOY1k.3933$89.3886@nlpi069.nbdc.sbc.com...

"JeDi" <jaydev.shelat@gmail.com> wrote in message
news:5927360c-b4ca-488f-9019-cee1a0ed569f@a9g2000prl.googlegroups.com...

So, my question is regarding Verilog HDL coding - Is there any
recommended coding style which improves timing closure (or in other
words makes it easier for the tools to meet timing ) ??


No, there are no 'coding styles' in any language that will do anything to
improve clock cycle performance.

To improve timing you change your design to pipeline the processing. To
pipeline you break up a 'big' computation (i.e. one that takes a long time
and therefore becomes a critical timing path) into smaller ones that take
multiple clock cycles.

Kevin Jennings

 

[Symon]

"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message
news:8n6g44151k7l4gpf0d3ugicepo6ki93fev@4ax.com...

hi folks

You may have noticed that I've been struggling to explain
some rather basic stuff about FIR filters to someone here.
I've run out of puff, and wish to sign off by recommending
some good books.

Hi Jonathan,
There are some free ones listed here...

http://www.dspguru.com/info/books/online.htm

HTH., Syms.


p.s. The books I learnt from include:-

Crochiere and Rabiner 1983
Crochiere, R., and L. R. Rabiner. 1983.
Multirate Digital Signal Processing.
Englewood Cliffs, NJ: Prentice-Hall, Inc.

Rabiner and Gold 1975
Rabiner, L. R., and B. Gold. 1975.
Theory and Application of Digital Signal Processing.
Englewood Cliffs, NJ: Prentice-Hall, Inc.

Dunno if they're still in print though.

 

[Symon]

"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message
news:8n6g44151k7l4gpf0d3ugicepo6ki93fev@4ax.com...

hi folks

You may have noticed that I've been struggling to explain
some rather basic stuff about FIR filters to someone here.
I've run out of puff, and wish to sign off by recommending
some good books.

Hi Jonathan,
There are some free ones listed here...

http://www.dspguru.com/info/books/online.htm

HTH., Syms.


p.s. The books I learnt from include:-

Crochiere and Rabiner 1983
Crochiere, R., and L. R. Rabiner. 1983.
Multirate Digital Signal Processing.
Englewood Cliffs, NJ: Prentice-Hall, Inc.

Rabiner and Gold 1975
Rabiner, L. R., and B. Gold. 1975.
Theory and Application of Digital Signal Processing.
Englewood Cliffs, NJ: Prentice-Hall, Inc.

Dunno if they're still in print though.

 

[Nico Coesel]

PFC <lists@peufeu.com> wrote:

If you are going to do multi-channel audio, Xilinx may have the
advantage that you can use the LUTs as 16x1 memory instead of
flipflops. If you want to process up to 16 channels, you can use luts
as temporary storage for filter results etc. The space savings can be
huge.

For the FIR I will probably use some BRAM but I was looking into this the
other day and I really like the tiny FIFOs you can make with the Xilinx
parts. Very useful for me ! I can instantiate one FIFO per channel using
very little slices and it greatly simplifies my data flow. And the SRLs
are nice to make audio I²S encoders, too.

Why FIR? AFAIK it takes less logic to implement an IIR filter.

--
Programmeren in Almere?
E-mail naar nico@nctdevpuntnl (punt=.)