EDK : FSL macros defined by Xilinx are wrong

[Andreas Ehliar]

On 2008-05-20, Kolja Sulimma <ksulimma@googlemail.com> wrote:

Don't confuse architecture and coding.
The parallel linear adder chain will cost exactly the same hardware
when coded with or without the for loop.

Of course, and I believe I wrote in my original post that a for
loop will simply be unrolled. My example was merely meant to
illustrate that it is very easy to write a for loop which will
be extremely expensive in hardware even though it is only a couple
of lines of code. This is why we recommend students to avoid
for-loops in our introductory courses, it is too easy to try to
program instead of designing hardware. If you don't use a for loop
you will immediately figure out that something is not right with
your design as you are going to write 512 individual additions...

However, since you seem to have some experience with synthesizers
that support wait statements I have a question for you: How should
you implement a synchronous reset if you have a process like the
following?

always begin

always @(posedge clk);
// This is the state I want to end up with at reset time
bar <= 0;

always @(posedge clk);
bar <= bar + 1;

always @(posedge clk);
bar <= bar + 1;

always @(posedge clk);
bar <= bar + 1;
end


/Andreas

 

[Symon]

"Jon Elson" <elson@wustl.edu> wrote in message
news:483324F1.4030005@wustl.edu...

As for registering the inputs, that DOES seem to be the right thing to do,
but the binary-coded state version works fine without.
Hi Jon,

You do realise that every build can have different timing? If you're saying
DOES because of your P&R results, you MAYBE mistaken.
HTH., Syms.

 

[Andreas Ehliar]

On 2008-05-21, fazulu deen <fazulu.vlsi@gmail.com> wrote:

As per Andreas: it is always advised that FOR loops are not to be
used in RTL coding

Just to set the record straight: What I sad was that we recommend our
students in _introductory_ courses to avoid for-loops. The reason is
that we have seen too many cases of students who try to program in
VHDL or Verilog instead of designing hardware in VHDL or Verilog.
We believe that it is probably not a good idea to teach for-loops
before a student has grasped the basic concepts of hardware design
using RTL language.

As I mentioned in an earlier posting, there is nothing magical about
for loops, the synthesizer will simply unroll the loop. For-loops
(especially in conjunction with generate) can be a great way to
minimize the amount of typing.

/ANdreas

 

[Andreas Ehliar]

On 2008-05-21, fazulu deen <fazulu.vlsi@gmail.com> wrote:

As per Andreas: it is always advised that FOR loops are not to be
used in RTL coding

Just to set the record straight: What I sad was that we recommend our
students in _introductory_ courses to avoid for-loops. The reason is
that we have seen too many cases of students who try to program in
VHDL or Verilog instead of designing hardware in VHDL or Verilog.
We believe that it is probably not a good idea to teach for-loops
before a student has grasped the basic concepts of hardware design
using RTL language.

As I mentioned in an earlier posting, there is nothing magical about
for loops, the synthesizer will simply unroll the loop. For-loops
(especially in conjunction with generate) can be a great way to
minimize the amount of typing.

/ANdreas

 

[KJ]

"Jon Elson" <elson@wustl.edu> wrote in message
news:4834722D.7020006@wustl.edu...

Jim Granville wrote:

Even with input registering, you should cover ALL states,
(including the 'illegal' ones) in your state code.

That's pretty easy to do with binary coded states, but with one-hot,
and enumerating the type, how do you even SPECIFY the illegal states,
as those, by definition, would be the ones with two or more bits "hot"?

If you choose to use enumerated types in your source code you don't have a
way to specify 'illegal' states. But that misses the point, which is that
you should have a design that can not get into an 'illegal' state. In your
case you got there by violating setup time by bringing your asynchronous
input signal into more than one flop (i.e. the multiple flops that make up
your state machine).

Can you clarify 'too frequently' ?
With a 25ns clock, a couple of IPs and 5 choices, lets
take a nice round 100ns IP sample rate. (10MHz)

The external signals, all two of them are from a mechanical system,
and change slowly.

The frequency of the signals from your mechanical system are irrelevant
unless they are 0 Hz. That input signal will not be changing at any
particular time relative to the clock of your state machine so you are
guaranteed to have instances that do not meet the setup time requirements.
It doesn't matter how frequently you think those things are changing, you
have to meet setup/hold time requirements on each and every clock cycle.

Kevin Jennings

 

[KJ]

"Jon Elson" <elson@wustl.edu> wrote in message
news:4834722D.7020006@wustl.edu...

Jim Granville wrote:

Even with input registering, you should cover ALL states,
(including the 'illegal' ones) in your state code.

That's pretty easy to do with binary coded states, but with one-hot,
and enumerating the type, how do you even SPECIFY the illegal states,
as those, by definition, would be the ones with two or more bits "hot"?

If you choose to use enumerated types in your source code you don't have a
way to specify 'illegal' states. But that misses the point, which is that
you should have a design that can not get into an 'illegal' state. In your
case you got there by violating setup time by bringing your asynchronous
input signal into more than one flop (i.e. the multiple flops that make up
your state machine).

Can you clarify 'too frequently' ?
With a 25ns clock, a couple of IPs and 5 choices, lets
take a nice round 100ns IP sample rate. (10MHz)

The external signals, all two of them are from a mechanical system,
and change slowly.

The frequency of the signals from your mechanical system are irrelevant
unless they are 0 Hz. That input signal will not be changing at any
particular time relative to the clock of your state machine so you are
guaranteed to have instances that do not meet the setup time requirements.
It doesn't matter how frequently you think those things are changing, you
have to meet setup/hold time requirements on each and every clock cycle.

Kevin Jennings

 

[Andreas Ehliar]

On 2008-05-22, fazulu deen <fazulu.vlsi@gmail.com> wrote:

So u mean to say both for loop & state machine will take same number
of clock cycles and resource utilization??

Depends on how you write it, and as another poster in this thread pointed
out, some synthesizers can synthesize a process with multiple event control
statements in it. But as I have repeatedly said, the synthesizer will
unroll a for-loop. If you write

for(i=0; i < 5; i = i + 1) begin
a = f+g + a;
end

the synthesizer will replace it with

a = f[0]+g[0] + a;
a = f[1]+g[1] + a;
// And so on...

This should give you enough knowledge to answer your questions
yourself.

Wat is the advantage i get interms of number of clocks,resources if i
have more number of states??

This sounds like a typical homework problem...

/Andreas

 

[Andreas Ehliar]

On 2008-05-22, fazulu deen <fazulu.vlsi@gmail.com> wrote:

So u mean to say both for loop & state machine will take same number
of clock cycles and resource utilization??

Depends on how you write it, and as another poster in this thread pointed
out, some synthesizers can synthesize a process with multiple event control
statements in it. But as I have repeatedly said, the synthesizer will
unroll a for-loop. If you write

for(i=0; i < 5; i = i + 1) begin
a = f+g + a;
end

the synthesizer will replace it with

a = f[0]+g[0] + a;
a = f[1]+g[1] + a;
// And so on...

This should give you enough knowledge to answer your questions
yourself.

Wat is the advantage i get interms of number of clocks,resources if i
have more number of states??

This sounds like a typical homework problem...

/Andreas

 

[Mike Lewis]

<vijayant.rutgers@gmail.com> wrote in message
news:57662a9c-7a37-4470-9468-faf94a5422f7@8g2000hse.googlegroups.com...

Hi,
I am looking for some tool / ip that can give me approximate gate
count of mapper/demapper. Any helpful hint is greatly welcome.

Thanks,
Vijayant

To get a gate count ... you have to synthesize it, the synthesis will give
you an area and typical a "gate" is a 2 input NAND gate. So divide you're
total area by the area of the NAND gate and that is your gate count.

Mike

 

[Mike Lewis]

<vijayant.rutgers@gmail.com> wrote in message
news:57662a9c-7a37-4470-9468-faf94a5422f7@8g2000hse.googlegroups.com...

Hi,
I am looking for some tool / ip that can give me approximate gate
count of mapper/demapper. Any helpful hint is greatly welcome.

Thanks,
Vijayant

To get a gate count ... you have to synthesize it, the synthesis will give
you an area and typical a "gate" is a 2 input NAND gate. So divide you're
total area by the area of the NAND gate and that is your gate count.

Mike

 

[Symon]

"Kolja Sulimma" <ksulimma@googlemail.com> wrote in message
news:ffe626f9-7404-4398-a311-6308d9c2a86d@s50g2000hsb.googlegroups.com...

Thx. That is exactly what I was looking for. (Actually I need XAPP860)

Hi Kolja,

Indeed, XAPP860 is a big improvement. In fact, it strikes me that with a
little work, an initial Rx cal with a training pattern isn't necessary for
eye alignment and the V5 can dynamically align to random data by comparing
the outputs of the master and slave ISERDES. Word alignment could be
achieved by looking for known patterns in the incoming signal, e.g. F628 for
SONET.
Cheers, Syms.

 

[Symon]

"uche" <uraniumore235@hotmail.com> wrote in message
news:2530908c-024f-4c71-9f1d-5d7daa3a2d96@i36g2000prf.googlegroups.com...

I need some help with this one...

Illegal LOC on IPAD symbol "CLK" or BUFGP symbol "CLK_BUFGP"
(output signal=DONE_OBUF), IPAD-IBUFG should only be LOCed to
GCLKIOB site.

What does that mean ?

Thanks

STFW
http://www.google.com/search?q=Illegal+LOC+on+IPAD+symbol

 

[Symon]

"vikram" <vikram788@gmail.com> wrote in message
news:72422d23-86bf-4916-a7ee-ad9fb22185d4@x1g2000prh.googlegroups.com...

hello

i am using a virtex 2 pro board to implement a communication system,
and want to interface it with my pc (Matlab) via rthernet. for this
purpose, i have acquired a Xilinx Ethernet MAC ip core (OPB). i am new

blah, blah

vikram

Vikram,
You posted this 4 days ago. I worry that you haven't found a solution for
your URGENT problem. Perhaps this link would help you.
http://www.xilinx.com/company/contact.htm
You could try calling someone on the telephone. There are folks in India. I
just hope you don't get put through to some guy with a thick English accent
that you can barely understand.
HTH., Syms.

 

[Mike Lewis]

"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message
news:hvydnRGK27J_zKvVnZ2dnUVZ_uqdnZ2d@comcast.com...

vijayant.rutgers@gmail.com wrote:

I am looking for some tool / ip that can give me approximate gate
count of mapper/demapper. Any helpful hint is greatly welcome.

The traditional method for ASIC is to divide the number
of transistors by the number of transistors in a 2 input
NAND gate. For CMOS, that is four.

Good or bad, that is the usual way.

-- glen

What is your method for determining how many transistors are in the design?
My synthesis tools only give me area.

Mike

 

[Mike Lewis]

"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message
news:hvydnRGK27J_zKvVnZ2dnUVZ_uqdnZ2d@comcast.com...

vijayant.rutgers@gmail.com wrote:

I am looking for some tool / ip that can give me approximate gate
count of mapper/demapper. Any helpful hint is greatly welcome.

The traditional method for ASIC is to divide the number
of transistors by the number of transistors in a 2 input
NAND gate. For CMOS, that is four.

Good or bad, that is the usual way.

-- glen

What is your method for determining how many transistors are in the design?
My synthesis tools only give me area.

Mike

 

[Symon]

"Symon" <symon_brewer@hotmail.com> wrote in message
news:g16680$2fn$1@aioe.org...

"uche" <uraniumore235@hotmail.com> wrote in message
news:2530908c-024f-4c71-9f1d-5d7daa3a2d96@i36g2000prf.googlegroups.com...
I need some help with this one...

Illegal LOC on IPAD symbol "CLK" or BUFGP symbol "CLK_BUFGP"
(output signal=DONE_OBUF), IPAD-IBUFG should only be LOCed to
GCLKIOB site.

What does that mean ?

Thanks

STFW
http://www.google.com/search?q=Illegal+LOC+on+IPAD+symbol
Sorry, I meant STW.

Regards, Syms.

 

[Uwe Bonnes]

fazulu deen <fazulu.vlsi@gmail.com> wrote:

On May 26, 10:51 am, rickman <gnu...@gmail.com> wrote:
On May 26, 12:43 am, cheri...@gmail.com wrote:

Someone please help me out.
tell me what file am i to use.

If you want to use the JTAG port, a .BIT file won't do it.  A .BIT
file is just the raw bits used to configure the part (plus a short
header).  This can be sent to the FPGA programming port, but not
directly to the JTAG port which has its own protocol.  I don't know
the details of the correct way to program the JTAG port, but I am
pretty sure the .SVF or .XSVF files are the right ones to use although
the programming software can likely read any of the valid formats to
create the appropriate file for downloading.

The easiest way to do this is to copy the hardware and use existing
software.  If you build a programmer that works the same as the
vendor's programmer, then you can use their software.  I am pretty
sure there is info available on how to build your own. Nose around on
the Internet.  Or do you want to build your own from scratch and
create open source software?  Even then, I would use compatible
hardware.  Why reinvent the wheel or have others get new hardware to
work with your software?

Rick

hai,

Don't get confuse ....Use the .bit file to generate mcs
file(programming file) using IMPACT

xc3sprog know hoe to handle a bit file to programm XC3S and XCF via a bit
file. With some understanding of the 1532 bsdl file delivered with Xilinx
ISE installation, a plugin for XC2S shopuld be writable.

--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

 

[Uwe Bonnes]

fazulu deen <fazulu.vlsi@gmail.com> wrote:

On May 26, 10:51 am, rickman <gnu...@gmail.com> wrote:
On May 26, 12:43 am, cheri...@gmail.com wrote:

Someone please help me out.
tell me what file am i to use.

If you want to use the JTAG port, a .BIT file won't do it.  A .BIT
file is just the raw bits used to configure the part (plus a short
header).  This can be sent to the FPGA programming port, but not
directly to the JTAG port which has its own protocol.  I don't know
the details of the correct way to program the JTAG port, but I am
pretty sure the .SVF or .XSVF files are the right ones to use although
the programming software can likely read any of the valid formats to
create the appropriate file for downloading.

The easiest way to do this is to copy the hardware and use existing
software.  If you build a programmer that works the same as the
vendor's programmer, then you can use their software.  I am pretty
sure there is info available on how to build your own. Nose around on
the Internet.  Or do you want to build your own from scratch and
create open source software?  Even then, I would use compatible
hardware.  Why reinvent the wheel or have others get new hardware to
work with your software?

Rick

hai,

Don't get confuse ....Use the .bit file to generate mcs
file(programming file) using IMPACT

xc3sprog know hoe to handle a bit file to programm XC3S and XCF via a bit
file. With some understanding of the 1532 bsdl file delivered with Xilinx
ISE installation, a plugin for XC2S shopuld be writable.

--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

 

[David Spencer]

<cherin99@gmail.com> wrote in message
news:2f382c23-6f98-4197-92dc-b981fe7d4203@v26g2000prm.googlegroups.com...

I intend to build an fpga programer for the spartan fpgas of xilinx

I am not sure about the file that i should send over the jtag to
program the fpga.
I got conflicting information from 2 different forums.

Someone told me that i could either use the .bit or the .bin file.
According to him i just had to send one of these files to the jtag
programer.

Someone else told me that i would have to generate either a .svf or
a .xsvf file from the .bit file using iMPACT. According to him i
should be specifying the devices in the jtag chain in iMPACT for
generating the correct .svf file.

Your best bet (in terms of minimal work) is to port Altera's JAM player to
your programmer architecture, which is typically trivial to do. You can then
create a .svf file from iMPACT, convert this to a .jbc file using the Altera
utilities (I think you need to run 'svf2jam' followed by the JAM compiler),
and program the file with your ported JAM player. I always thought it rather
ironic that Altera provided such an easy way for in-system programming
Xilinx parts!

 

[David Spencer]

<cherin99@gmail.com> wrote in message
news:2f382c23-6f98-4197-92dc-b981fe7d4203@v26g2000prm.googlegroups.com...

I intend to build an fpga programer for the spartan fpgas of xilinx

I am not sure about the file that i should send over the jtag to
program the fpga.
I got conflicting information from 2 different forums.

Someone told me that i could either use the .bit or the .bin file.
According to him i just had to send one of these files to the jtag
programer.

Someone else told me that i would have to generate either a .svf or
a .xsvf file from the .bit file using iMPACT. According to him i
should be specifying the devices in the jtag chain in iMPACT for
generating the correct .svf file.

Your best bet (in terms of minimal work) is to port Altera's JAM player to
your programmer architecture, which is typically trivial to do. You can then
create a .svf file from iMPACT, convert this to a .jbc file using the Altera
utilities (I think you need to run 'svf2jam' followed by the JAM compiler),
and program the file with your ported JAM player. I always thought it rather
ironic that Altera provided such an easy way for in-system programming
Xilinx parts!