EDK : FSL macros defined by Xilinx are wrong

[Symon]

"kislo" <kislo02@student.sdu.dk> wrote in message
news:046b8420-5e4a-4ee8-8ca2-1903b2253991@34g2000hsf.googlegroups.com...

The IO drive level constrain specifies the drive level of a output
signal .. if i am using LVCMOS33 with a drive level of 8mA how can i
determine the the output impedance if using f.x a 50ohm characteristic
impedance of my trace?

From the IBIS files. Use them with your SI simulator.
HTH., Syms.

 

[Symon]

"kislo" <kislo02@student.sdu.dk> wrote in message
news:046b8420-5e4a-4ee8-8ca2-1903b2253991@34g2000hsf.googlegroups.com...

The IO drive level constrain specifies the drive level of a output
signal .. if i am using LVCMOS33 with a drive level of 8mA how can i
determine the the output impedance if using f.x a 50ohm characteristic
impedance of my trace?

From the IBIS files. Use them with your SI simulator.
HTH., Syms.

 

[Symon]

"kislo" <kislo02@student.sdu.dk> wrote in message
news:4bd6ea99-ffd4-45be-8208-7c52b2433bd2@y21g2000hsf.googlegroups.com...

On 27 Maj, 01:09, "Symon" <symon_bre...@hotmail.com> wrote:
"kislo" <kisl...@student.sdu.dk> wrote in message

news:046b8420-5e4a-4ee8-8ca2-1903b2253991@34g2000hsf.googlegroups.com...

The IO drive level constrain specifies the drive level of a output
signal .. if i am using LVCMOS33 with a drive level of 8mA how can i
determine the the output impedance if using f.x a 50ohm characteristic
impedance of my trace?

From the IBIS files. Use them with your SI simulator.
HTH., Syms.

i dont have any SI simulator available so how to extract the
impedance from the IBIS model ? there is alot of voltage and current
values, but what values should i use ?

STW.
http://groups.google.com/groups/search?q=impedance+ibis+group%3Acomp.arch.fpga&qt_s=Search

HTH., Syms.

 

[Symon]

"kislo" <kislo02@student.sdu.dk> wrote in message
news:4bd6ea99-ffd4-45be-8208-7c52b2433bd2@y21g2000hsf.googlegroups.com...

On 27 Maj, 01:09, "Symon" <symon_bre...@hotmail.com> wrote:
"kislo" <kisl...@student.sdu.dk> wrote in message

news:046b8420-5e4a-4ee8-8ca2-1903b2253991@34g2000hsf.googlegroups.com...

The IO drive level constrain specifies the drive level of a output
signal .. if i am using LVCMOS33 with a drive level of 8mA how can i
determine the the output impedance if using f.x a 50ohm characteristic
impedance of my trace?

From the IBIS files. Use them with your SI simulator.
HTH., Syms.

i dont have any SI simulator available so how to extract the
impedance from the IBIS model ? there is alot of voltage and current
values, but what values should i use ?

STW.
http://groups.google.com/groups/search?q=impedance+ibis+group%3Acomp.arch.fpga&qt_s=Search

HTH., Syms.

 

[MM]

"Zorjak" <Zorjak@gmail.com> wrote in message
news:275e239e-3045-4368-b0d1-8526ba3756e8@26g2000hsk.googlegroups.com...

My core folder is located in the my ise
project directory. All I I included my vhd core file in to my ise
project. After you told me this I have copied all files from core
directory to my ise directory and i tried to start compilation again.
My result is the same. I am getting the same error.

Two notes:
1. The help article you found about EDK pcores is totally irrelevant. Forget
about EDK and MPD files. You are working with basic ISE and coregen and they
have nothing to do with EDK.

2. The vhdl wrapper file generated by coregen is for simulation, not for
synthesis. You don't need to add any vhdl files to your project to be able
to use the core. What you need to add is the ngc file, although I believe it
should find it even if you don't add it explicitly. Also, ISE GUI expects
you to do this all differently. After you create a new project you can right
click in the sources pane and choose new source, then choose IP in the new
window which will open. This will start coregen and will let you generate
your core. It will also attach an xco file to the project, which is a
coregen config file for the specific core. Since you have already run the
coregen you can add the existing xco file to the project.

/Mikhail

 

[Andreas Ehliar]

On 2008-05-28, Pablo H <pablo.huerta@gmail.com> wrote:

This conferences are specially oriented to reconfigurable computing,
including FPGA technology:

In America;
http://www.reconfig.org
http://www.splconf.org/spl09/

In Europe:
http://fpl.org/
http://dcis.org/

In Spain:
http://www.jcraconf.org/

A nice list is also available at http://www.ece.ubc.ca/~stevew/conf.html

/Andreas

 

[Andreas Ehliar]

On 2008-05-28, Pablo H <pablo.huerta@gmail.com> wrote:

This conferences are specially oriented to reconfigurable computing,
including FPGA technology:

In America;
http://www.reconfig.org
http://www.splconf.org/spl09/

In Europe:
http://fpl.org/
http://dcis.org/

In Spain:
http://www.jcraconf.org/

A nice list is also available at http://www.ece.ubc.ca/~stevew/conf.html

/Andreas

 

[KJ]

"Peter Alfke" <peter@xilinx.com> wrote in message
news:e3a18ba3-db21-498c-840a-3b36ce73246f@u12g2000prd.googlegroups.com...

Is somebody trying to re-invent the wheel?

Most likely...but also most likely not in order to invent a better wheel but
to learn.

Haven't we been through this in a seemingly endless thread?

Yes

Didn't I point out two perfect and compact solutions?

Others posted solutions as well, don't take all the credit.

How much effort do we intend to waste on such a clearly-defined non-
problem ?

If you feel that you're wasting your time, then perhaps you should choose
not to do that.

KJ

 

[KJ]

"MikeWhy" <boat042-nospam@yahoo.com> wrote in message
news:Rpg%j.1342$iM3.234@flpi150.ffdc.sbc.com...

"KJ" <kkjennings@sbcglobal.net> wrote in message
news:148a2566-df59-4dc1-9644-f231a378a9eb@t54g2000hsg.googlegroups.com...
On May 28, 6:50 am, "MikeWhy" <boat042-nos...@yahoo.com> wrote:
Sorry, Guys. We're not quite done yet with the quadrature encoder. I
tried
to rewrite it as a synchronous process. The behavioral sim shows it
working
as intended. The post-route sim and onboard test don't work.
'debouncing'
never changes state in the sim. The leds don't sequence when I twist the
magic knob.


This is always a symptom of a timing problem. In your particular case
I suspect the timing of 'a' and 'b' relative to clk is not meeting the
setup/hold time requirements of the device (from your report file).
The signals 'a' and 'b' should be brought into only one flop, the
output of that flop should be fed into a second flop, the output of
that second flop can then be reliably used wherever you currently have
'a' and 'b'.

===================

'a' and 'b' are driven by a hand turned rotary encoder.

Timing analysis is not about how often things change, but when do they
change relative to whatever it is that samples them. You have three
asynchronous inputs to your design (rst, a, b). What that means is that if
I were to ask you when does rst change in relationship to the clock your
answer would be I dunno (or something more grammatically correct). The same
would be true for 'a' and 'b'.

The problem is you then use these signals directly as inputs into logic that
gets clocked. The propogation delay from the input pin through whatever
logic there is to EACH flip flop will be different so when the clock comes
along some of the flops will see the 'new' value others will miss it. On
the next clock cycle, since some of the flops may have changed state, the
net result of the logic may be different. That's why you need to
synchronize everything to the clock first and then only use the synchronized
signals. In your case, make some new signals like rst_sync, a_sync and
b_sync where you bring rst, a and b in and perform no logic at all, just
clock them into a flop (i.e. with a clocked process).

Now change your logic to use a_sync instead of 'a', b_sync instead of 'b'
and rst_sync instead of 'rst'. This means lines like this...
if (rst = '1') then
if (a /= a_prev) then
etc.

will change to this...
if (rst_sync = '1') then
if (a_sync /= a_prev) then
etc.

Make sure that the ONLY place you use 'rst', 'a', or 'b' is to generate
'rst_sync', 'a_sync' and 'b_sync'. Reset the temptation to violate this
anywhere for any reason.

Simulate and make sure things still function.

I tried buffering them into flops with concurrent statements, a_next and
b_next, and used a_next and b_next internally. This caused 'a' and 'b' to
not get routed at all, along with all logic associated with them. The
circuit was reduced to only those parts lighting the leds.

Well, for starters you can't buffer them into flops with concurrent
statements unless you did this.
rst_sync <= rst when rising_edge(clk)
Usually one would do it like this
process(clk)
begin
if rising_edge(clk) then
rst_sync <= rst;
end if;
end process;

You can of course simply add the "rst_sync <= rst;" statement to your
clocked process if you prefer inside the "elsif (clk'event and clk = '1')
then" portion.

Secondly, if things didn't get routed, it was because you didn't connect
something up properly. Had you simulated the design you would find that it
wasn't working either.

Also, is there a way to tell XST to not treat reset as a clock? I haven't
fully read up on configuration, having spent way too much time on this
little time waster.

What makes you think that it is using reset as a clock?

======
The synthesis report:

Number of GCLKs: 2 out of 24 8%

...

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
sys_rst_pin | IBUF+BUFG | 1 |
sys_clk_pin | BUFGP | 7 |
-----------------------------------+------------------------+-------+

This is not a concern. It is simply saying that it's using a buffer to
drive the reset signal because it has a lot of internal loads, just like the
clock does. It's unfortunate that it says 'clock buffer' when it means
something more like 'big honkin buffer that can drive a lot of loads'.

Kevin Jennings

 

[Symon]

"Grant Stockly" <grant@stockly.com> wrote in message
news:f7276c42-5e33-4b6e-96e1-d16afeae08cb@p25g2000pri.googlegroups.com...

If this is NOT recommended, then would 2 two bit counters (one with an
inverted clock) and a 4 bit adder be the best solution?

That's almost certainly not the 'best' solution. A better solution is to use
a DCM to double the frequency. At 10MHz input frequency, you'll need to use
its CLKFX output.

I'd like to keep my clock at 10MHz.

No you wouldn't. You'd like to keep your logic clock _enabled_ at 10MHz, but
clocked by your newly DCMed 20MHz clock.

HTH., Syms.

p.s. Designing with schematics? How quaint! ;-)

 

[Symon]

"Grant Stockly" <grant@stockly.com> wrote in message
news:9e47c9b5-5269-46ac-b640-1d85a53da66b@y22g2000prd.googlegroups.com...

p.s. Designing with schematics? How quaint! ;-)

I will learn Verilog or VHDL soon! : ) I promise!

I spent a few months pouring over the Homebrewcpu.com schematics and
now find it easy to visualize what I want to do. : )

Hi Grant,

I tell you what, if more people adopted your learning approach, there would
be fewer folks on comp.arch.fpga struggling to understand why their 'System
C' code works in ModelSIM but doesn't work in their Spartan2e. Simulation
aside, HDLs are merely great shortcuts for implementing the hardware that
the designer has visualised. For sure, I still 'see' schematics in my head
when I write my VHDL.

Going back to your original post, I'd recommend to anyone starting out
designing FPGAs to do more reading about FPGA clocking. If you can meet the
timing, the rest is junior engineering!

Cheers, Syms.

 

[Symon]

"Eric Smith" <eric@brouhaha.com> wrote in message
news:m3d4n5aqp0.fsf@donnybrook.brouhaha.com...

Peter Alfke wrote:
Grant, years ago I published a reliable clock doubler circuit, part of
the "six easy pieces" that seem to be lost.

I repeat my request that the Xilinx marketing and/or web people put all
the old stuff that they unceremoniously removed back into an archive
section of the web or FTP site.

The "six easy pieces" article is exactly the sort of thing that I was
worried would be lost. :-(

Just because application notes and white papers are old does NOT mean
that they aren't of any use to Xilinx customers.

Eric

Hey Eric,

Yeah, yeah, yeah. Sod that.

We're still waiting for the FPGA 'Six Not So Easy Pieces'.

Syms.

 

[Symon]

"Grant Stockly" <grant@stockly.com> wrote in message
news:0370016c-1f93-4cb5-ba0a-3ce58b804b3f@q27g2000prf.googlegroups.com...

I found something...

http://www.pldworld.com/_xilinx/html/tip/sixeasypieces.htm

No pictures for me. :-(

 

[Mike Lewis]

"backhus" <nix@nirgends.xyz> wrote in message
news:g1o928$c8$1@news.hs-bremen.de...

Hi Vijayant,
every "rule of thumb" you are trying to use will give you a misleading
result. Even if you just want a maximum value.

The only way to get a nearly accurate number is to synthesize your design
with an asic synthesis tool using the desired technology library.

You may use a default synthesis at first, to get an idea of the size and
gate count. These results may vary depending on your design goals. If you
want to increase speed your design may become larger. If speed is
negotiable the design may become smaller with some area optimization
constraints.

However, the result of this synthesis will be an area value (most likely
in square micro meters) because the used gates (and flipflops) heavily
vary in size and transistor count. Unless you are using a sea of gates
technology that has only nand2-elements.

To give you an idea think about this:

If you have a simple 4to1 mux, this may be synthesized with a single mux4
cell in some standard cell technologies. With a sea of gates technology
you need a bunch of nand2's for this function, plus some routing
resources.
So, how would you express the number of gates in these two cases?
The mux4 is just the solution with the minimum number of cells. depending
on your constraints the result might be any correct combination of simpler
gates.

Also, the gate count, however calculated is not relevant for production.
Only the area tells you how many chips can be fabricated on a single
waver. And the area changes with the used technology of course.
So 1000 gates in a 130nm technology yield less chips per waver than 2000
gates in a 45nm technology. (rough estimation, just to give you an idea)

So forget gate counts if you want to compare technologies.
Only use of gate counts is if you want to compare designs using the same
technology. And I mean the very same technology! (Just take a look at some
of the fruitless gate count discussions about Brand-A and Brand-X FPGAs)

Just wanted to argue on your last point .. gate count is the easiest means
to compare technologies. It will stay relatively constant from tech to tech
and you will have the nand2 area for the technology you are in so you can
roughly compare the area of a design for different technologies using the
gate count for the design.

Mike

 

[Mike Lewis]

"backhus" <nix@nirgends.xyz> wrote in message
news:g1o928$c8$1@news.hs-bremen.de...

Hi Vijayant,
every "rule of thumb" you are trying to use will give you a misleading
result. Even if you just want a maximum value.

The only way to get a nearly accurate number is to synthesize your design
with an asic synthesis tool using the desired technology library.

You may use a default synthesis at first, to get an idea of the size and
gate count. These results may vary depending on your design goals. If you
want to increase speed your design may become larger. If speed is
negotiable the design may become smaller with some area optimization
constraints.

However, the result of this synthesis will be an area value (most likely
in square micro meters) because the used gates (and flipflops) heavily
vary in size and transistor count. Unless you are using a sea of gates
technology that has only nand2-elements.

To give you an idea think about this:

If you have a simple 4to1 mux, this may be synthesized with a single mux4
cell in some standard cell technologies. With a sea of gates technology
you need a bunch of nand2's for this function, plus some routing
resources.
So, how would you express the number of gates in these two cases?
The mux4 is just the solution with the minimum number of cells. depending
on your constraints the result might be any correct combination of simpler
gates.

Also, the gate count, however calculated is not relevant for production.
Only the area tells you how many chips can be fabricated on a single
waver. And the area changes with the used technology of course.
So 1000 gates in a 130nm technology yield less chips per waver than 2000
gates in a 45nm technology. (rough estimation, just to give you an idea)

So forget gate counts if you want to compare technologies.
Only use of gate counts is if you want to compare designs using the same
technology. And I mean the very same technology! (Just take a look at some
of the fruitless gate count discussions about Brand-A and Brand-X FPGAs)

Just wanted to argue on your last point .. gate count is the easiest means
to compare technologies. It will stay relatively constant from tech to tech
and you will have the nand2 area for the technology you are in so you can
roughly compare the area of a design for different technologies using the
gate count for the design.

Mike

 

[Symon]

"mk" <kal*@dspia.*comdelete> wrote in message
newspp044h31mfnk52ge8dopsj135jh21od2r@4ax.com...

On Fri, 30 May 2008 01:31:51 +0100, "Symon" <symon_brewer@hotmail.com
wrote:

"Grant Stockly" <grant@stockly.com> wrote in message
http://www.pldworld.com/_xilinx/html/tip/sixeasypieces.htm

No pictures for me. :-(


This seems to be problem with firefox. Internet explorer manages to
view site correctly with the embedded images.

OK, got it! thanks guys.

 

[jtw]

Are they really totally asynchronous (for treatment)? I have found that
sometimes I care, but just not to the extent that the tools would
automatically force it. So, instead of a TIG, I might create a multi-cycle
constraint. This relieves the pressure on the routing tool, but may still
keep the tool from doing really stupid things, such as placing the interface
logic parts far apart on the die.

JTW

"Barry" <barry374@gmail.com> wrote in message
news:36949c5d-23f2-400e-bc96-eaec566585e9@j22g2000hsf.googlegroups.com...
On May 30, 11:37 am, Kevin Neilson
<kevin_neil...@removethiscomcast.net> wrote:

NET "*fifo/wclk" TNM="write_stuff";
NET "*fifo/rclk" TNM="read_stuff";
TIMESPEC "TS_false_path7"=FROM "write_stuff" TO "read_stuff" TIG;
TIMESPEC "TS_false_path8"=FROM "read_stuff" TO "write_stuff" TIG;

-Kevin

Thanks, Kevin. After some research, I came up with something
similar. It appears to work, and relieves me of having to keep track
of every asynchronous register.
Barry

NET "pci_clk" TNM = FFS pci_clk_grp;
NET "ddr2_clk0" TNM = FFS ddr2_clk0_grp;
NET "ilb_clk" TNM = FFS ilb_clk_grp;
TIMESPEC TS_false_path1 = FROM pci_clk_grp TO ddr2_clk0_grp TIG;
TIMESPEC TS_false_path2 = FROM pci_clk_grp TO ilb_clk_grp TIG;
TIMESPEC TS_false_path3 = FROM ddr2_clk0_grp TO pci_clk_grp TIG;
TIMESPEC TS_false_path4 = FROM ddr2_clk0_grp TO ilb_clk_grp TIG;
TIMESPEC TS_false_path5 = FROM ilb_clk_grp TO pci_clk_grp TIG;
TIMESPEC TS_false_path6 = FROM ilb_clk_grp TO ddr2_clk0_grp TIG;

 

[Icky Thwacket]

"fazulu deen" <fazulu.vlsi@gmail.com> wrote in message
news:04f3b99d-e815-4d7e-b9ea-9cc1a2fc6795@l28g2000prd.googlegroups.com...

Hai,

What is the cutoff frequency range setted for communication and
multimedia application??

Between 0.00001 Hz or less and 100GHz or greater depending on the
application

And which is the optimal FIR filter design
method suited for that??

Variable ratio multitap with adaptive confocal formalized feedback

 

[Icky Thwacket]

"fazulu deen" <fazulu.vlsi@gmail.com> wrote in message
news:8a769af7-bae0-4b22-b2fa-5eab42bc1a26@w34g2000prm.googlegroups.com...
Hai,

Between 0.00001 Hz or less and 100GHz or greater depending on the
application

Can i say the cutoff frequency range can fall anywhere inbetween
0.0001hz to 100Ghz for communication and multimedia application..??

Yes probably

Variable ratio multitap with adaptive confocal formalized feedback

can u suggest among the following which is the optimal filter design
method for the above applications..
1.equiripple
2.window
3.constant least squares
4.complex equiripple
5.interpolated FIR

Over the frequency range in question, probably a generalized mix of all of
them.

 

[Icky Thwacket]

"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message
news:ra8244hivnivfr1cas3spthtolgnts05v2@4ax.com...

On Sat, 31 May 2008 09:48:17 +0100, "Icky Thwacket" wrote:

And which is the optimal FIR filter design
method suited for that??

Variable ratio multitap with adaptive confocal formalized feedback

Really? In fairness to the OP we ought to mention the
possibility of polyglobular phase-incontrovertible
Tchebyshev locus diagrams. I find them invaluable for
completing my sub-fusc harmonic variance charts for
phase-denibulized channels.
--

Yes you are right - forgot about that one - thanks for reminding me. --
although I don't think they are quite as accurate in the sub Hz range due to
non convergence of the cyclohelical semidisquashed hydronoid reciprocity
function.