EDK : FSL macros defined by Xilinx are wrong

[Symon]

http://lmgtfy.com/?q=list+of+free+news+servers

 

[Barry]

On Jul 8, 3:31 pm, Bob Smith <use...@linuxtoys.org> wrote:

Sorry if this was asked once before ....

ATT is shutting down USENET for its residential DSL subscribers.

Is there a web portal to comp.arch.fpga anywhere?

I'd have to have to pay for third-party usenet if it can be avoided.

thanks
Bob Smith



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groups.google.com

 

[Hal Murray]

In article <d41578a0-9128-4729-9f5c-c320762aaace@r33g2000yqn.googlegroups.com>,
rickman <gnuarm@gmail.com> writes:

I find there are any number of aspects of the VHDL language that I
just do not remember and I am not going to make up flash cards to help
me remember. So I drag a half dozen VHDL books around with me when I
am working on VHDL (or much less frequently, Verilog; one of the books
covers both).

I am getting tired of heaving the books up into the truck every time I
go to the lake and am starting to wonder if I should invest in some
good e-books on HDL.

What do the rest of you prefer? Do you have both? Do you still need
to rely on your books or do you pretty well have the language down
pat?

Several suggestions...

Make flash cards. I'm thinking of small files with working
examples so you can cut/paste. You only have to make one each
time you have to look something up.

Get second copies of the books to leave at the lake. (Or the
ones you use the most.)

Find a web site or 3 that has what you need.


Personally, I prefer paper if I need anything more than a memory
refresher. But it's hard to search so that only works if there
is a good index or good table of contents or I know my way around
well enough to quickly find what I'm looking for.

Different people have different preferences. I'm happy with
a data sheet printed on separate pages. A good friend hates
paper but he's happy with PDFs.

--
These are my opinions, not necessarily my employer's. I hate spam.

 

[Muhamed Alatalo]

Kun heinäluoma otti 2008 vapun keskusteluaseekseen Suomen NATO-jäsenyyden ja
lupaili, ettei kansamme ole sinne pakko mennä, jossei sitä kaipaa, on
kyseessä tietysti demokratian peruselementti. Vaan miksei Heinäluoma
samantien vaatinut asiasta kansanäänestystä myös?

Olisi jäänyt sitten jatkon Häkämiehen panikoinnit ja vaatimukset koko
Pohjolan pakkonatoisuudesta omaan arvoonsa. Nykyinen kansantahtoa pilkkanaan
pitävä pakkoliittymisuhkailut alkaa syödä myös hallintomme kykyä tajuta
kansaansa laajemmin. Kaikkein keskeisintä demokratian mukaisen
kansalaisvastustuksen tallaamisen päälle on täysin keskustelemattomuuksiin
jäänyt fakta, miksi pitää mennä yhteisöön jonka liittymisen naapurusto
tulkitsee suorastaan sodanjulistukseksi heille. Lisäksi tarpeeton
liittyminen maksaa miljoonia, joita ei haluta kansalle laskea, miksei?

Onko tilanne tulkittava siltä pohjalta, että NATO-jäsenyyden todelliset syyt
sanoi TVO:n toimitusjohtaja P. Simola YVA-kokouksesissaan:"Venäjän Majak
tuottaa 100% koko Euroopan ydinpolttoaineesta, kuten Suomen kaiken uraanin
jalosteista. Koska Majak sulkee toiminnan 2008 Putinin sanoin
kanmnattamattomana, on tilalle saatava Suomeen vastaava laitos
uraanintuotantoon, ettei Euroopan ydinvoimalat uraaninpuutoksesta pysähdy"!
Hän kertoi aikatauluksi 5vuotta! Mikä kertoo myös aiheen paniikinnomaisuuden
Häkämiehen kommenteista, koska niin OL-3 laitokselle kaavailut
plutoniumpoltot kuin Suomen isotoopijalostamo ei mahdollistu ilman maamme
NATO-jäsenyyttä.

 

[Steven Elzinga]

Ralph,

Sorry for the delay in my response. I tried the code below with ISE
5.2i sp3 targeting a 9572:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity inits is
Port ( d : in std_logic;
c : in std_logic;
q : out std_logic);
end inits;

architecture inits_arch of inits is

signal q_temp : std_logic := '1';

begin

process (c) is begin
if c'event and c = '1' then

q_temp <= d;

end if;
end process;

q <= q_temp;

end inits_arch;

The register had the INIT value of '1' attached to it. I then tried the
below code with record types:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity inits is
Port ( d1 : in std_logic_vector (4 downto 0);
d2 : in std_logic_vector (4 downto 0);
c : in std_logic;
q1 : out std_logic_vector (4 downto 0);
q2 : out std_logic_vector (4 downto 0));
end inits;

architecture inits_arch of inits is

type v_reg_type is record
-- registers
IOLatch : std_logic_vector(4 downto 0);
IOLatch2 : std_logic_vector(4 downto 0);
end record;

signal d_temp : v_reg_type;
signal q_temp : v_reg_type := (IOLatch => "11111", IOLatch2 => "11111");

begin

process (c) is begin
if c'event and c = '1' then

q_temp <= d_temp;

end if;
end process;

d_temp.IOLatch <= d1;
d_temp.IOLatch2 <= d2;

q1 <= q_temp.IOLatch;
q2 <= q_temp.IOLatch2;

end inits_arch;

The registers did not get initialized in 5.2i sp3 or in our next version
of the software. I will file a bug report on this.

As for your version of webpack not working please try the latest
version. If the register is still not initializing as suspected (not
using record types that is) please contact the hotline.

thanks

Steve


Ralph Mason wrote:

"Steven Elzinga" <steven.elzinga@xilinx.com> wrote in message
news:3EFC59CE.8090103@xilinx.com...


Ralph,

Another method (aside from passing an INIT) is to initialize the signal
that will be registered:

library ieee;
ues ieee.std_logic_1164.all;

entity ff is
port (d, c : in std_logic;
q : out std_logic);
end entity;

architecture ff_arch of ff is
signal q_temp : std_logic := '0'; -- XST will pass the proper INIT
value based off of the signal initialization
-- This INIT value is the state to
which the register will power up
-- q_temp is the signal that will be
registered
begin
:
:


Steve




Hi Steve,

With webpack 5.1 this doesn't seem to work at all. Doing this and then
looking at the report file there is no change in the init states of the
registers do not change at all.

Taking the inferred net names from the synthesis report and using a
constraints file worked fine though.

Any ideas why your approach wouldn't work for me? Perhaps I am doing
something wrong?

Thanks
Ralph

 

[William LenihanIii]

Peter --

I have no problem with the fact that these are 2 seperate product lines
which target 2 different needs, but when Xilinx states that "Spartan-3 is
basically Virtex-II, but whith a few things missing", I think Xilinx ought
to be considerate of it's customers and enumerate EXACTLY what those "....
few things missing" are. To paraphrase John Cooley (Synopsys & EDA Gadfly):
Customers can accept virtually any truth about a product as long as they
don't have to find out about it painfully.

I'm not asking for "champagne on a beer budget". What I am saying is: I've
spent a good amount of time studying champagne (Virtex-II), but I don't have
a lot of time right now to study beer (Spartan-3) from scratch. Since Xilinx
claims to be making beer by subtracting a few things from champagne, Xilinx
can save me a LOT OF TIME by just telling me what those few subtractions
are, and then I can quickly figure out if beer is what I need. My management
is experiencing a little sticker shock right now at the cost of champagne,
but if I get them hooked on the cost of beer, and we discover that beer
can't quite satisfy our tastes 6 months from now, that will be an enormous
source of grief & embarrassment that I want to avoid.

Can you comment on my list? Additions? Corrections?



"Peter Alfke" <peter@xilinx.com> wrote in message
news:3F0200FB.FF77F1E8@xilinx.com...

Xilinx has two major product lines. Virtex is for performance and
features, Spartan is for low cost. Otherwise, the architectures are very
similar.

That gives us a chance to really optimize each line. The Spartan
developers reduce the cost, accepting that this makes their devices
non-optimal for certain applications, but there is always Virtex to
deliver higher functionality and performance (at a higher price).
The Virtex designers can optimize functionality and speed, knowing that
this might increase the cost, but there is always Spartan to satisfy
less performance-critical, but more cost-sensitive applications.

There is no free lunch, in engineering almost everything is a trade-off.
But everybody still asks for champagne on a beer budget
Peter Alfke
=======================
Luiz Carlos wrote:


I'm not complaining, and I know that Xilinx wil not make a special
Spartan3 just for me. But I have the right to express what I think,
and maybe I'm not alone. Maybe there are a lot of Luizes and Rays,
maybe Xilinx will hear us and maybe, at these nanometer scales where
the pads are so big, to have all the CLBs configurable as memory is
not so significant in silicon area.

Luiz Carlos Oenning Martins
KHOMP Solutions

 

[David Brown]

"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F027B39.A0E8DD68@yahoo.com...

"Steven K. Knapp" wrote:

"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F00FDD2.C74022BD@yahoo.com...
"Nicholas C. Weaver" wrote:
That is a good point about the tools. I forget that the XC3S is only
supported in webpack in the XC3S50 now and I think only up to the
XC3S400 in the next release. I honestly don't get the idea of selling
very low cost chips and not adding them to the free tools.

Personally, I agree with your statement and have been trying to convince
the
powers that be to add additional Spartan-3 devices to WebPack. The
folks
responsible for WebPack are concerned about the total download size.
The
larger devices have multi-MB support files.

If the size of the download is the issue, there are very simple ways to
address that. One is to split the download into two parts, one for the
current configuration and one for the added support for the larger
devices. The other is just to ship the CD as you already do. I don't
think adding all the chips will blow away a CD will it? As it is, I
don't think it is very practical to ask a user to download a 150 MB
file. At least it is not practical for me to download it.

There's little doubt that multiple optional download parts is the most
elegant solution - along with the possiblity of getting everything on CD for
those that want that. However, the current WebPack is so large that a few
extra megabytes for extra part support would not make a significant
difference. And anyway, are there many companies with the resources to be
involved in fpga design, but without a permanent internet connection? Even
if it's a bit slow, you can always leave a download running overnight.

 

[Tim]

William LenihanIii wrote:

I'm not asking for "champagne on a beer budget". What I am saying is:
I've spent a good amount of time studying champagne (Virtex-II), but
I don't have a lot of time right now to study beer (Spartan-3) from
scratch.

As has been said before in the group, one of the best features
of Xilinx datasheets was the section on 'how this part differs
from the last generation.' Is that too complex for management
to get it?

 

[Tim]

Peter Alfke wrote:

I cannot understand that at all. If the question is ventilated in
public, it should be answered in public. Unless the answer is very
embarrassing...

It's like sex - can be embarrassing at first for the strongest
soul, but once you get the habit... Someone at Altera should
take a vow to answer _every_ question for, say, a week. We will
all applaud.

To paraphase Blackadder on airplanes: "I treat my Usenet
questions like I treat my women. Climb aboard twice a day
and fly them up to heaven."

 

[Luiz Carlos]

There is no free lunch, in engineering almost everything is a trade-off.
But everybody still asks for champagne on a beer budget
Peter Alfke

French champagne, please!

Luiz Carlos

 

[Luiz Carlos]

After all,
you are comparing 90 nm Spartan 3s to 150 nm VirtexIIs. It is very
possible that the S3s will run faster even with the added delays.

It doesn't look like (using the projected speeds for MicroBlaze).

I am sorry if my "nagging" is annoying. But I have watched a lot of
changes in FPGAs and have often felt they were not for the better. But
somewhere around the Virtex or VirtexII parts I started to realize that
I needed to forget about how the parts were different and focus on how
to solve my design problems using them. With that I have come to
understand that often what I saw as a limitation is more than made up
for in other areas. I am sure that Xilinx does not remove functionality
without considering the trade offs very seriously.

It's ok.
Maybe some day we can take a drink and talk about this. Better, let's
invite Peter, he can pay that french champagne! (I like beer too)

Luiz Carlos

 

[Sandeep Kulkarni]

Hello,
The synthesis tool is identifying your signal as clock and instantiating a
clock buffer. This has to be loc'ed to a gclkiob.
If you do not want the synthesiser to instantiate clock buffer, in the
synthesis options under the 'Xilinx specific options' tab, specify zero in
the 'number of clock buffer' field. This will prevent the tool to
instantiate clock buffers on its own.
The properties will show this if you have the 'show advanced properties' set
in the preference in the edit menu.

Sandeep
<hamish@cloud.net.au> wrote in message
news:3f015fc6$0$23112$5a62ac22@freenews.iinet.net.au...

Thomas <tom3@protectedfromreality.com> wrote:
ERROR:MapLib:93 - Illegal LOC on symbol "pin_cpuphase2" (pad
signal=pin_cpuphase2) or BUFGP symbol "pin_cpuphase2_bufgp" (output
signal=pin_cpuphase2_bufgp), IPAD-IBUFG should only be LOCed to
GCLKIOB
site.

so, apparently it wants that signal to be on a GCLKIOB; what would be
the
workaround to use this input as a clock without going through one of the
gclkiob pin?

You need to use a simple IBUF instead of an IBUFG. Your synthesis tool
is probably trying to be helpful. You may have to instantiate the IBUF.

Hamish
--
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au

 

[Glen Herrmannsfeldt]

"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message
news:bdrmtf$101fja$1@ID-84877.news.dfncis.de...

Marlboro> schrieb im Newsbeitrag news:ee7e56e.2@WebX.sUN8CHnE...
Hi Petter,
The speed is very slow, data is updated every 33 ms or so but the clock is
50 mhz, I think there would be no problem...

In this case you should consider using a serial adder. Uses much less
ressources.

Without more description it would be hard to say. If the whole design could
be implemented serially it would make a lot of sense. If a parallel 48 bit
output is needed, then deserializing the result will make it more
complicated.

It is interesting what people used to do. I remember a description of the
PDP-8s, a PDP-8 implemented with a serial ALU.

-- glen

 

[Paul Leventis]

I cannot understand that at all. If the question is ventilated in
public, it should be answered in public. Unless the answer is very
embarrassing...

Embarrassment has nothing to do with it. I personally think that this
newsgroup is the wrong place to attack the competitor's products -- in
general, I think both X & A are pretty well behaved, pointing out our strong
points instead of directly pointing out weaknesses in our competitor's
products. In a personal email, there is much more freedom to say what I
feel like and to venture off into opinion from fact. Plus, if I'm not 100%
sure, I can just say so and follow-up later when I find out the full answer;
in the newsgroup, you can look pretty silly when you do so (speaking from
experience...).

Most of us who post here from Altera are in the R&D side of the company, so
we're usually unaware of product positioning or the "company line" on
certain issues. When in doubt, I rather just reply offline while I wait for
a response from the apps folks.

Regards,

Paul

 

[Brian Davis]

"Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com> wrote in message
news:<omuMa.1725$zn2.469105682@twister1.starband.net>...

The non-'J' version of the XC3S50 also includes block RAM, embedded
multipliers, and 2 Digital Clock Managers (DCMs)

While you're adding things, any chance of sneaking the real differential
input terminators ( LVDS_25_DT, LDT_25_DT, etc. ) of the V2Pro into the S3 ?

Brian

P.S. And I'd personally love to see some TBUF's - Xilinx seems to have
forgotten that not only did they provide (the illusion of) tristate buffers,
but also dedicated chip-spanning routing for wide multi-source buses without
tying up routing resources.

Although their demise was not unexpected, given that they'd already been
chopped off at the knees in V2 by providing TBUF's at a vertical pitch
that didn't match the carry chain pitch.

For V3(??), how about a full set of TBUFs every N columns, instead of a
half set in every column?

 

[Al Williams]

dreamguy007@hotmail.com (Jack) wrote in message news:<b7c82826.0306271328.8bb2ef4@posting.google.com>...

hello.

i'm just getting started to learn fpga and i'm interested in dsp
design in fpga.
what small projects do you recommend to start with?
i need to define small projects so that i have goals, rather than
studying without any target.

thanks!

Have a look at http://tutor.al-williams.com -- we have several free
PLD tutorials there including info on Xilinx, Altera, Verilog, etc.

Al Williams
AWC

 

[Peter Sommerfeld]

I too have been contacted thru email everytime that my Altera ng
questions were not replied to in the group. Altera seemed to put alot
of thought into the answers. It would be nice if they replied to the
group to share the knowledge, except that maybe my questions were too
specific to be helpful to others.

-- Pete

Steve Casselman wrote:

What you should really do is count the number of times someone from Xilinx
has answered questions on the NG and the number of times you see someone
from Altera (or other vendors) answer any questions. I think you will see it
is about 100 to 1. A question about Xilinx will almost always be answered
where as a question about Altera will only be answered by some other user.
So basically you see more Xilinx questions because users know they will get
an answer by someone who knows what they are talking about. You can't say
that about Altera.

Except that I often am contacted by Altera directly rather than here in
public. I can understand why they would do that. I think you will also
find that very recently there are a lot more posts here from Altera.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[rickman]

David Brown wrote:

"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F027B39.A0E8DD68@yahoo.com...
"Steven K. Knapp" wrote:

"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F00FDD2.C74022BD@yahoo.com...
"Nicholas C. Weaver" wrote:
That is a good point about the tools. I forget that the XC3S is only
supported in webpack in the XC3S50 now and I think only up to the
XC3S400 in the next release. I honestly don't get the idea of selling
very low cost chips and not adding them to the free tools.

Personally, I agree with your statement and have been trying to convince
the
powers that be to add additional Spartan-3 devices to WebPack. The
folks
responsible for WebPack are concerned about the total download size.
The
larger devices have multi-MB support files.

If the size of the download is the issue, there are very simple ways to
address that. One is to split the download into two parts, one for the
current configuration and one for the added support for the larger
devices. The other is just to ship the CD as you already do. I don't
think adding all the chips will blow away a CD will it? As it is, I
don't think it is very practical to ask a user to download a 150 MB
file. At least it is not practical for me to download it.


There's little doubt that multiple optional download parts is the most
elegant solution - along with the possiblity of getting everything on CD for
those that want that. However, the current WebPack is so large that a few
extra megabytes for extra part support would not make a significant
difference. And anyway, are there many companies with the resources to be
involved in fpga design, but without a permanent internet connection? Even
if it's a bit slow, you can always leave a download running overnight.

Overnight does not cut it. As for the resources, it really does not
take a lot and a high speed internet connection is not even on the list
other than for this sort of download. These files are so large that the
reliability of the connection becomes a significant factor. The last
time I actually downloaded webpack, it took me about five trys and over
a week.

I know there are tools that let you restart an interrupted download, but
even then it is a real chore getting a download completed. I much
prefer to buy the CD.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Steven Elzinga]

reposting in plain text

Kris,

The value E4E4 is the hex value in the LUT that is derived from a truth
table:

inputs | output
4 3 2 1 | out
-------------
0 0 0 0 | 0
0 0 0 1 | 0
0 0 1 0 | 1
0 0 1 1 | 0
0 1 0 0 | 0
0 1 0 1 | 1
0 1 1 0 | 1
0 1 1 1 | 1
:
:

The first 8 output bits that are listed -> 1 1 1 0 0 1 0 0 is a hex
value of E4.

Steve


kris wrote:

Hi all,
If you look at the mapped netlist then the lut's are defined as
defparam NameOfLut.INIT=16'hE4E4;
does anybody know how the INIT defines the functionality of the LUT. In
other words
what does E4E4 mean?
Kris

 

[Glen Herrmannsfeldt]

"H. Peter Anvin" <hpa@zytor.com> wrote in message
news:bdr4h8$2p1$1@cesium.transmeta.com...

Followup to: <vfv8tlhpgtpk57@corp.supernews.com
By author: "Jerry" <nospam@nowhere.com
In newsgroup: comp.arch.fpga

I come from the ASIC side, and I have
something in verilog like: assign Z = (a[15:0] / b[9:0]); and I get
an
error saying the divisor must be a power of 2. Looking around, it
seems that this cannot be implemented into HW??

The limitation is with your synthesis tool, not the capabilities of
FPGA.

Any advice is appreciated.

Buy a good book on computer arithmetic and implement the
operation yourself
(or alternatively search a bit hardware around the web and you're
bound to
find some example code). Don't expect the resultant hardware to be
small.

To expand on what JonB said, there is a trade off between gate count and
number of clock cycles required to perform the operation.

To further expand...

Something that reads in Verilog like what you have above is
all-combinatorial logic, meaning no loops and no latches. Not even
microprocessors usually have combinatorial dividers, because of the
sheer amount of area required; you may want to see if you can't use a
clocked design instead. Common designs are 1, 2 or 4 bits per clock.

Algorithms like that used in the IBM 360/91 or Cray-1 could be implemented
as combinatorial dividers. An iterative algorithm like the 360/91, or
fully pipelined like the Cray-1 could also be implemented depending on the
required speed and available clock.

Possibly implemented in combination with the block RAM a reasonably
efficient implementation might be possible.

-- glen