EDK : FSL macros defined by Xilinx are wrong

[Mark McDougall]

News123 wrote:

But just imagine, you're lost in a snow storm and a cylinder of your car
is broken.
Then you won't have any CNC machine and you'd be sooo glad to not have
cheated with a CNC machine during your metalwork course.

That's fine if you've broken down in Northern America (or thereabouts).
How are you going to get elk antlers in outback Australia???

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

 

On Apr 6, 9:03 am, "Dave Wilson" <d...@noaddress.net> wrote:

"Jonathan Bromley" <jonathan.brom...@MYCOMPANY.com> wrote in message

news:4g4it4d9ah49jmotmo9btar8lmd8qoa3cm@4ax.com...



On Sun, 5 Apr 2009 21:55:21 +0200, "Xin Xiao" wrote:

Thanks, but I have to do it with schematics.....

Oh dear.  Why?

Basic Metalwork course, Lab 1:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
You are given a piece of steel approximately
5cm x 5cm x 5cm.  Your task is to construct
a steel cylinder, of diameter 3cm and length
4cm, without using a lathe.  Marks will be
deducted for any evidence that you borrowed
your friend's CNC milling machine.  Extra
credit is available for completing the task
using tools made only from elk antlers.

--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

????
If he was using Altera Quartus schematic then it would take less than 10
seconds using the LPM_COUNTER wizard - about 100 times faster than using
crap VHDL.

[sarcasm on]

An we don't need to waste any time on that simulation stuff, either

[sarcasm off]

I don't know any reasonably sized companies that would hire a person
that wasn't
well versed in an HDL. There's a reason - using an HDL is far more
productive,
portable, and re-usable.

AND... you can use off-the-shelf source code control systems with an
HDL.

I haven't drawn a schematic (other than for spice) in years. I don't
miss schematics
at all.

John Providenza

 

On 6 Apr., 09:54, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:

On Sun, 5 Apr 2009 23:42:12 -0700 (PDT), goo...@twinmail.de wrote:
Ok, you get this warning about possible dangers arising from clock
skew.
This is definitly true, and would affect your design if you would play
in the X- MHz league.
But for your 10Hz design you probably could have 64bit combinatorical
multipliers in your datapath without being bothered by clock skew
problems.

OUCH - dangerous myth... as Eilert knows well, I hope.

Clock skew is likely to lead to hold time violations,
which break the design's functionality on EACH INDIVIDUAL
clock edge.  Hold problems are not related to the time
between clocks, and cannot be fixed by running the clock
more slowly.

(Actually, some logic between your FFs would be
very useful in this case.)

Yes; hold-time fixup.  Some FPGA tools already do this for you
to some extent.

For a small, slow design, the message is clear:
USE CLOCK ENABLES.  Get your divide-by-10 circuit to
generate a synchronous pulse that is true for 1 cycle
of the 10Hz clock, and false for 9 cycles.  Use that
pulse as the clock enable for any logic that you want
to run at 1Hz.  Use the single, common 10Hz clock
as the clock input for every flip-flop in the design.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Hi Jonathan,
I wanted Xin to do some thinking for himself, but it's ok that you
pointed out the details so we can talk about it some more.

Truly, hold time violations can occur independent of the clock
frequency.
But if I remember it correctly Xilinx FPGA CLB-FFs are specified with
a hold time of '0', so I wonder if and how this can be violated?
If data changes before the clock edge, its a setup violation, and any
time after the edge it's ok.
So it's just the few ps of the rising clock itself that can lead to a
fault, which is not impossible, but quite unlikely for the average
design.
Or is there something more to consider?
______
Good design practice is to use clock enables, no doubt about that.
But sometimes the designer is forced to use normal routing ressources
to clock some FFs.
eg. DDR Data Strobe signals. A design can have lots of them and most
likely on normal IOBs.
This is a critical part of the design and needs careful investigation.
The only thing that reduces timing violation risks a little is
the fact that the strobe drives only a very limited number of clock
inputs which should be placed close together, reducing the skew to a
minimum.

So, knowledge of good design practice is one side of the medal, but
somtimes it is neccessary to take a look on the other side as well.

Regards
Eilert

 

[Brian Drummond]

On Mon, 06 Apr 2009 17:47:03 +0100, Jonathan Bromley
<jonathan.bromley@MYCOMPANY.com> wrote:

On Mon, 6 Apr 2009 17:03:28 +0100, "Dave Wilson" wrote:


I guess we'll have to agree to differ, but I gave up
serious use of schematics a decade ago and I don't miss
them even a tiny little bit.

Entity EL34 is
generic (
V_Heater : Real := 6.3;
V_grid : Real := -10;
V_scr : Real := 225;
V_anode : Real := 450;
g_m : Real := 11 -- mA/V
)
port (
Anode : signal_type;
Suppressor : signal_type;
Screen : signal_type;
Grid : signal_type;
Cathode : signal_type;
Heater1 : heater_type;
Heater2 : heater_type
)
end entity EL34;

Hmmm, I do believe schematics have their place.

Just not here.

- Brian

 

[Jonathan Bromley]

On Tue, 07 Apr 2009 13:03:18 +0100, Brian Drummond wrote:

Hmmm, I do believe schematics have their place.

LOL! But shouldn't the heater ports be LINKAGE?


--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[gabor]

On Apr 7, 3:53 am, goo...@twinmail.de wrote:

On 6 Apr., 09:54, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com
wrote:



On Sun, 5 Apr 2009 23:42:12 -0700 (PDT), goo...@twinmail.de wrote:
Ok, you get this warning about possible dangers arising from clock
skew.
This is definitly true, and would affect your design if you would play
in the X- MHz league.
But for your 10Hz design you probably could have 64bit combinatorical
multipliers in your datapath without being bothered by clock skew
problems.

OUCH - dangerous myth... as Eilert knows well, I hope.

Clock skew is likely to lead to hold time violations,
which break the design's functionality on EACH INDIVIDUAL
clock edge.  Hold problems are not related to the time
between clocks, and cannot be fixed by running the clock
more slowly.

(Actually, some logic between your FFs would be
very useful in this case.)

Yes; hold-time fixup.  Some FPGA tools already do this for you
to some extent.

For a small, slow design, the message is clear:
USE CLOCK ENABLES.  Get your divide-by-10 circuit to
generate a synchronous pulse that is true for 1 cycle
of the 10Hz clock, and false for 9 cycles.  Use that
pulse as the clock enable for any logic that you want
to run at 1Hz.  Use the single, common 10Hz clock
as the clock input for every flip-flop in the design.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Hi Jonathan,
I wanted Xin to do some thinking for himself, but it's ok that you
pointed out the details so we can talk about it some more.

Truly,  hold time violations can occur independent of the clock
frequency.
But if I remember it correctly Xilinx FPGA CLB-FFs are specified with
a hold time of '0',  so  I wonder if and how this can be violated?
If data changes before the clock edge, its a setup violation, and any
time after the edge it's ok.
So it's just the few ps of the rising clock itself that can lead to a
fault, which is not impossible, but quite unlikely for the average
design.
Or is there something more to consider?

The obvious thing to consider is the routing delay. For a global
clock net, where the delay is almost the same to every load,
the zero hold time will prevent hold violations. If your clock
uses ordinary fabric routing, it is very easy to get skews
in the nanoseconds range, definitely large enough to exceed
the data delay and cause hold violations, and as Jonathan
pointed out, this has nothing to do with the clock frequency.

______
Good design practice is to use clock enables, no doubt about that.
But sometimes the designer is forced to use normal routing ressources
to clock some FFs.
eg. DDR Data Strobe signals. A design can have lots of them and most
likely on normal IOBs.
This is a critical part of the design and needs careful investigation.
The only thing that reduces timing violation risks a little is
the fact that the strobe drives only a very limited number of clock
inputs which should be placed close together, reducing the skew to a
minimum.

So, knowledge of good design practice is one side of the medal, but
somtimes it is neccessary to take a look on the other side as well.

Regards
  Eilert

In the Xilinx world, you can have local routing for clocks over a
small
area and there is a constraint that forces use of low skew routing.

In the OP's case, even using synchronous design practices (the
counter he pulled from the library is an example of a synchronous
counter design), the circuit will not work unless the clock uses
global routing. Even if he uses a clock enable. Period.

When you design with schematics, I believe it is necessary
to place the BUFG in your clock path. It does not get inserted
automatically as it might in an HDL design where you could
just use the pin name as your clock net. This is at least how
it worked back in Foundation 4.1i, the last version with decent
(Aldec) schematics and the last time I used schematics for
any FPGA design. On those old designs I placed a pad symbol
followed by an IBUFG (for a global clock input pad) followed
by a BUFG. The BUFG output was the clock net. You could
also place an inverter at the output of the BUFG and it
would get absorbed into the clock loads (turn all those
library elements into falling-edge versions).

I hope we haven't scared away the OP with the annual
schematic v. HDL war ;-)

Regards,
Gabor

 

[Dave Wilson]

"Mark McDougall" <markm@vl.com.au> wrote in message
news:49da9eed@dnews.tpgi.com.au...

Jonathan Bromley wrote:

I guess we'll have to agree to differ, but I gave up serious use of
schematics a decade ago and I don't miss them even a tiny little bit.

Not to mention problems with re-use,

Modules designed using schematics are just as portable and re-useable as
those using an HDL

portability to other vendors,

That's the real joke - unless you design using primitives - you mean you DO?

You cannot transfer across vendors without massive rework using an HDL so
that often quoted fact is a farce.

Personally I have never had to - you mean you have?




and

version control software issues (diff anyone?).

Not a problem. each module has it's own version called from the top level

Serious PL work just isn't done in schematics.

You must be living in cloud cuckoo land - fancy a big bet?

 

[Dave Wilson]

<jprovidenza@yahoo.com> wrote in message
news:a6510994-3caf-4584-b8a0-61422f3831f3@d25g2000prn.googlegroups.com...
On Apr 6, 9:03 am, "Dave Wilson" <d...@noaddress.net> wrote:

"Jonathan Bromley" <jonathan.brom...@MYCOMPANY.com> wrote in message

news:4g4it4d9ah49jmotmo9btar8lmd8qoa3cm@4ax.com...



On Sun, 5 Apr 2009 21:55:21 +0200, "Xin Xiao" wrote:

Thanks, but I have to do it with schematics.....

Oh dear. Why?

Basic Metalwork course, Lab 1:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
You are given a piece of steel approximately
5cm x 5cm x 5cm. Your task is to construct
a steel cylinder, of diameter 3cm and length
4cm, without using a lathe. Marks will be
deducted for any evidence that you borrowed
your friend's CNC milling machine. Extra
credit is available for completing the task
using tools made only from elk antlers.

--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

????
If he was using Altera Quartus schematic then it would take less than 10
seconds using the LPM_COUNTER wizard - about 100 times faster than using
crap VHDL.

[sarcasm on]

[An we don't need to waste any time on that simulation stuff, either

[[sarcasm off]

Oh yes we do! - don't you?

[I don't know any reasonably sized companies that would hire a person
[that wasn't
[well versed in an HDL.

I work for one

[There's a reason - using an HDL is far more
[productive,

Disagree - I can design /compile /simulate faster than you

portable,

you are joking!!!!! Not without extensive rework

[and re-usable.

I reuse code all the time

[AND... you can use off-the-shelf source code control systems with an
[HDL.

Don't need to

[I haven't drawn a schematic (other than for spice) in years. I don't
[miss schematics
[at all.

I truly feel sorry for you - life must be exceedingly boring!

 

[Rob Gaddi]

On Tue, 7 Apr 2009 17:21:27 +0100
"Dave Wilson" <dave@noaddress.net> wrote:

Dave, you seem to be the only guy out here defending schematic entry.
Therefore, obviously, you're not using the horribly crippled Xilinx
schematic tool, which seems to crash more and more with each revision.

If I may ask, what schematic tool are you using, and what did it run
you? Can it handle structured port types to talk to VHDL?

--
Rob Gaddi, Highland Technology
Email address is currently out of order

 

[Dave Wilson]

"Rob Gaddi" <rgaddi@technologyhighland.com> wrote in message
news:20090407093644.00004a8b@unknown...

On Tue, 7 Apr 2009 17:21:27 +0100
"Dave Wilson" <dave@noaddress.net> wrote:

[positively about schematic entry]

Dave, you seem to be the only guy out here defending schematic entry.
Therefore, obviously, you're not using the horribly crippled Xilinx
schematic tool, which seems to crash more and more with each revision.

If I may ask, what schematic tool are you using, and what did it run
you? Can it handle structured port types to talk to VHDL?

--
Rob Gaddi, Highland Technology
Email address is currently out of order

I use Altera Quartus - been using it for the last 22 years or more -
including the old DOS version. It is a very solid integrated platform for
either schematic or HDL entry, full simulation tools etc with links to
external design tools. Yes of course you can mix HDL/schematic exactly how
you like.

You can download a free web version to try out from www.altera.com.

A full license for a years updates is around $2500, but the software is
yours - you just don't get updates/support for new devices when the license
expires.

 

[Xin Xiao]

thanks, could you point me to that xilinx documentation that explains that?

i'm using a counter as a frequency divider because I need to blink a led, so
I think I need a 1Hz clock so that the blink is visible on my FPGA.

So the solution is to connect my gated clock to each of the CE pins and
connect the CLK pin to the FPGA oscillator?

Xin

<goouse@twinmail.de> wrote in message
news:7cc6d8ac-a628-44a2-a208-9d4f1b0cac1f@v15g2000yqn.googlegroups.com...
On Apr 5, 2:16 am, "Xin Xiao" <n...@no.com> wrote:

Hello, my question is I'm making a modulo-10 counter using a CB4CLE
counter
(http://www.xilinx.com/itp/xilinx6/books/data/docs/lib/lib0080_48.html)
and
some logic gates. I am making a modulo-10 counter because I need a 1 Hz
clock for my design (the clock input to the counter is a 10 Hz signal).
The
problem is that, when I implement my design to a FPGA, my tool warns me
that
there may be a problem due to clock skew, because the clock is being
generated after a combinational network (two levels of AND gates to detect
when the counter reaches 10).

My question is simple, is there any other method to build a modulo-10
counter from CB4CLE modules or I can simply ignore the warning?

Thank,

Hi Xin,
as pointed out by KJ it is not a wise idea not to use the global clock
nets for clock signals.
However it's very tricky to do so with signals created by your own
logic.
But there is a well working solution to your problem.

Build your modulo 10 counter so, that it generates a some kind of
ripple signal that is active for only one 10Hz period.
Use this signal as a Clock Enable for all the FFs that shall run with
1Hz. The Clock for these FFs is your 10Hz Master Clock.

There are papers available, e.g. from xilinx, that discuss this method
in detail.
____
Truly, schematic input is not the method of choice for designing FPGA
logic, but it's not your fault that you are forced to use it.
If you are a student, schematics are helpful to understand digital
logic. But if that task is mixed up with understanding how FPGAs work
it is like learning to walk during an olympic sprinting competition.

_____
One more comment :
Ok, you get this warning about possible dangers arising from clock
skew.
This is definitly true, and would affect your design if you would play
in the X- MHz league.
But for your 10Hz design you probably could have 64bit combinatorical
multipliers in your datapath without being bothered by clock skew
problems.
Data would be stable way loooong before the next clock edge.
(Actually, some logic between your FFs would be very useful in this
case.)
There's a very good article in the english wikipedia about Clock Skew.
Read it for further understanding.

Have a nice synthesis
Eilert

 

[Jon Elson]

Xin Xiao wrote:

Hello, my question is I'm making a modulo-10 counter using a CB4CLE
counter
Isn't there a CD4CLE? If not, don't gate the clock, just reset the

counter whenever the count = 9. Or, preset it to 6 every time it
reaches terminal count.

Jon

 

[Antti.Lukats@googlemail.c]

On Apr 7, 7:36 pm, Rob Gaddi <rga...@technologyhighland.com> wrote:

On Tue, 7 Apr 2009 17:21:27 +0100

"Dave Wilson" <d...@noaddress.net> wrote:
[positively about schematic entry]

Dave, you seem to be the only guy out here defending schematic entry.
Therefore, obviously, you're not using the horribly crippled Xilinx
schematic tool, which seems to crash more and more with each revision.

If I may ask, what schematic tool are you using, and what did it run
you?  Can it handle structured port types to talk to VHDL?

--
Rob Gaddi, Highland Technology
Email address is currently out of order

HDL Designer
..

 

[russ]

Mark McDougall wrote:

News123 wrote:

But just imagine, you're lost in a snow storm and a cylinder of your car
is broken.
Then you won't have any CNC machine and you'd be sooo glad to not have
cheated with a CNC machine during your metalwork course.

That's fine if you've broken down in Northern America (or thereabouts).
How are you going to get elk antlers in outback Australia???

Regards,

Think out of the box. Use a 'roo rib instead

 

[Mark McDougall]

Dave Wilson wrote:

Modules designed using schematics are just as portable and re-useable
as those using an HDL

Yeah? Do your Quartus schematic designs compile under ISE?

You cannot transfer across vendors without massive rework using an HDL
so that often quoted fact is a farce.
Personally I have never had to - you mean you have?

Absolute garbage. You admit that you've never done it, and don't program
in it, yet you claim that it requires massive rework. Divine insight? I've
done it, on several occasions, with very little rework.

version control software issues (diff anyone?).
Not a problem. each module has it's own version called from the top
level

You've either missed the point entirely, or I don't understand your response.

Let me count the number of projects on opencores that are done in
schematic... hmm...

In any case, it's clear that you - against overwhelming opinion - prefer
schematic entry, and that's fine. That you have your shackles up about it
is somewhat bemusing... but each to their own...

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

 

[Manny]

On Apr 6, 5:47 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:

Schematics live in my head, as a thinking tool, and
occasionally leak out on to paper as a tool for communicating
with myself or with fellow humans.  They are a lousy design
entry tool.  And that's even before you start to deal with
the general crumminess of most schematic capture packages,
where tools for ripping and re-numbering buses are
palaeolithic, and re-use means working out how to bring
up impenetrable property sheets instead of simply patching
and commenting the generics on VHDL components.
Just finished designing a large piece of logic to do with spread

spectrum comms. The Wishbone-compliant core was completely designed in
Xilinx's SysGen which can be thought of after all as a schematic
capture environment. Control was done in m-code statemachines. You get
the added benefit of having the feature-rich Matlab environment at
your disposal for testing and simulating the design. Arithmetic type
can't be specified more easily. And oh yeah, the core is parametrized
with a top-level dialogbox; a Simulink feature. I have to admit
though, naming the wires is a bit fiddly at times. But if your
competent enough in Simulink - which I'm not - I'm sure you can even
instantiate blocks programmatically - seen it before. One last thing:
the design met timing like magic. I suppose you can get the same
quality results with endless coregen invocations. This way you just
need to have your pick from the Xilinx blockset. I read from and wrote
back to Matlab's workspace in accordance to Wishbone bus cycles using
Stateflow (statemachine) objects in Simulink. After all you can plot
and run all sorts of diagnostics on the output within Matlab and life
couldn't be easier. Try to do that in VHDL. I'm sure you can - I love
VHDL by the way - but this way it's much faster and DSP-appropriate.

-Momo

 

[Manny]

On Apr 8, 11:46 pm, Manny <mlou...@hotmail.com> wrote:

On Apr 6, 5:47 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com
wrote:> Schematics live in my head, as a thinking tool, and
occasionally leak out on to paper as a tool for communicating
with myself or with fellow humans.  They are a lousy design
entry tool.  And that's even before you start to deal with
the general crumminess of most schematic capture packages,
where tools for ripping and re-numbering buses are
palaeolithic, and re-use means working out how to bring
up impenetrable property sheets instead of simply patching
and commenting the generics on VHDL components.

Just finished designing a large piece of logic to do with spread
spectrum comms. The Wishbone-compliant core was completely designed in
Xilinx's SysGen which can be thought of after all as a schematic
capture environment. Control was done in m-code statemachines. You get
the added benefit of having the feature-rich Matlab environment at
your disposal for testing and simulating the design. Arithmetic type
can't be specified more easily. And oh yeah, the core is parametrized
with a top-level dialogbox; a Simulink feature. I have to admit
though, naming the wires is a bit fiddly at times. But if your
competent enough in Simulink - which I'm not - I'm sure you can even
instantiate blocks programmatically - seen it before. One last thing:
the design met timing like magic. I suppose you can get the same
quality results with endless coregen invocations. This way you just
need to have your pick from the Xilinx blockset. I read from and wrote
back to Matlab's workspace in accordance to Wishbone bus cycles using
Stateflow (statemachine) objects in Simulink. After all you can plot
and run all sorts of diagnostics on the output within Matlab and life
couldn't be easier. Try to do that in VHDL. I'm sure you can - I love
VHDL by the way - but this way it's much faster and DSP-appropriate.

Forgot to mention for the sake of historical credibility that there
was one block that I couldn't parametrize in the whole design. It was
a bitbasher block - for some reason, SysGen doesn't allow
parametrization to be applied on this one. I'm sure in time the Xilinx
folk will sort this out. You just need somebody to chase'em up on
this. I have neither the stamina nor the credentials for this.

-Momo

 

[Symon]

http://www.theregister.co.uk/2009/04/14/facebook_twitter_users_dunces_amoral/

"Vikram" <vkr101@gmail.com> wrote in message
news:4af78531-9571-4cd3-9437-fed73274249f@n7g2000prc.googlegroups.com...

Guys,

Wanted to let you know abou the FPGA Twitter at http://twitter.com/fpga
, it is a great way to follow what is hapenning in the FPGA world..

-Vikram

 

[Benjamin Krill]

On Thu, 2009-05-14 at 05:20 -0700, Antti wrote:

how?

in GUI can just add many UCF files they are all used
but in the cmd log only one of them is displayed?

must be some magic? I do not want to create .ISE files, need just
script file to spec multiple UCFs

Hi Antti,

I found no ise solution for that. So my solution was:

"find <src-dir> -name '*.ucf' -exec cat {} >> merged.ucf \;"

For some projects I define a variable with all ucf files
and merged these into one file. Depends on your project tree.

cheers
ben

 

[Antti.Lukats@googlemail.c]

On May 14, 3:36 pm, Benjamin Krill <b...@codiert.org> wrote:

On Thu, 2009-05-14 at 05:20 -0700, Antti wrote:
how?

in GUI can just add many UCF files they are all used
but in the cmd log only one of them is displayed?

must be some magic? I do not want to create .ISE files, need just
script file to spec multiple UCFs

Hi Antti,

I found no ise solution for that. So my solution was:

"find <src-dir> -name '*.ucf' -exec cat {} >> merged.ucf \;"

For some projects I define a variable with all ucf files
and merged these into one file. Depends on your project tree.

cheers
 ben

but this !?

when it works with ISE GUI,
it should also work from commandline???

Antti