EDK : FSL macros defined by Xilinx are wrong

[juice28]

Version 5.2 only works on windows 2000. I am using 3.2 as it seems to be
the only one that works on my setup. I have also assigned the input and
outputs to pins using the user constraints, but I did not use the ibuf and
obuf (it seemed to compile alright though) so maybe that is my problem.
Still wondering what is up with Q/ on the flip flops too.


Thanks,

Fred

"Chris Carlen" <crcarle@BOGUS.sandia.gov> wrote in message
news:be1i2j$h77$1@sass2141.sandia.gov...

juice28 wrote:
Hi all,

I am an extreme newbe to the xilinx CPLD's. I will try to explain what I
have and what I am having problems with. If someone can help out that
would
be great.

After trying to download most of the versions of webpack I finally got
version 3.8 to work on my windows 98 setup.

What version is that? I have just installed 5.2i. Are you getting the
software from Xilinx?

I am using the schematic entry and using a xilinx xc9572 in plcc44. I am
not
sure if you need to use verlog or what, but I pick one and then use the
schematic entry.

Don't need Verilog or any HDL, if you want to do a schematic.

My questions are when you make a schematic is it mandatory to use ibuf
and
obuf on your inputs and outputs.

I think so, I do it. I would be surprized if it will compile without
using IO buffers. (Pardon my lack of knowing if the right term is
"synthesize", "translate", "fit", or some combination of the above).

I will await hearing what the experts have to say on this one as well.

Also none of the flip flops have a /Q
output. Do you simply use an inverter on the Q output for Q/ ? I have
made
a couple of schematics and programmed the chip, but they do not function
as
I would expect.

When that happened to me in the beginning, it was because the software
was not using my pin assignment constraints. You should have ran a
module called "assign package pins" or something like that. I am
currently puzzled by the convoluted approach to this in Xilinx software,
which I will likely post about in a few minutes.

But basically, you need to have created a .ucf user constraints file,
through one means or another. There are GUI programs to do it, or you
can edit text. This file associates net names (signals) in your design
(schematic) with physical chip pins.

Now on older software, it was my experience that the software would not
obey my selections unless I also checked a box in the "synthesize"
propoerties (right click on "synthesize" part of the project navigator),
which was something like "use user contraints file" in the old software.

Now things are different, and even more confusing overall, but works
better by default.

You really need to use 5.2, unless it doesn't support the old CPLD you
are using?


I think that you must have to be a rocket scientist to
figure this stuff out

Yes, that is correct. Enroll in a rocket scientist course immediately!

;-)





--
_______________________________________________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov -- NOTE: Remove "BOGUS" from email address to reply.

 

[rickman]

David Brown wrote:

Personally, I agree with your statement and have been trying to
convince
the
powers that be to add additional Spartan-3 devices to WebPack. The
folks
responsible for WebPack are concerned about the total download size.
The
larger devices have multi-MB support files.

If the size of the download is the issue, there are very simple ways
to
address that. One is to split the download into two parts, one for
the
current configuration and one for the added support for the larger
devices. The other is just to ship the CD as you already do. I don't
think adding all the chips will blow away a CD will it? As it is, I
don't think it is very practical to ask a user to download a 150 MB
file. At least it is not practical for me to download it.


There's little doubt that multiple optional download parts is the most
elegant solution - along with the possiblity of getting everything on CD
for
those that want that. However, the current WebPack is so large that a
few
extra megabytes for extra part support would not make a significant
difference. And anyway, are there many companies with the resources to
be
involved in fpga design, but without a permanent internet connection?
Even
if it's a bit slow, you can always leave a download running overnight.

Overnight does not cut it. As for the resources, it really does not
take a lot and a high speed internet connection is not even on the list
other than for this sort of download. These files are so large that the
reliability of the connection becomes a significant factor. The last
time I actually downloaded webpack, it took me about five trys and over
a week.

I know there are tools that let you restart an interrupted download, but
even then it is a real chore getting a download completed. I much
prefer to buy the CD.


I fully support the option of being able to buy the CD - even for those of
us with reliable internet connections, there are times where a single CD in
the post can be more convenient. And I agree that reliability is the main
factor for the internet connection - a 57kbaud modem can download 150 MB
overnight, but only if it is reliable enough! But is it really that hard or
that expensive to get a solid line? I find it is an essential requirement
for my work - speed is not critical (we have a 386 kbit ADSL line for the
office), but reliability is.

Incidently, you might like to try NetAnts for downloading over a dodgy line,
although I'm sure everyone has there favourite download utility.

I don't know about my line being "dodgy". I just know that the
combination of ISP, phone line, modem, OS and browser software makes it
hard to get a 17 hour download to complete without error. It is also a
PITA tying up the modem connection for a day while this is going on. It
makes it very slow to browse or even get emails.

As to the effort required to get a solid data line, there is virtually
*nothing* you can do if your voice capability is not affected. I have
talked to the phone company before and they have made it clear that a
phone line is not a data line. They guarantee no specific data rate.
DSL is not available in the second largest city in Maryland and Cable
Modem is a fixed installation, it can not be easily moved from one
computer to another. Cable Modem also goes out in nearly every storm
along with the TV.

I only wish I could get connected at 57 kbps!

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[rickman]

Marc Randolph wrote:

"Paul Leventis" <paul.leventis@utoronto.ca> wrote in message news:<M7JMa.30912$a51.1242@news02.bloor.is.net.cable.rogers.com>...
Hi Dennis,

for the new multichannel filter design I have a choice -
Altera Cyclone EP1C12 ($60) or Xilinx Spartan-3 XC3S1000(???)

Here are a few key advantages for Cyclone that I can think of off the top of
my head:

- Availability. The 1C12 is in full production on a 130 um process that
we've used to manufacture 10+ different devices (including 7 Stratix
members, 4 Cyclone members, and some Apex II members)

- Performance. The _slowest_ Cyclone speed grade is 20% faster (geometric
average of fmax over many real user designs) than Spartan-3, which is
currently offered in only one speed-grade. If you need greater performance,
there are two more Cyclone speed grades available, giving you an additional
30% performance advantage.

Howdy Paul,

I love competitive comparisons, and I love Altera for continuing to
push the level of competition higher, but PLEASE, could you keep this
FUD free?

Xilinx tells everybody that the speed files that are released for the
Spartan-3 are very preliminary and quite conservative, and I'm sure
your tech people know that. This is bordering on the same level of
FUD that I got from my Altera rep about some Virtex II availability or
yield or some such nonsense early this year.

- 3.3V Tolerance. Cyclone is 3.3V tolerant, in today's silicon. PCI? No
problem.

Not quite as misleading since you put "in today's silicon", but many
would still walk away with the incorrect impression that the Spartan-3
will not be 3.3V tolerant. The truth is that it will be 3.3V by the
time most people get their hands on them (due to the current limited
availability of S3 ES silicon).

- Bitstream Compression. Regardless of your data source, you can compress
your bitstream (~2:1 ratio) to reduce the cost of your non-volatile storage
device, whether that is our low-cost, low-footprint serial configuration
devices or something else.

Especially for larger devices, this is an excellent feature. We have
a considerable amount of flash memory on our systems to hold all the
FPGA loads, and it adds up quickly. I sure wish Xilinx had it.

What about high speed I/O? Seems like you all don't push that nearly
has hard as you should. What about listing a few of the major
advantages of a non-digital PLL? Or perhaps you all have better clock
to out on block ram's? Not to mention multiple sizes of them. All of
these would be better talking points than some nebulous claim of being
30% faster than a part that is nowhere near released and whose claimed
speed is known to be artificially low.

Marc,

If you learn nothing else about dealing with IC vendors it should be
that you never, ever, EVER listen to what one vendor says about
another. Feel free to check it out yourself, but you should always
assume that any vendor will put his competition in the worst possible
light, perhaps even unfairly.

So don't blame a vendor for being a vendor. They all do it. Just learn
to be a discriminating listener. Kinda like when you watch commercials
on TV.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[David Brown]

"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F04660E.33F1EF2@yahoo.com...

David Brown wrote:

I fully support the option of being able to buy the CD - even for those
of
us with reliable internet connections, there are times where a single CD
in
the post can be more convenient. And I agree that reliability is the
main
factor for the internet connection - a 57kbaud modem can download 150 MB
overnight, but only if it is reliable enough! But is it really that
hard or
that expensive to get a solid line? I find it is an essential
requirement
for my work - speed is not critical (we have a 386 kbit ADSL line for
the
office), but reliability is.

Incidently, you might like to try NetAnts for downloading over a dodgy
line,
although I'm sure everyone has there favourite download utility.

I don't know about my line being "dodgy". I just know that the
combination of ISP, phone line, modem, OS and browser software makes it
hard to get a 17 hour download to complete without error. It is also a
PITA tying up the modem connection for a day while this is going on. It
makes it very slow to browse or even get emails.

As to the effort required to get a solid data line, there is virtually
*nothing* you can do if your voice capability is not affected. I have
talked to the phone company before and they have made it clear that a
phone line is not a data line. They guarantee no specific data rate.
DSL is not available in the second largest city in Maryland and Cable
Modem is a fixed installation, it can not be easily moved from one
computer to another. Cable Modem also goes out in nearly every storm
along with the TV.

I only wish I could get connected at 57 kbps!

Can't you use a firewall/router connected to a cable modem? Of course, it
won't fix the storm problem, and not every isp's contract will let you
connect a whole network to their system. Can you get ISDN there? I have no
real idea whether that is available in the US or not - it is popular in
Europe for businesses, and used to be common for internet access before ADSL
became so widespread. Maybe you can get radio internet connections? Many
of these are pretty ropey, but there are some ISP's here in Norway that
manage to do it well, so it's certainly possible. Other than that, I can
offer nothing but sympathy (and surprise - I knew the US had a problematic
telephone system, but I didn't know it was that bad).

 

[Peter Alfke]

This is beautiful !
I had felt like commenting, but it's so much better coming from a user.
Thanks, Rickman!
We should put our best foot forward, and be as honest as we can.
But I will not slam Altera's products. Maybe needle their people...
Have a safe Fourth of July !
Peter Alfke

rickman wrote:

Marc,

If you learn nothing else about dealing with IC vendors it should be
that you never, ever, EVER listen to what one vendor says about
another. Feel free to check it out yourself, but you should always
assume that any vendor will put his competition in the worst possible
light, perhaps even unfairly.

So don't blame a vendor for being a vendor. They all do it. Just learn
to be a discriminating listener. Kinda like when you watch commercials
on TV.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[rickman]

Andy Peters wrote:

rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F07008B.5E495267@yahoo.com>...
I just tried to install the Quartus II web edition software and I see
that to get a license I need to have an Ethernet card. Does Altera
provide for any other sort of license? It seems silly to require me to
buy and install an Ethernet interface just so they can key a license for
*free* software.

Rick -- ask the REAL question: why do they continue bother with the
licensing bullshit AT ALL, esp. for FREE SOFTWARE that enables us to
design with their chips? Rant rant rant.

If I had a nickel for every minute I've wasted on FlexLM, I'd retire.

I would very much like to rant until they dropped the licencing on the
free tools. But I feel I rant a bit too much already and I don't want
to alienate anyone (or anyone more than I have). I know that sometimes
I push buttons with Peter and Austin. I hope they don't mind too much.

I remember telling the Orcad people what I thought of their new
licensing scheme when they were bought by some larger, high end player.
The new owners felt that Orcad should have high end licensing and I let
them know that I would not be installing the upgrade because of it. I
belive it would have required me to either buy an Ethernet card or to
use a dongle. These days I am not willing to do either to use
software. But a hard drive key is within my comfort zone. I know that
if I replace my hard drive I can set my own serial number and be back on
the air without depending on them. Orcad is one company I will *never*
depend on for anything.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Spam Hater 7]

My current favorite is Mentor; their "perpetual" license must be
renewed every 5 years. (This is for their "perpetual" leonardo
license.)

I would very much like to rant until they dropped the licencing on the
free tools. But I feel I rant a bit too much already and I don't want
to alienate anyone (or anyone more than I have). I know that sometimes
I push buttons with Peter and Austin. I hope they don't mind too much.


Rick "rickman" Collins

 

[Jonathan Bromley]

"Brad Smallridge" <bsmallridge@dslextreme.com> wrote in message
news:vgbmmurk77rs22@corp.supernews.com...

A follow up:

Someone sent this solution to me and said it would provide no assymetrical
delays and would be better than a long elsif chain.

"Better" is a style choice. The "assymetrical delays" (sic) is a
canard caused by the respondent's lack of understanding of VHDL
signal assignment, I suspect. The meaning of the VHDL is the
same in both cases. As you say, a good synthesis tool should
give the same results for both (it's not really a "fitter"
problem).
Finally, any design that relies on symmetry of delay through
synthesised asynchronous logic deserves to fail.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Steve Lass]

db wrote:

I have to ask the question why XST prints such a useless message as:

FATAL_ERROR:Xstortability/export/Port_Main.h:126:1.13 - This
application has discovered an exceptional condition from which it
cannot recover. Process will terminate. To resolve this error,
please consult the Answers Database and other online resources at
http://support.xilinx.com. If you need further assistance, please open
a Webcase by clicking on the "WebCase" link at
http://support.xilinx.com
Error: XST failed

This tells me absolutely nothing about the problem. Looking at the
Xilinx website has never gleaned any useful information. I am able to
figure out the what the problem is, but I waste a lot time doing this
trying to pin down the problem when I get such uninformative messages
as above.

So if XST knows something is wrong, why is it unable to tell me.

A FATAL_ERROR means that XST terminated unexpectedly, which is why it

can't tell
you what happened.

If it
wont tell me, I certainly can not tell tech support if I want to open
a WebCase.

If you submit the design that failed, our engineers can debug the

problem and probably find
a workaround.

Steve

I hope someone from Xilinx can give me an answer to this.

 

[John_H]

The decision on what works "better" is dependent on why you need to stretch
the pulse.

If you need a signal that's big enough to be sensed in a different clock
domain, an "acknowledge" can be brought back to the first time domain to
shut the pulse back off. This assumes that two pulses won't be close enough
to interfere.

If we stick with your original approach, rather than using the |stretcher in
your construct below, I'd turn longer_pulse into a set/reset flop that's
started with the single_clock_pulse and ended with the stretcher_sr[2], i.e.

longer_pulse <= longer_pulse ? ~stretcher_sr[2] : single_clock_pulse;

Two very-close events would only produce one pulse with this arrangement
rather than the extension that you'd get with the wide or. The only reason
to use the alternative arrangement is to get the shift register in an SRL
for a Xilinx device or to reduce the width of the logic for a wider pulse
than what you're using.



"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message
news:atiOa.105$FA6.16959707@newssvr14.news.prodigy.com...

What are the best techniques for stretching single-clock pulses? Here
"best" defined as either faster or smaller logic.

I've been using the following technique with great success, the idea is to
add a few clock cycles to a pulse prior to having it cross a clock domain
or
send it somewhere where it would be safer to have it be active longer:

reg [3:0] counter;
reg single_clock_pulse;
reg [3:0] strecher_sr;
reg longer_pulse;

// Generate a test pulse
always @(posedge clock)begin
counter <= counter + 1;
single_clock_pulse <= & counter;
end

// Stretch the pulse
always @(posedge clock)begin
stretcher_sr <= {stretcher_sr[2:0], single_clock_pulse};
longer_pulse <= | stretcher_sr;
end

By changing the length of the shift register I can control the new pulse
duration. This is obviously not a good technique for very long durations.
What are some of the other techniques? Anything more "elegant" than this?

Thanks,


--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"

 

[Jean Nicolle]

I guess everyone is trying to download Quartus 3.0 at once during daytime.
The file weights 137MB and has just been released, so a busy server is
understandable today. I got it late last night and the download was very
fast.
As for Ethernet adapters, nobody likes to jump into hoops to get a software
running, but it's not so bad to buy a cheap Ethernet card, and I guess they
want to keep their licensing options open.

"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F09B67B.1E2765E4@yahoo.com...

I have not been having a good day (weekend actually) trying to download
the Altera web edition software. Large downloads like this normally
take three or so tries to get the full file.

But I find that I am not able to get a license file anyway. I don't
have an Ethernet adapter in the PC where I will be running the tools and
the web site is not set up for anything else. So what do I need to do
to get running with quartus web edition?

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Martin Euredjian]

"John_H" <johnhandwork@mail.com> wrote:

If you need a signal that's big enough to be sensed in a different clock
domain, an "acknowledge" can be brought back to the first time domain to
shut the pulse back off. This assumes that two pulses won't be close
enough
to interfere.

Right. I've used this approach in some modules, like both sides of a FIFO
operating across clock-domain boundaries. I had to resort to stretching
when the signal in question had to go to multiple desitinations and it
didn't seem practical to generate and maintain different pulse <-> ack
channels. My personal bias is that it made everything seems a bit messy.

My general approach to clock domain crossing has been to stretch the pulse
(if necessary) to guarantee that it will span several of the receiver's
clock cycles; re-sample with at least four F/F's and edge-detect. So far,
so good.

: single_clock_pulse;

Two very-close events would only produce one pulse with this arrangement
rather than the extension that you'd get with the wide or. The only
reason
to use the alternative arrangement is to get the shift register in an SRL
for a Xilinx device or to reduce the width of the logic for a wider pulse
than what you're using.

A single SRL sounds good to me.

Thanks,


--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"

 

[H. Peter Anvin]

Followup to: <bebnhi$36kqm$1@ID-61213.news.dfncis.de>
By author: "Giuseppeł" <miaooaim@inwind.it>
In newsgroup: comp.arch.fpga

cut

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

Hello Rick,

Would you care to explain how you set the serial number ?
I've looked before but never been able to find out how.

Michael Kellett
www.mkesc.co.uk


Just using the program "VOLUMEID.exe" from the www.sysinternals.com site.

For Ethernet cards, too; for most it's trivial to flash a new MAC
address permanently. You need hardware-specific tools to do it, but
virtually all modern Ethernet cards have the MAC address in a serial
EEPROM of some sort.

You can still, obviously, not have two Ethernet cards with the same
MAC address on the same network.

-hpa
--
<hpa@transmeta.com> at work, <hpa@zytor.com> in private!
"Unix gives you enough rope to shoot yourself in the foot."
Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64

 

[Peter Alfke]

You might want to look at an article I wrote some time ago:
"Moving data across asynchronous clock boundaries".
You find it among the TechXclusives.
http://support.xilinx.com/xlnx/xweb/xil_tx_home.jsp

Peter Alfke, Xilinx
============
Martin Euredjian wrote:

"John_H" <johnhandwork@mail.com> wrote:

If you need a signal that's big enough to be sensed in a different clock
domain, an "acknowledge" can be brought back to the first time domain to
shut the pulse back off. This assumes that two pulses won't be close
enough
to interfere.

Right. I've used this approach in some modules, like both sides of a FIFO
operating across clock-domain boundaries. I had to resort to stretching
when the signal in question had to go to multiple desitinations and it
didn't seem practical to generate and maintain different pulse <-> ack
channels. My personal bias is that it made everything seems a bit messy.

My general approach to clock domain crossing has been to stretch the pulse
(if necessary) to guarantee that it will span several of the receiver's
clock cycles; re-sample with at least four F/F's and edge-detect. So far,
so good.

longer_pulse <= longer_pulse ? ~stretcher_sr[2] : single_clock_pulse;

Two very-close events would only produce one pulse with this arrangement
rather than the extension that you'd get with the wide or. The only
reason
to use the alternative arrangement is to get the shift register in an SRL
for a Xilinx device or to reduce the width of the logic for a wider pulse
than what you're using.

A single SRL sounds good to me.

Thanks,

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"

 

[John]

The ssp0 core has a mir interface within. You need to assign the
addresses for
the mir registers. I.E:

BEGIN opb_core_ssp0
PARAMETER INSTANCE = opb_core_ssp0_1
PARAMETER HW_VER = 1.00.b
PARAMETER c_BASEADDR = 0x21000000
PARAMETER c_HIGHADDR = 0x210000ff
PARAMETER c_mir_BASEADDR = 0x21000100
PARAMETER c_mir_HIGHADDR = 0x210001ff
PORT opb_clk = sys_clk
PORT led = led
BUS_INTERFACE SOPB = opb
END


Matthias Dyer wrote:

Hello,

We are trying to implement an OPB slave user core as described in the
"User
Core Template Reference Guide" (Jan 2003). We are using the template
"opb_core_ssp0_v1_00_a". We have connected the user core to the OPB
Bus of a
Microblaze system (generated with Xilinx EDK3.2 SP1 tools). Now, having
this core as the only opb slave on the bus causes no problems. But
when we
connect other pre-build peripherials such as the "uart-lite", our core
interfers somehow with the other cores. In particular the uart output is
croped after 16 chars if our user core is present. This is a weird
behavior
since our core should have a well defined opb addres space and does only
read from the opb and does not write to it.

This effect even occurs when we take an empty user core template!

Have anyone had the same experience or can anyone help?

Thanks a lot and best regards,

Matthias

 

[John]

dataOut <= dataForRead when (doAread = '1') else
(others => 'Z');

Muhammad Khan wrote:

HI Fellows,
The process given below is to read and write to Vertex device ( only
vhdl part is shown here not C ). I want to tristate SR_DATA_IO_int
when not driven as read.
First of all the code below for write and read is correct or not!!!!
SR_DATA_IO_int pins ( which are 32 , I am using upper 7 bits only )
will be acting as bi directional pins. While writing these will take
bits from PCI interface to device and while reading they will exactly
opposite. But while writing I have to tristate SR_DATA_IO_int so as to
avoid short circuiting. Any help on tristate will be highly
appreciated.


process(CLK_2X,SR_ADDR_IO_int,SR_DATA_IO_int,SR_IRD_int,SR_IWR_int,SR_IVCS_V3_int)
begin
if RISING_EDGE(CLK_2X) then
if SR_IVCS_V3_int = '0' then
if SR_IWR_int = '0' then
if SR_ADDR_IO_int = "001100" then
RESULT <= SR_DATA_IO_int(6 downto 0);
End if ;
Elsif SR_IRD_int = '0' then
if SR_ADDR_IO_int = "001101" then
SR_DATA_IO_int(6 downto 0)<=RESULT ;
End if;
End if;
End if;
End if;

 

[John]

Be carefull. Usually when you instantiate a ibufg, you are actually
instantiating a IOB configured as an input, and a bufg. You only want to use an
IOB as the input and make sure it is loc'd to a clk input pin location.

As for your div/2, you can divide the input to the dll by 2 using the
CLKIN_DIVIDE_BY_2 parameter. Don't know if this helps because the clk0 will be
div/2 since the dll is dividing the input to the dll.





Markus Meng wrote:

Hi All,

some notes I could not figure out directly from one of the XAPP132, 174
from Xilinx. If I want to drive an Off-Chip device with half of the clkin
frequency
without using a GBUF driver, can I feedback the devided signal from the obuf
driving the pin through an IBUFG and still having the DLL functionality of
phase
shift an duty cycle correction. I read that the feedback signam MUST be
clkout
or 2xclkout. The problem is that I am running out of GBUF's in my design ...

markus

 

[Noel Klonsky]

Hey guys, I'd recommend that splitting up your design into smaller
projects is not the way to proceed, IMHO. You are just going to
complicate your design and make it more difficult to simulate.

How much memory does your PC have? What's the processor? Is the hard
disk working a lot during compilation? Check the memory usage using
the Task Manager: see if the machine is running out of RAM and paging
to hard disk. If so, you should buy some more RAM: RAM is cheap, far
cheaper than messing around with your project to get it to compile in
a smaller memory space. Paging to hard disk will slow down compilation
vastly (perhaps by a factor of 10 or more).

You should alsi install DK2.0 SP1 and PDK 2.0. PDK 2.0 has a new
standard library with more efficient implementations (in terms of
compilation time) of the useful macros.

Don't use the netlist simulator: this is old and has not been updated
for a while. I think it is provided by Celoxica merely for backwards
compatibility or for long-term users. The new simulator simulates a
lot faster and is much more stable. Also, the netlist simulator cannot
simulate multiple projects at once any more than the new simulator
can.

Make sure you have the latest version of the Xilinx tools with the
latest service packs.

Things you can look for are: heavy use of recursive macros. These
should be avoided as they take a lot of time and memory to compile.
Read the Celoxica Knowledge Base (http://www.celoxica.com/support) for
tips on optimising your design: there is plenty of useful information
there. Sometimes optimisations that produce more efficient code can
also bring down the compilation time.

Good designing

Noel



"Alan Fitch" <alan.fitch@doulos.com> wrote in message news:<bdpbf9$m5c$1$8302bc10@news.demon.co.uk>...

"P. Prasad" <pprasad@chandra.cse.iitb.ac.in> wrote in
message
newsine.GSO.4.40.0306212128530.29004-100000@chandra.cse.iitb.ac.in...
Hi,
I am working on a HANDELC project on Xilinx FPGA(RC1000
board) and using Celoxica's DK1 environment. I have some
doubts regarding HANDELC. I am new to HANDELC and FPGA.


The Problem
-----------

As the project is getting bigger and bigger, the
compilation(synthesis into EDIF) time is taking many hours.
So the goal is to reduce the compilation time.


My experience of this is that people don't think enough
about hardware.
For instance, if you divide by 2^12, I have seen code where
people write

A = B /4096;

This will result in HandelC attempting to synthesise a large
divider.
This is a) very slow in hardware b) very slow to compile.

So my first suggestion is to look through your code for
"sillies" like this.
You can get big clues by getting the timing and area reports
from DK1 and
correlating them with the code you've written.

(By the way, the above line should be

A = B << 12;

which essentially synthesises to some wires!)

So step one is to check the code for sensible "hardware"
style coding.


The approach which I tried to use was to break up the
program into smaller parts, compile these into separate
EDIFs and hook them into the main HANDELC program using
interfaces(ports). So the parts of the program which have
already been synthesized into EDIF do not take any time at
all thus saving lot of time.

But I am doing some mistake in my code and I am clueless
to what is wrong. Actually I feel that I need to synchronise
the EDIF component with the main HANDELC program but don't
know how ( maybe use interfaces properly???). I have given
below the detailed description of the things I tried.

You approach makes sense. Remember that you need to create
separate
mains (i.e. separate projects) in DK1 to create separate
EDIF netlists.

Secondly, when you combine everything, you cannot simulate
it in
the C simulator - you would have to simulate it in the
netlist simulator.

I guess in your example below, you are talking about "actual
hardware"
rather than simulation?

So step 2 is to check you are using the netlist simulator.

Other than that, your code looks sensible,

regards

Alan

--
Alan Fitch
HDL Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification *
Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood,
Hampshire, BH24 1AW, UK
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http://www.doulos.com

The contents of this message may contain personal views
which are not the
views of Doulos Ltd., unless specifically stated.

 

[Khim Bittle]

On Mon, 7 Jul 2003 21:41:57 -0400, "Jerry" <nospam@nowhere.com> wrote:

I have searched around the net (googled groups and web) for an existing eCOS
port for
Altera's NIOS. Did find on the red hat site some limited discussion about
somebody wanting to port.
Altera's web site had a press release about supporting an eCOS port for NIOS
but no ported code.

Is there any interest in this group about an eCOS port? Right now we are
using a RTOS that has
royalties associated with it which is bad for my profit sharing.

Is this the proper group to bring this subject up? Is there anybody out
there that would participate in a port?

regards
Jerry

have you tried uCOSII ?

>

 

[Steve Casselman]

What does "multiple" mean?

More than one column. There is a load multiple column command. This loads
columns that are contigous to each other. Usually the reconfiguration
process loads one column on the left side of the die and then one on the
right side of the die. This is to distribute the current evenly over the
chip.

If I take the 30 ms boundary seriuosly a full (re)configuration would
destroy the device )
A full configuration loads one side then the other.

Is it possible to create a reconfigurable design with a static and a
dynamically changed
module arranged on top of each other (share the same columns)?

Actually, it should work with differential bitstreams due to the fact that
only bits are toggled
that where modified.

You answered your own question. The answer is "yes." The "static" bits of
the design would just get reloaded as they are.

Steve