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There are designs that in reality don't need a reset, but do in simulation.always @ (posedge(clkin))
clkout <= ~clkout;
above is a single clk_div module, but when I do simulation, I can't get it
work.
I know the reason. without a reset signal to give it a initial value of
'0'
or '1', the clkout will keep the value 'x' during simulation.
but there's no 'x' in FPGA or CPLD, the clkout will get whatever a value
after power up, and it can get work without additional reset.
Doing floating point in an FPGA is pretty expensive (in terms of CLBs used).Hi,
I'm a student in computer science and I'm working on the Singular Value
Decomposition. I have implementd the Brent Luk Van Loan SVD systolic array
using HandelC on FPGA and I'm looking for existing FPGA or VLSI
implementations to compare with.
Does anyone know about hardware implementaions of the SVD ?
If you needed a lower frequency couldn't you always generate a power of two
multiple of it, and then divide that down?
-- glen
What's the voltage on your supply rails/planes on the sideThe problem is the output of the PBGA seem to be producing a 1HZ pulse
which is expected when the 28V is on but not expected when the 28V is
turned off. The 1HZ pulse has a amplitude of 2V when the 28V is off
but when the 28V is on, the amplitude is 5V.
I have tested the power supply stand-alone and it works perfectly.
When the 28V is off, the PBGA power should be zero but in this case,
the voltage is 1.4V when connected to the PCB.
I can guarantee you that neither Xilinx nor Altera harbors this kind ofOften vendors don't want to seem like they are hawking their wares
here.
Split the download, or switch the devcie files to bePersonally, I agree with your statement and have been trying to convince the
powers that be to add additional Spartan-3 devices to WebPack. The folks
responsible for WebPack are concerned about the total download size. The
larger devices have multi-MB support files.
I too have been contacted thru email everytime that my Altera ng
questions were not replied to in the group. Altera seemed to put alot
of thought into the answers. It would be nice if they replied to the
group to share the knowledge, except that maybe my questions were too
specific to be helpful to others.
I don't really have allot of time to spend with this now (it's working finereposting in plain text
Ralph,
Sorry for the delay in my response. I tried the code below with ISE
5.2i sp3 targeting a 9572:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity inits is
Port ( d : in std_logic;
c : in std_logic;
q : out std_logic);
end inits;
architecture inits_arch of inits is
signal q_temp : std_logic := '1';
begin
process (c) is begin
if c'event and c = '1' then
q_temp <= d;
end if;
end process;
q <= q_temp;
end inits_arch;
The register had the INIT value of '1' attached to it. I then tried the
below code with record types:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity inits is
Port ( d1 : in std_logic_vector (4 downto 0);
d2 : in std_logic_vector (4 downto 0);
c : in std_logic;
q1 : out std_logic_vector (4 downto 0);
q2 : out std_logic_vector (4 downto 0));
end inits;
architecture inits_arch of inits is
type v_reg_type is record
-- registers
IOLatch : std_logic_vector(4 downto 0);
IOLatch2 : std_logic_vector(4 downto 0);
end record;
signal d_temp : v_reg_type;
signal q_temp : v_reg_type := (IOLatch => "11111", IOLatch2 =
"11111");
begin
process (c) is begin
if c'event and c = '1' then
q_temp <= d_temp;
end if;
end process;
d_temp.IOLatch <= d1;
d_temp.IOLatch2 <= d2;
q1 <= q_temp.IOLatch;
q2 <= q_temp.IOLatch2;
end inits_arch;
The registers did not get initialized in 5.2i sp3 or in our next version
of the software. I will file a bug report on this.
As for your version of webpack not working please try the latest
version. If the register is still not initializing as suspected (not
using record types that is) please contact the hotline.
Actually the device files should be separate anyway since they changeIn article <omuMa.1725$zn2.469105682@twister1.starband.net>,
Steven K. Knapp <steve.knappNO#SPAM@xilinx.com> wrote:
Personally, I agree with your statement and have been trying to convince the
powers that be to add additional Spartan-3 devices to WebPack. The folks
responsible for WebPack are concerned about the total download size. The
larger devices have multi-MB support files.
Split the download, or switch the devcie files to be
download-on-demand or download-via-miniapp.
I don't really care how I get help. When I have a question, I just wantrickman wrote:
Often vendors don't want to seem like they are hawking their wares
here.
I can guarantee you that neither Xilinx nor Altera harbors this kind of
girlish modesty.
But we must consider the audience, and avoid the BS.
I definitely will hawk the capabilities of the Virtex-II DCM and MGTs if
anybody ever asks for a related functionality. That's my job, and that's
what this ng is for, isn't it?
Peter Alfke
I had misunderstood the problem as violating the min INPUT frequency...If you needed a lower frequency couldn't you always generate a power of two
multiple of it, and then divide that down?
Of course, that's the way.
designs are certainly morePeter Alfke wrote:
rickman wrote:
Often vendors don't want to seem like they are hawking their wares
here.
I can guarantee you that neither Xilinx nor Altera harbors this kind of
girlish modesty.
But we must consider the audience, and avoid the BS.
I definitely will hawk the capabilities of the Virtex-II DCM and MGTs if
anybody ever asks for a related functionality. That's my job, and that's
what this ng is for, isn't it?
Peter Alfke
I don't really care how I get help. When I have a question, I just want
an answer. If they are more comfortable with email than the newsgroup,
I don't care. Anything is better than the hotline or god forbid.. the
web site!
But I guess I should say that an open discussion here was what alerted
me to the modular configuration capability of ISE. I have checked this
out on the web site several times and pretty much found nothing. But
now I have at least one app note about how to use it and this will make
a very big difference in my device selection. However I expect this
will require a lot of support since it seems a bit more complex than the
app note covers.
It depends on how well your design fits into physical modules. Some
you a name.Can you recommend a point of contact for modular
configuration?
Yes, I will check with a couple of our modular design experts and get
This is exactly the sort of thing I expect will be like
pulling teeth to get any real info on from the hotline.
ahem, no, it's just that (I quote the website)please, if anyone can help me to find some information to interface the
OV6620 to my FPGA ( VHDL ), don"t hesitate !
ov6620 : www.ovt.com
ther is no application note .. no support.. :-(
(NDA = Non Disclosure Agreement, a confidentialityThe DATASHEET for the OV6620 requires an NDA.
Here are a few key advantages for Cyclone that I can think of off the top offor the new multichannel filter design I have a choice -
Altera Cyclone EP1C12 ($60) or Xilinx Spartan-3 XC3S1000(???)
"PC" <philippe.chagny**@NOSPAM@**@free.fr> wrote
in message news:3f033fb1$0$4611$626a54ce@news.free.fr...
please, if anyone can help me to find some information to interface the
OV6620 to my FPGA ( VHDL ), don"t hesitate !
ov6620 : www.ovt.com
ther is no application note .. no support.. :-(
ahem, no, it's just that (I quote the website)
The DATASHEET for the OV6620 requires an NDA.
(NDA = Non Disclosure Agreement, a confidentiality
contract agreeing that you won't give away any technical
information without the vendor's permission).
On the other hand, there is a full data sheet for the
OV6630 part on the web site.
If you got the sample device legitimately, how about
contacting them, signing the NDA and getting the data
that way?
Hint: If anyone else HAS the data, they've signed the
NDA already and therefore they would be breaking their
contract with Omnivision by telling you about it.
Cheers
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW,
UK
Tel: +44 (0)1425 471223 mail:
jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web:
http://www.doulos.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Hi,
I am using the following flow:
VHDL - Entry
Synplify Pro - Synthesis
Xilinx Design Manager - Post synthesis, place and route, etc.
The target device is Xilinx Spartan XL - XCS20XL.
I am trying to understand the two summaries:
1. Synthesis Summary
--------------------
Logic Mapping Summary:
FMAPs: 243 of 392 (62%)
HMAPs: 83 of 196 (43%)
Total packed CLBs: 173 of 196 (89%) <-*-*-*-
(Packed CLBs is determined by the larger of three quantities:
Registers / 2, HMAPs, or FMAPs / 2.)
2. Xilinx Design Manager Summary
--------------------------------
Design Summary:
Number of errors: 1
Number of warnings: 6
Number of CLBs: 250 out of 196 127% <-*-*-*-
CLB Flip Flops: 346
CLB Latches: 3
4 input LUTs: 246
3 input LUTs: 230 (147 used as route-throughs)
Number of bonded IOBs: 48 out of 112 42%
IOB Flops: 34
IOB Latches: 0
Number of clock IOB pads: 4 out of 8 50%
Number of TBUFs: 2 out of 448 1%
Number of BUFGLSs: 4 out of 8 50%
32 unrelated functions packed into 31 CLBs.
(12% of the CLBs used are affected.)
Total equivalent gate count for design: 4178
Additional JTAG gate count for IOBs: 2304
-------------------------------------------------------------------
Why is there a discrepancy between the Number of CLBs reported
by the synthesis tool (173) and the Xilinx design manager (250)?
As you would observe, the design manager reports an error due
to the excess usage of CLBs. As a result the flow does not proceed
to Place and Route etc. Any suggestions?
Thank you for your time.
Thanks,
Anand
I have two 5 V and two 3V3 power lines. One pair (5V and 3V3) is usedThe problem is the output of the PBGA seem to be producing a 1HZ pulse
which is expected when the 28V is on but not expected when the 28V is
turned off. The 1HZ pulse has a amplitude of 2V when the 28V is off
but when the 28V is on, the amplitude is 5V.
I have tested the power supply stand-alone and it works perfectly.
When the 28V is off, the PBGA power should be zero but in this case,
the voltage is 1.4V when connected to the PCB.
What's the voltage on your supply rails/planes on the side
that you expect to be off?
I have checked the power supply design and I think I will add aMy guess is that you have some signals going from the
expect-to-be-on section to the expect-to-be-off section,
and the protection diodes are kicking in and connecting the
energy from the signals to the power rail and there is enough
power getting through for the logic to start to work.
Last time I looked, there was one desktop class motherboard that seemedHi,
There are a number of boards available. You should look
for a server class motherboard, one that supports PCI-X
or at least PCI at 66 MHz. A board that supports either
of those will be (by requirement) at 3.3v slot, not a 5.0v
slot.
Altera will be shipping a Cyclone, 1C20-based PCI development kitAnybody know of Cyclone EP1C12 (preferably) or EP1C20
(also ok) based PCI development boards? Do such things
even exist - or in other words, what is the approximate
timline after chip availability that one can expect such
to be around?