EDK : FSL macros defined by Xilinx are wrong

[Jeff Cunningham]

Peter Alfke wrote:

Please, don't throw any more of your venom at this newsgroup.
You have stopped being entertaining or informative, a long time ago.
Peter Alfke, from home.

I couldn't agree more. The soaring ego combined with the chip on the
shoulder is really getting tiresome. Reminds me of the level of
discourse on sci.electronics. What a shame.
-Jeff

 

[bjzhangwn]

Thanks,the specification I have read many times,the fpga I used is
stratix 2,and the signals (dmack,ata addr,diow,dior) sampled by the
logic analyzer inside the fpga are crrectly.

 

[Brian Drummond]

On 6 Mar 2006 21:24:29 -0800, sachink321@gmail.com wrote:

HI
how would i use internal signals in XPS for microblaze on spartan 3
fpga board.

let me explain my project
in opb_emc
im using 2 memory banks
so im having two Output enable signals
but i have only one external pin
so i need to AND these two output signals and produce a single output
this output will be given to the external signal.

but i cant understand how can we produce a logic
for these internal signals?

any ideaz

There are two approaches; the util_reduced_logic core is one; for
something slightly more complex you can create your own core for the XPS
project and add it just like util_reduced_logic. This allows you to keep
the entire project in XPS.

But the other approach is to embed the XPS-generated system as a
subsystem in an ISE top level project. The XPS tools will generate a
"stub" design that simply brings every pin on your subsystem out through
I/O buffers to FPGA pins on the top level design.

You can then use this "stub" as a starting point for your own top level
design. In this instance you would simply "and" the two signals from the
subsystem and connect the result to a single output pin (deleting the
unused one).

For a single "and" gate this would not be simpler, but for a large
amount of "traditional" logic (e.g. FFT, filters, etc) it is probably
easier than creating XPS cores for everything you want to add...

- Brian

 

[Michael Schöberl]

bjzhangwn schrieb:

the fpga I used is stratix 2

I don't think this FPGA can handle 5V ... I assume you use a level
shifter outside the fpga? does the direction switching of the data lines
work? are the voltage levels ok?


bye,
Michael

 

bjzhangwn wrote:

Thanks,the specification I have read many times,the fpga I used is
stratix 2,and the signals (dmack,ata addr,diow,dior) sampled by the
logic analyzer inside the fpga are crrectly.

They match what you designed them to do, but that doesn't mean they are
correct for the IDE interface.

 

[Austin Lesea]

John, (or should I call you Mr. Bass?)

Sorry to hear you are this upset, John.

I will promise not to shorten your name (or alias) in the future.

My posting was a news item, of LSI dropping their structured ASIC offering.

My second posting was to direct you to the subject of the first posting
(you seemed to be wandering somewhere that I could not follow).

My opinion (no secret) is that ASICs are moving into an area where only
a few can afford to develop them, and as such, the number of design
starts has fallen off. But, the amount of money has actually increased
(due to their getting more expensive to develop, and those that do get
done, covering huge new markets - like gaming consoles).

Not counting microprocessors, and memories, Xilinx is now the second
largest vendor of "logic" (which includes ASICs, per Gartner-DataQuest).

It has been great to have the ASIC vendors treat FPGAs with such
disdain, and contempt. While they basked in their obvious unassailable
superiority, we just ate their lunch. With great margins, too.

Will ASICs go away? Of course not. Will they continue to be the growth
industry they were? In my opinion, that sun already set. Will they
continue to make a lot of money? Of course. At least until the
customers get tired of paying too much, for too little.

I recommend you look into the story of steel mills in the US. They
ruled the world. Then these little mini-mills started competing, and
the US super mills said "our steel is so high quality, we will give the
low grade steel business to the mini-mills. Won't even notice the drop
in volume, and we will make more money." Then, after a while, the
mini-mills made better steel. The big guys said, "well, that wasn't as
profitable as it used to be, so what the heck." We all know what
happened. The US steel business collapsed. I see ASICs in the same
boat. I can see the ASIC board room discussion, "we will let the FPGAs
have those sockets: they were getting too tough to win anyway. No
profit left in it. They can't do what we do, so we don't have to worry.
We will just go on to the more profitable markets..."

Austin

 

[Aurelian Lazarut]

if you are trying to learn vhdl by asking simple questions to this group
you'll never learn.
Download a good tutorial from the web and start working with the
provided examples.

Aurash

laura_pretty05@yahoo.com.hk wrote:

Now, I used the state machine to apply to VHDL. In my case, there are
two states, S0 and S1.
When I press a button, S0 is transit to S1 such that the LED display
some of the segments,like segment a,b,c. And press this button again,
S1 is back to S0. How can I present in VHDL so that the LED display in
segment a,b,c ? Thanks!!

 

[John_H]

<fpga_toys@yahoo.com> wrote in message
news:1141824014.067825.151340@u72g2000cwu.googlegroups.com...

Actually, Austin has addressed replys to me as John back in Jan. And
despite my objections, or specifically because I objected, he's choosen
to push the toy button as well as other much more direct attacks. I
was polite and firm asking that he stop.

Two, or three, or more can play his game. As I suggested quiet some
time ago, if he wants to play nasty that way, then he becomes
responsible for setting the tone and nature in which others can, and
will, interact with him as well.

Dude,

Change your handle here to something that can't be "nicknamed" to something
*you* find offensive and you won't get pissed off by someone using part of
your name to address you.

When I see "fpga_toys" in an "fpga" newsgroup, the only thing that isn't
redundant is that which follows the underscore.

Austin pisses you off, you piss me off with your ranting. I won't bother
you further when your emails "obviously" are derogatory to others on this
forum.

- John Handwork

 

I want to know which VHDL book is better for learning...??

 

[Jim Granville]

Austin Lesea wrote:

My opinion (no secret) is that ASICs are moving into an area where only
a few can afford to develop them, and as such, the number of design
starts has fallen off. But, the amount of money has actually increased
(due to their getting more expensive to develop, and those that do get
done, covering huge new markets - like gaming consoles).

snip

Will ASICs go away? Of course not. Will they continue to be the growth
industry they were? In my opinion, that sun already set. Will they
continue to make a lot of money? Of course. At least until the
customers get tired of paying too much, for too little.

Yess... OK, until you start to drift a little in the last sentence...

I recommend you look into the story of steel mills in the US. They
ruled the world. Then these little mini-mills started competing, and
the US super mills said "our steel is so high quality, we will give the
low grade steel business to the mini-mills. Won't even notice the drop
in volume, and we will make more money." Then, after a while, the
mini-mills made better steel. The big guys said, "well, that wasn't as
profitable as it used to be, so what the heck." We all know what
happened. The US steel business collapsed. I see ASICs in the same
boat. I can see the ASIC board room discussion, "we will let the FPGAs
have those sockets: they were getting too tough to win anyway. No
profit left in it. They can't do what we do, so we don't have to worry.
We will just go on to the more profitable markets..."

I love Austin on a roll.....

Take a deep breath, and read what you wrote above: ASICs will NEVER go
away.
Points to ponder :
** An FPGA is also an ASIC - remember "Application Specific Integrated
Circuit"
Some very big players have large revenue streams in targeted silicon.
(ASICs) As soon as any given market gets large enough, they can afford
to take the performance gain of an ASIC.

** look at this news item
http://www.eet.com/news/design/showArticle.jhtml;jsessionid=NO4FYXLJXNB0EQSNDBCSKHSCJUMEKJVN?articleID=181501574

** look at the devices comming from ST

** Ponder that the mini-mills just might be Lattice and Actel, and
Xilinx might be the larger insular, belligerant model.

I think it was my Gran used to say "Pride comes before a fall" ?

-jg

 

[Jerry Coffin]

In article <dun1n1$ar211@xco-news.xilinx.com>,
austin@xilinx.com says...

[ ... ]

My posting was a news item, of LSI dropping their
structured ASIC offering.

I hope you'll pardon my jumping in, but I think this is
where things started to go wrong. While this may arguably
be related to the FPGA business in general, it seems
pretty clear to me that it's not related to anything like
architecture or development.

Other than as an ego boost, it's pointless anyway: given
that this newsgroup is devoted specifically to FPGAs to
start with, the only people here to see the post are
already reasonably convinced that FPGAs are/can be
useful, and most of use use them more or less regularly
already.

--
Later,
Jerry.

The universe is a figment of its own imagination.

 

[Fabio Rodrigues de la Roc]

Hello,
A good source of information is the tutorial EVITA
(http://www.aldec.com/products/tutorials/) and
(http://www.vhdl-online.de/tutorial/). Also, you can use the google to
find others. I started using the book "VHDL starter's guide"

Fabio

laura_pretty05@yahoo.com.hk wrote:

I want to know which VHDL book is better for learning...??

 

[Jim Granville]

fpga_toys@yahoo.com wrote:

<snip>

It's with this perspective that domestic FPGA vendors could easily
disappear off the map as quickly as GE, RCA, Magnavox, Packard Bell,
Motorola, and other US TV and Radio suppliers did from 1965 to 1970
when domestic production pretty much stopped.

Xilinx doesn't control it's means of production, and with that, it also
does not control it's fate. As FPGAs become a comodity building block
for all electronics, as it seems it will during this decade, then every
major fab on the planet will be producing them ... frequently with the
fabs own design and logo. Since early US patents are set to expire this
decade, that is almost a given. Those same fabs producing FPGAs are
very likely to offer discounted ASIC facilities based on their netlists
... so I see the structured ASIC market as long term, at all levels.

I think FPGAs are a little insulated from the simpler boxes trends,
as a substantial portion of the product, is actually software.
IIRC, both Altera and Xilinx employ more Engineers on the SW side,
than HW, and have done for a while.
With Lattice now in the fray, with Fujitsu FAB'd devices, software
is going to be the key differentiator.
After all, in spite of the best spin efforts from all the marketing
departments, the Silicon performances are actually quite similar -
expected given they depend mostly on what Process the leading edge FABs
can run.
-jg

 

[Austin Lesea]

Jim,

I know about Menta and ST.

ST are countering IBMs 90nm ASIC offering which has been using a
licensed 90nm FPGA core from us for over two years now.

ST just staying competitive, in my book.

Perhaps they saw an opportunity that having a small FPGA core would
allow them to address? It appears that the use of the core is
restricted to customizing a processor. Not enough details to really see
what is being offered. For what, or why.

But, if there were any details, then the holders of significant FPGA
patent portfolios would probably start to get interested....

At least if you bought the IBM solution you could develop and prototype
your solution with Xilinx' proven tools, and be assured that the
solution you were getting was from two of the world leaders in their
respective fields, and that there would not be any patent disputes that
might cause a disruption in supply.

The fact that ST dropped their GOSPL FPGA project and went with an
(unknown) third party for their offering has puzzled a number of people.

We will see.

Austin

 

[Austin Lesea]

John,

Interesting opinions.

Of course, I disagree that ASICs have any rosy future at all, and I also
feel that your conclusion that whoever controls the foundry controls the
technology is also quite bizarre.

How many patents does Xilinx have?

How many are due to expire?

How many that are due to expire matter? (All it takes is one of the most
recent ones to be a barrier to entry...for the next 20 years).

How many lines of code do you need to support your FPGA design (in the
tools)?

How many hotline engineers does it take to support FPGAs?

How do you train and support the distributors, FAEs and customers in a
new technology from a new vendor?

How much circuit design for FPGAs is done outside the US? Outside
silicon valley? How much software for CAD tool support of FPGAs is done
elsewhere? Where are the patents being filed?

Xilinx doesn't just excell in one area, we excell in as many areas as
possible. Each by itself is a huge barrier to entry.

Only getting tougher to compete.

And, we don't stand still. Did you see the 65nm FPGA announcement last
week?

http://www.xilinx.com/prs_rls/2006/xil_corp/0630_65nm.htm

And, have you heard anything about that 65nm ASIC process being ready
for anyone, anywhere? For anything? Other than it is too much money,
and too much power? (with no proven IP)

Ouch. Where is all that new cool 65nm IP, and stuff for that next
killer application? MGTs, MACs, DSP, PPC, etc.

Oh, Xilinx has it in their FPGA.

Austin

 

[Austin Lesea]

Jim,

I beg to differ. In terms of power, resistance to neutron SEUs, and
signal integrity, our silicon has significant advantages.

One not so small feature: we have 90nm triple oxide.

The process was developed for us, at our request, by two foundries.

Oh, and we have it for 65nm, too.

Wake up and smell the coffee. We asked for a process, and we had more
than one foundry eager to supply it.

That sounds to me like a revolution in the fabless model. Instead of
"give me your masks and I'll give you some chips" we have a working
partnership and cooperation in developing a new process unique to our
industry.

Austin

 

Austin Lesea wrote:

How many that are due to expire matter? (All it takes is one of the most
recent ones to be a barrier to entry...for the next 20 years).

All it takes is demonstrated prior art to avoid it as well, plus some
litigation to avoid the challenges. By 1989 what was published
regarding FPGAs, and the devices that were in production at that time,
provide an architectural wealth for producing patent free comodity FPGA
devices, which scaled to current processes, would make a strong
competitor for main stream FPGAs. The market for advanced FPGAs would
at that time not be nearly as high margin with the cash cows
slaughtered, and the competition would become stiff.

 

[Joseph H Allen]

A more intersting discussion for me is the best path for converting
expensive high end FPGA designs into ASICs. I viewed rapidchip as one of
these paths- so what's left? Is this even a big business?

Xilinx: easypath - lower cost but no faster.

Altera: hardcopy-II - these are structured ASICs. They look appealing, but
I did not get the impression that there were many conversions (at least as
of a year ago).

--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0%79-77?1:0<1659?79:0>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

 

[Rob]

Volumes and TTM (time to market) will dictate the path you take, either ASIC
or structure ASIC. And sometimes they both can work for you. We have a
recent product with projected numbers that make an ASIC the best candidate,
lowest UMC. The downside is that the ASIC has a long schedule; so long that
we would miss launch: missing the market with a product can cost a company
big $$. The answer, launch with a structure ASIC (Altera HC) and roll in
the full ASIC later in production. Yes, you get nailed with 2 NRE's, but if
your numbers are high enough (as they are in our case) the business case can
make sense.

In our case the ASIC was a little less than half the cost of the Structured
ASIC. Altera's HC also can afford you a pin compatible footprint such that
you can plop an FPGA down on your production board if you wanted to do
further development.


"Joseph H Allen" <jhallen@TheWorld.com> wrote in message
news:duo67n$4ml$1@pcls4.std.com...

A more intersting discussion for me is the best path for converting
expensive high end FPGA designs into ASICs. I viewed rapidchip as one of
these paths- so what's left? Is this even a big business?

Xilinx: easypath - lower cost but no faster.

Altera: hardcopy-II - these are structured ASICs. They look appealing,
but
I did not get the impression that there were many conversions (at least as
of a year ago).

--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H.
Allen */
int
a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0%79-77?1:0<1659?79:0>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817printf(q%79?"%c":"%c\n","
#"[!a[q-1]]);}

 

[Petter Gustad]

jhallen@TheWorld.com (Joseph H Allen) writes:

A more intersting discussion for me is the best path for converting
expensive high end FPGA designs into ASICs. I viewed rapidchip as one of
these paths- so what's left? Is this even a big business?

NEC has a structured ASIC family (like the ISSP90).

Petter

--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?