EDK : FSL macros defined by Xilinx are wrong

[RobJ]

Austin, Paul -

Why no mention of EasyPath or HardCopy? Where do those flows fit into the
FPGA vs. structured ASIC battle? Can you guys share any numbers for your
respective "ASIC conversion" programs? As in how many design conversions per
year, trends up or down over the last few years, profit margins vs. your
FPGA business, cost for an EasyPath or HardCopy part vs. an equivalent
structured ASIC part from one of the nine remaining vendors? Are these
programs viable and will they continue? I've seen both of you guys bail from
similar programs in the past.

Good thread.

Rob

 

[Austin Lesea]

Rob,

Easypath is not a structured ASIC, it is an FPGA. Identical in every
way to what the customer is already using. Except that we haven't
tested the bits they don't use.

As for "success" of Easypath, it requires no design, no software, and no
support. No R&D. Completely different business model.

So just one customer for Easypath is direct $ to the bottom line.

Obviously, we have more than one customer, yet I am not able to give you
the exact number (as we consider it proprietary).

I do not consider Easypath as a competitor to ASICs (structured or
otherwise), but as a cost lowering alternative for FPGA customers who no
longer need to reconfigure their product. In effect, this is a new
segment of an existing market.

Would these customers go to an ASIC if Easypath was not an option? I
really don't know. I suspect not. I suspect they would just move on to
the next product, and either end the life of the one, or accept reduced
profits and reduced sales.

I know that Easypath is positioned as an alternative to Altera's
HardCopy, but I disagree: Easypath is just that - easy. HardCopy is
just that - hard.

One is buying exactly the same silicon for a lower price, and moving on.

The other is converting from a FPGA prototype of your design, to an
ASIC, with all of those real risks (and I have heard of real cases of
failure to converge from customers doing just that) and time to market
issues.

We did have a program for cost reduction, and hardening the FPGA design.
It was called Hardwire. We had Hardwire 1, 2, 3... All we learned
from this was the ASIC business is not our business (it is totally
different business). And, we also learned that it is incredibly hard to
make any money. Lots of competitors, many that are very hungry, and
will drop the prices to take business beyond sanity.

The structured ASIC shell and pea game is just that. Some of our
hardwire products were just vias to short out memory cells, so the
"conversion" was only a couple of masks, and costs were supposed to be
incrediby low. Not. The story was good, but the reality was horrible:
it didn't work the way it was supposed to (sound familar?). We
eventually ended up with a standard cell ASIC flow after a gate array
flow. Guess what? Didn't matter what the flow, it was still the ASIC
business. You still did an incredible amount of work once, for one
customer, with no guarantee of success, with no future, and no reuse of
anything for the next technology node.

With a real chance of failure. If the customer makes a mistake, we both
fail.

I like the model for FPGAs: if the customer makes a mistake, they fix
it, and move on. Meanwhile we are succeeding with all of the other
customers. They will succeed, too.

If you will, we already have "been there, done that" and decided that we
should stick with the customers, markets, business and business models
that have made us the success we are today.

Let those nine companies circle the drain, the plug has been pulled.

Austin

 

[Jim Granville]

RobJ wrote:

Austin, Paul -

Why no mention of EasyPath or HardCopy? Where do those flows fit into the
FPGA vs. structured ASIC battle? Can you guys share any numbers for your
respective "ASIC conversion" programs? As in how many design conversions per
year, trends up or down over the last few years, profit margins vs. your
FPGA business, cost for an EasyPath or HardCopy part vs. an equivalent
structured ASIC part from one of the nine remaining vendors? Are these
programs viable and will they continue? I've seen both of you guys bail from
similar programs in the past.

Good thread.

Paul did mention this, in another branch :

HardCopy II is particularly exciting because it uses a very efficient
fine-grained logic fabric and provides a choice of migration devices
allowing greater cost reductions than previous members of the family.
HardCopy II also provides a significant speed-up over the equivalent
Stratix II FPGA devices and cuts power consumption in half.

Which is interesting, because that offers a lot more than Xilinx's
subset testing - and as Paul also mentions, it is the Prototyping, and
tool flows, that make a large difference in taking this step.

What is pretty much the same, in X & A's 'custom' offerings, is both
will do the component testing, on their FPGA testers.

Unlike other ASIC vendors, the FPGA players have (very) large
investments in the SW side of their business.
Of course HardCopy paths are only for a tiny % of customers, so
from a design-start viewpoint, they are insiginifcant, but the revenue
potential of that small group are significant.

Still, if I were a Xilinx stock holder I might be a bit worried
about their ignoring this sector. Let's see where they stand in 2008..

-jg

 

[Austin Lesea]

Jim,

Let's see, Xilinx is "ignoring" a piece of a 155 M$ business with lousy
margins and 9 other vendors competing and willing to drop prices below
their costs?

As a Xilinx stockholder, I am pleased to see that Xilinx can keep their
eye on the prize, and not stray off to the "gold ring du jour."

I do agree that having a cost reduction path is important for business.

I do not agree that spending a proportion of your revenue is warranted
to "capture" it. A simple ROI calculation will reveal if it is real
business, or just plain dumb.

Toshiba figured it out.

LSI figured it out.

We figured it out years ago.

Two others figured it out (too late as they drove themselves right into
the ground).

Austin

 

[Evan Lavelle]

I know it's a mistake getting involved in this thread, but...

here are some observations on EasyPath and (Structured) ASICs which
don't appear to have come up elsewhere:

1 - EasyPath has an NRE. I don't have real numbers, but Xilinx's
literature gives figures between $75K and $300K, and an MOQ of 50K
pieces. It's not cheap.

2 - If you commit to EasyPath, you can't change your design without
paying the NRE again. In this respect, EasyPath is the same as an
ASIC. You have to be absolutely sure that it'll work. Just like an
ASIC, in fact.

3 - The RapidChip NRE, for a device with about the same capacity as a
very large Virtex-4, came in at about $100K - $150K, with much smaller
MOQs. And this is a *small* device.

4 - EasyPath is not 'just the same' as the FPGA you were buying
before. When I last looked, it was a device that had failed test.
Perhaps someone from Xilinx could comment on whether this is true or
not. This matters, because fewer devices will fail testing when yields
go up, as they will. You're going to have to ask yourself whether
Xilinx will carry on selling you cheap devices when they could sell
them to someone else at full price.

5 - As I said in my other post in this thread, there is no comparison
between EasyPath and even a 'structured' ASIC when it comes to
capacity, performance, and power consumption.

6 - You can (or could) get RapidChip prototypes in about 8 weeks from
handoff. I don't have EasyPath figures, but it's not going to be a lot
less than that.

7 - I've seen (in several places) the claim that EasyPath devices are
cheap because they require less testing. I don't believe it. They're
cheap because they failed test in the first place, and so would have
no value at all without the EasyPath route. It would be nice to have a
definitive statement from someone in Xilinx if they happen to disagree
with this.

Where I agree with Austin is "I do not consider Easypath as a
competitor to ASICs". So, what on earth is the point of spending all
this (uninformed) effort knocking ASICs? If someone can get the
business model right, then Structured ASICs will fit very nicely into
the space between FPGAs and standard cell. And they will make no
difference at all to the vast majority of the FPGA market.

Evan
--
Riverside
emlat
riverside-machinesdotcodotuk

 

[Jim Granville]

Austin Lesea wrote:

Jim,

Let's see, Xilinx is "ignoring" a piece of a 155 M$ business with lousy
margins and 9 other vendors competing and willing to drop prices below
their costs?

I have to smile - all those 'make it your ASIC' promotions by
marketing, and here you now claim the market is tiny, and with no
margins ?! .....
-jg

 

[Austin Lesea]

Jim!

That is a bait and switch on your part.

The "make it your ASIC" program is selling Spartan 3 90nm part directly
against gate arrays (an easy winner, no brainer), and selling Spartan 3
90 parts directly against a segment of the standard cell ASIC business
(definetly can't win all of that market! - yet).

In fact, the "make it your ASIC" (referring to Spartan 3 90nm) has been
so successful, that with 10 million devices sold (see press
announcement), it represents more 90nm, basically supplying 70% of all
90nm FPGAs.

http://www.xilinx.com/prs_rls/silicon_spart/05118_90nm10mil.htm

That was December, 2005. And now we have had almost a whole quarter of
sales which just extend this lead by even more (which I can't say, as I
really don't know the numbers until they are announced).

How does that compare with 90nm ASICs? Well, I can say pretty safely
that without this program, and these parts, there might be 10 million
more 90nm ASICs in the world in the last year...

But I really doubt it, as most ASICs don't work, never get to market,
and generally just cause gray hair.

We got the sockets. We got the parts.

Austin



Jim Granville wrote:

Austin Lesea wrote:

Jim,

Let's see, Xilinx is "ignoring" a piece of a 155 M$ business with
lousy margins and 9 other vendors competing and willing to drop prices
below their costs?


I have to smile - all those 'make it your ASIC' promotions by
marketing, and here you now claim the market is tiny, and with no
margins ?! .....
-jg

 

[Jim Granville]

Austin Lesea wrote:

Jim!

That is a bait and switch on your part.

The "make it your ASIC" program is selling Spartan 3 90nm part directly
against gate arrays (an easy winner, no brainer), and selling Spartan 3
90 parts directly against a segment of the standard cell ASIC business
(definetly can't win all of that market! - yet).

In fact, the "make it your ASIC" (referring to Spartan 3 90nm) has been
so successful, that with 10 million devices sold (see press
announcement), it represents more 90nm, basically supplying 70% of all
90nm FPGAs.

http://www.xilinx.com/prs_rls/silicon_spart/05118_90nm10mil.htm

That was December, 2005. And now we have had almost a whole quarter of
sales which just extend this lead by even more (which I can't say, as I
really don't know the numbers until they are announced).

How does that compare with 90nm ASICs? Well, I can say pretty safely
that without this program, and these parts, there might be 10 million
more 90nm ASICs in the world in the last year...

Wow - and I have to smile again...
Now you are saying that 100% of the Spartan 3 business is ASIC
replacement, and that a spartan sold is an ASIC replaced/removed ?

-jg

 

[Jim Granville]

Evan Lavelle wrote:

I know it's a mistake getting involved in this thread, but...
snip
7 - I've seen (in several places) the claim that EasyPath devices are
cheap because they require less testing. I don't believe it. They're
cheap because they failed test in the first place, and so would have
no value at all without the EasyPath route. It would be nice to have a
definitive statement from someone in Xilinx if they happen to disagree
with this.

Many companies have 'bining' flows, where the same die attract
different prices, sometimes over a 2:1 range.

Yes, EasyPath helps if they can use otherwise reject parts, but
remember if it failed a generic test, it is likely to fail in your
application.
ie Only a subset of failure types will be candidates.

Testing IS expensive, but so also is running a custom test - thus the
fairly high NRE prices on EasyPath - it also serves as a 'go away' flag
to those with insufficent volumes

Testers themselves are expensive, if your app can run on a low cost
one, that frees up the cutting edge ones, for higher margin full FPGAs

-jg

 

[austin]

Jim,

OK, OK. You caught me in a wild unsupported assumption.

No, not all of those 10M sockets stole an ASIC win.

Austin

Jim Granville wrote:

Austin Lesea wrote:

Jim!

That is a bait and switch on your part.

The "make it your ASIC" program is selling Spartan 3 90nm part
directly against gate arrays (an easy winner, no brainer), and selling
Spartan 3 90 parts directly against a segment of the standard cell
ASIC business (definetly can't win all of that market! - yet).

In fact, the "make it your ASIC" (referring to Spartan 3 90nm) has
been so successful, that with 10 million devices sold (see press
announcement), it represents more 90nm, basically supplying 70% of all
90nm FPGAs.

http://www.xilinx.com/prs_rls/silicon_spart/05118_90nm10mil.htm

That was December, 2005. And now we have had almost a whole quarter
of sales which just extend this lead by even more (which I can't say,
as I really don't know the numbers until they are announced).

How does that compare with 90nm ASICs? Well, I can say pretty safely
that without this program, and these parts, there might be 10 million
more 90nm ASICs in the world in the last year...


Wow - and I have to smile again...
Now you are saying that 100% of the Spartan 3 business is ASIC
replacement, and that a spartan sold is an ASIC replaced/removed ?

-jg

 

Thomas Womack wrote:

There has been a lot of research put into efficient implementations of
the S-boxes without using lookup tables;

http://www.st.com/stonline/press/magazine/stjournal/vol00/pdf/art08.pdf

might be an example. I went to a conference in August where
http://class.ee.iastate.edu/tyagi/cpre681/papers/AESCHES05.pdf was
presented, which runs AES at 25Gbits/second on an XC3S2000; the round
function is pipelined into seven stages of three levels of LUT each.

Any clue what the specific GF functions and tables are?

 

[Jim Granville]

Rob wrote:

Austin,


Let those nine companies circle the drain, the plug has been pulled.


I'm really having great difficulty trying to understand why you think the
ASIC/ structured ASIC market is going to die. Can you give us Xilinx's
roadmap/business model that will compete?

Don't forget Xilinx have a (large) vested interest in talking down any
ASIC MASK flows.

For instance: can you give me a 60k/annum pricing for a product that has a
3yr life--total pcs 180k of a 375k Gate device with 3Mbit of on chip ram and
4 PLL's? And I'll compare it to my quote from our ASIC vendor. When we
started this design we were in a V2PRO30, since then our design has grown
beyond the limits of this device. But since I only have pricing on the
V2P30 my math will have to be based on this part. I will only give
percentages as it would not be prudent for me to reveal the actual numbers.

The ASIC is 8x cheaper than the V2P part. How much more lower would the
ASIC be when compared to an FPGA that could hold our current design? It is
very easy to see that we save the company BIG $$ by going to an ASIC. The
structured ASIC pricing was approx 4x cheaper, which is still very much
cheaper than going with an FPGA.

Did you get a Hardcopy II price from Altera, or is that what you mean here ?

Do you have any current consumption ratios ?

Xilinx has decided to ignore this market, based on one of your posts--155M
is too small for a 2B dollar company.

That has to be a very hard number to quantify reliably - for example,
I doubt if Altera's HardCopy is in that pigenhole, they will be called
FPGA's.
Altera only has to hit ~15% revenue via HardCopy, to equal that number.

Another way to approach this, is the FSA just said their members hit
$40B last year, and they are only a portion of FAB runs.
TSMC alone is presently close to $10B/yr, at the FAB end.

Everything a FAB makes, is an ASIC - a large chunk will not be
reachable by FPGAs due to sheer low power, or Analog features ( tho
Actel can start to argue on that last point, at least for average analog
features ).

-jg

 

Rob wrote:

Austin,

Let those nine companies circle the drain, the plug has been pulled.

I'm really having great difficulty trying to understand why you think the
ASIC/ structured ASIC market is going to die. Can you give us Xilinx's
roadmap/business model that will compete?

We've just come thru one of the largest and longest tech slumps that
has created MANY corrections and changes in the market. What has been
not so profitable for the last five years is no indiction of what will
be profitable for the next five years if we resume a normal boom cycle
at this point. Cashflows have been VERY tight, making NRE's very
difficult to swallow, which is certainly been tough on both the ASIC
industry and all capital intensive related markets.

Xilinx has substantial reasons to gain by declaring the ASIC markets
dead, FUD to help push projects thinking about the NRE's to FPGAs. High
end businesses sift thru technologies ranging from pure ASIC to PLD on
a project by project basis, directly coupled to sales ... which if
headed up will also mean they are headed up the logic food chain too.

 

[Allan Herriman]

On Fri, 10 Mar 2006 12:24:10 +0100, backhus <nix@nirgends.xyz> wrote:

Google shows that there are many papers claiming rather fast AES in
FPGAs (with some fine print saying they're using a non-feedback mode).
I've never seen a feedback mode cypher in a real world application get
anything over some Gb/s.

Regards,
Allan

Hi Allan,
interesting point, but have you thought about what the reasons may be?

Let's do some (approximative) calculations.

Assume you have a single AES-Round that runs with a 100MHz Clock.
This round needs at least 10 clocks to produce an AES Cipher.

With 128 Bits Data width that gives:

128 * 100e6 /10 = 1,28e9 Bits per second

So that is the limit for the assumed circuit.

Adding a feedback path for block cipher modes will extend the number of
clocs to create a ciper.

Let's assume 14 clocks to produce a CBC cipher

Now we have:

128 * 100e6 /14 = 914,3e6 Bits per second

That's all what's possible with the assumed circuit.

How can we increase the throughput?

1) Wait for better silicon that allows higher clock rates.
2) Use more chip-space to implement aditional rounds and decrease the
number of iterations needed in the round. But that may be rather expensive!

3) Improve the rounds latency. Make it fast to the limit. (Which is at
about 500MHz as some vendors claim for their products ;-) )

Now let's assume our circuit will still run at 100MHz, but the improved
round runs at 500 MHz. That will reduce the round latency to 2 100MHz
cycles. Which gives 6 cycles to create the CBC cipher.

Now we have:

128 * 100e6 /6 = 2,1e9 Bits per second

So, that's the theoretical limit for the assumed circuit. You can exceed
it by investing in additional or better (ASIC) silicon, if you have the
money.

As I understand the original posting, these guys want to spend some work
on solution 3 somehow.

My tip to manjunath & co.: Have a look at the standard implementations
and the book "The design of rijndael" ISBN: 3540425802
Identify the modules and start optimizing the designs to whatever your
goal is.

Have a nice synthesis
Eilert

Hi Eilert,

That's the idea. Your numbers are a little out though. Using a
mature FPGA process (with moderate speed grade) is likley to result in
a clock of about 200MHz if hand placement of the sboxes is used.

AES takes 14 rounds per block.
It might be possible to have feedback around that block without
wasting another clock, but let's assume that it takes 1 extra clock
for the feedback mux, which gives 128 bits of result every 15 clocks.
This results in a throughput of 1.7Gb/s.

A newer FPGA + fastest speed grade + hand placement of some LUTs might
double the numbers. I doubt it could reach a 500MHz clock in an FPGA.

Of course, if one isn't using a feedback mode, many AES engines can be
run in parallel for a vast increase in speed. Alternately, the loops
can be unrolled for the same effect.

I notice that OC192 / STM64 AES encryptors have been available for a
couple of years. I assume these have a single FPGA which produces
approx 20Gb/s of crypto material (10Gb/s encrypt, 10Gb/s decrypt + the
encrypt and decrypt streams are different so they can't share any
hardware).

Regards,
Allan

 

[manjunath.rg@gmail.com]

No i dont think you can implement hardware concepts of subpipeling that
too in non feedback mode in C so easily..anyway if you have a c to vhdl
converter do tell me

 

[Thomas Womack]

In article <1142043401.992063.195710@e56g2000cwe.googlegroups.com>,
<fpga_toys@yahoo.com> wrote:

Thomas Womack wrote:
There has been a lot of research put into efficient implementations of
the S-boxes without using lookup tables;

http://www.st.com/stonline/press/magazine/stjournal/vol00/pdf/art08.pdf

might be an example. I went to a conference in August where
http://class.ee.iastate.edu/tyagi/cpre681/papers/AESCHES05.pdf was
presented, which runs AES at 25Gbits/second on an XC3S2000; the round
function is pipelined into seven stages of three levels of LUT each.

Any clue what the specific GF functions and tables are?

http://eprint.iacr.org/2004/134.pdf at the bottom of page six and top
of page seven gives a set of fields that you could use, but I'm afraid
I'm not really in the mood to explain GF(2^k) arithmetic in full
detail in a Usenet post, and on trying I've found that I can't
reconstruct the whole process without a fair amount of work; how much
do you know about it to begin with?

It's basically a generalisation of complex numbers to binary
arithmetic: start off with W defined so that W^2 = 1+W, and you have
[with a,b,c,d single bits]

(a+bW)(c+dW) = ac + (bc+ad)W + bdW^2 = (ac+bd) + (bc+ad+bd)W

(a+bW)^{-1} = (a+b) + bW

so, multiplication and inversion of things of the form a+bW are two
LUTs each. You then define X^2 = (something in 1 and W) + (something
in 1 and W)*X and repeat the process, using the definition of
inversion at the bottom of page 6 of the iacr preprint, to get
multiplication of four-bit expressions; you then define Y^2 =
(something in 1, X, W) + (something in 1,X,W)*Y and repeat again.

This is probably easiest done if you can find a spare mathematician to
lean over your shoulder while you're doing it, or ask on sci.crypt
where there will probably be someone who has the derivation handy:
good terms to google on are 'composite extensions' and 'towers of
fields'.

Tom

 

manjunath.rg@gmail.com wrote:

No i dont think you can implement hardware concepts of subpipeling that
too in non feedback mode in C so easily..anyway if you have a c to vhdl
converter do tell me

Pipelines in C are relatively easy at the statement level, just
requires reversing statement order.

a = 1;
b = a;
c = b;

propagates 1 to c with sequential execution.

for(; {
c = b;
b = a;
a = 1;
}

requires three clocks before c obtains the 1 value, three clock latency
pipeline that trickles up ward.

 

Thomas Womack wrote:

This is probably easiest done if you can find a spare mathematician to
lean over your shoulder while you're doing it, or ask on sci.crypt
where there will probably be someone who has the derivation handy:
good terms to google on are 'composite extensions' and 'towers of
fields'.

Thanks Tom. My math skills date back to very early 70's, and have not
needed to progress past that for most of the hardware/software
engineering I've done since. I do have a general interest in crypto
stuff, and would probably need a math guy with some patience to walk me
thru it.

I did take the Deamon example code for study this morning, and while
not suitable for FPGA implementation because of the all the serialized
looping it was enough to understand the core algorithm pretty quickly.
I re-wrote it into a fully unrolled subset C for FpgaC in a couple
hours that is highly parallel, and pipelined at each round. The Sbox's
are just stubbed out with a define macro, waiting for something
reasonable to place in the macro. It appears that it should run at a
pretty fair clip once someone can provide a set of C statements for the
Sbox implementation you have reference.

it does suffer a bit from a long standing problem we inherited from
TMCC, which is that it doesn't know how to map F5/F6 muxes for
extending 4-LUT equations, and tends to push terms down a little too
quickly forcing a slightly deeper logic tree than optimal. This is also
impacting the PCI core I started as demo code a few weeks ago.

So, I'm off re-writting the FpgaC bottom end code to solve that
problem for good. After the mux fixes, it appears FpgaC can compile the
AES engine to netlist very well, along with the earlier RSA demo code's
barrel shifters.

John

 

[austin]

Rob,

I am not saying ASIC business is decreasing.

In fact, I stated the dollars are increasing (on fewer design starts).

I am stating that the structured ASIC business has been a real money
loser for the companies that are toughing it out. And, that there are
companies leaving that business because "there is no money" (Toshiba's
quote, not mine).

So, do not misquote me. ASIC's $ increase; structured ASIC $ ? (unknown
if it will increase or decrease, but you may be sure that companies will
have a hard time making money if they continue to pretend it is a one
or two mask operation).

155M$ is the whole MARKET (IN 2005, ISuppli). That was spread over as
many as 12 companies in that year. LSI had the largest share of that,
at 35M$. Everyone one else had a smaller chunk that 35M$.

Now, I ask you, if you had to assign dozens of IC Designers, software,
and support people (perhaps this number is in the 100's) to support a
business, how hard is it to do an ROI?

One must have assumed that the entire market was just going to explode,
or the market was going to shake out quickly.

I can understand optimism. I can not understand believing that one
could get even 50% of any market with so many competitors, and so many
BIG competitors (IBM, Fujitsu, Toshiba ...).

I can see a BIG company making a ten year effort and realizing that the
payback may not come for a long time, but even then, there is a board of
directors, and that board has got to be pretty ugly right now. Wouldn't
want to be in those board rooms explaining why the new star (Structured
ASICs) are still losing money, and why they are draining resources, and
knocking the gross margins down.

So, a simple review:

ASIC business = really HUGE $ and increasing. Design starts slowing,
and reducing due to equally HUGE NRE, and issues with ultra deep
submicron technolgy leading to expensive failures (or too many million $
mask sets).

Companies making business decisions to no longer use ASICs (losing too
much money, time, etc.).

FPGA business picking up lots of what used to be ASIC business.

ASIC IC designers looking for jobs (we are hiring, send me your resume).

ASIC IC designers taking jobs designing with FPGAs.

Structured ASIC business looking shakey. Were 13 players. Now ten.
Largest just threw in the towel.

Austin

 

[Rob]

Did you get a Hardcopy II price from Altera, or is that what you mean here
?

Prices were from Altera and Rapid Chip. And both vendors came back with
similar pricing. The ASIC is being done by KLSI. KLSI's NRE was also very
reasonable.

Do you have any current consumption ratios ?

No, I don't have this information presently at hand.



"Jim Granville" <no.spam@designtools.co.nz> wrote in message
news:441261f2$1@clear.net.nz...

Rob wrote:
Austin,


Let those nine companies circle the drain, the plug has been pulled.


I'm really having great difficulty trying to understand why you think the
ASIC/ structured ASIC market is going to die. Can you give us Xilinx's
roadmap/business model that will compete?

Don't forget Xilinx have a (large) vested interest in talking down any
ASIC MASK flows.


For instance: can you give me a 60k/annum pricing for a product that has
a 3yr life--total pcs 180k of a 375k Gate device with 3Mbit of on chip
ram and 4 PLL's? And I'll compare it to my quote from our ASIC vendor.
When we started this design we were in a V2PRO30, since then our design
has grown beyond the limits of this device. But since I only have
pricing on the V2P30 my math will have to be based on this part. I will
only give percentages as it would not be prudent for me to reveal the
actual numbers.

The ASIC is 8x cheaper than the V2P part. How much more lower would the
ASIC be when compared to an FPGA that could hold our current design? It
is very easy to see that we save the company BIG $$ by going to an ASIC.
The structured ASIC pricing was approx 4x cheaper, which is still very
much cheaper than going with an FPGA.

Did you get a Hardcopy II price from Altera, or is that what you mean here
?

Do you have any current consumption ratios ?

Xilinx has decided to ignore this market, based on one of your
posts--155M is too small for a 2B dollar company.

That has to be a very hard number to quantify reliably - for example, I
doubt if Altera's HardCopy is in that pigenhole, they will be called
FPGA's.
Altera only has to hit ~15% revenue via HardCopy, to equal that number.

Another way to approach this, is the FSA just said their members hit
$40B last year, and they are only a portion of FAB runs.
TSMC alone is presently close to $10B/yr, at the FAB end.

Everything a FAB makes, is an ASIC - a large chunk will not be reachable
by FPGAs due to sheer low power, or Analog features ( tho Actel can start
to argue on that last point, at least for average analog features ).

-jg