EDK : FSL macros defined by Xilinx are wrong

[Austin Lesea]

The temptation is great,

Austin

Simon Peacock wrote:

but sarcasm is so much better than a pointy stick.

Simon

"austin" <austin@xilinx.com> wrote in message
news:dude5h$ar25@xco-news.xilinx.com...

Duane,

Yes, I apologize for my sarcasm.

I had just read the posting concerning newsgroups, and how to get the
best answers from them. This post was a classic example of someone who
had not even had the foresight to do any research on their own.

Given that everyone who posts here has access to google (or any other
search engine), it is generally annoying to see questions that could be
answered by three minutes of browsing and reading.

Sarcasm is the weapon of the weak, and I should have been more civil,

Austin

Duane Clark wrote:


Hendra wrote:


Austin Lesea wrote:


Matt,

If you use a a cpld, you need to post in comp.arch.cpld

Austin


There is no comp.arch.cpld


I suspect he was being facetious, and just forgot the smiley

 

[Antti Lukats]

<me_2003@walla.co.il> schrieb im Newsbeitrag
news:1141549248.324091.136550@p10g2000cwp.googlegroups.com...

Hi all, my question is as follows,
I am now going through a ppc design that I would like to run as follows
:
I need to use a internal BRAM for boot sequence and a NAND FLASH to
contain all the code. the code will be placed and run on external SRAM.
My question are as follows:
1) what should I choose as internal BRAM IF OCM or PLB_CTLR ?
doesnt really matter

2) Are there any better ways to design such a system ?

what is your question? if NAND is the cheapest NV memory ? or what?

if you need more than 8MB of NV memory then NAND is a good choice

Antti

 

[MM]

To your first question:

If I understand correctly OCM runs at the CPU clock and thus anything you
put on that bus will affect the max achievable CPU speed, at least that's
the impression I got when I actually tried implementing some big OCM
memory... I believe most of the designs use PLB_BRAM controllers...

/Mikhail



<me_2003@walla.co.il> wrote in message
news:1141549248.324091.136550@p10g2000cwp.googlegroups.com...

Hi all, my question is as follows,
I am now going through a ppc design that I would like to run as follows
:
I need to use a internal BRAM for boot sequence and a NAND FLASH to
contain all the code. the code will be placed and run on external SRAM.
My question are as follows:
1) what should I choose as internal BRAM IF OCM or PLB_CTLR ?
2) Are there any better ways to design such a system ?
Thanks in advance, Mordehay?

 

[Göran Bilski]

sachink321@gmail.com wrote:

HI
how would i use internal signals in XPS for microblaze on spartan 3
fpga board.

let me explain my project
in opb_emc
im using 2 memory banks
so im having two Output enable signals
but i have only one external pin
so i need to AND these two output signals and produce a single output
this output will be given to the external signal.

but i cant understand how can we produce a logic
for these internal signals?

any ideaz

Put a util_reduced_logic core in the .mhs

Göran

 

[Thomas Stanka]

Hi,

Simon Peacock schrieb:

OK.. I admit there are a few minor players who have flash based or fuse
based FPGA's.. but then they aren't by definition field Programmable are
they?

Yes, for sure. Field programmable has nothing to do with
reconfiguration.

They are in fact very large CPLD's as a FPGA is a Field Programmable Gate
Array and Fuse devices aren't field programmable (or at least are only
one-shot) FLASH devices could be considered field programmable... but some
can't be used while a new program is getting uploaded. So that excludes
them from what I would call Field Programmable.

Ever tried to use a xilinx device while uploading them? If my memories
correct, uloading with parallel port took over a minute for the first
Virtex.

Ok, my answer on your last posting was a bit short, because a similar
thread started in comp.lang.vhdl a few days ago :=). Sorry, should have
used a full answer.

Originaly you had CPLD with less registers and weak routing abilities
providing fast pathdelays against FPGAs with more registers and good
routing but slow path delays.

Nowadays you differ between CPLD and FPGA mostly by marketing. The big
CPLDs from Altera and Lattice are AFAIK FPGAs on a technological point
of view. It seems to me only marketing to call them CPLD (maybe some
customer are used to CPLDs and would never change to Fpga).

bye Thomas

 

[Antti]

there is on very sad thing, namly as soon as you get

.... Portability ... 127

error means that you need to wait for next service pack or quickpatch.

its generic error and doesnt give any hint what is actually wrong.
like a generic root of all devil by xilinx software.

the same main.h:127 just keeps coming, in each major release, in each
service pack


Antti
PS if you need to quick test DDR2 then EDK 8.1 SP1 has DDR2 and that
does pass synthesis at least, no crash, havent tested the hardware if
it works also though.

 

[motty]

You can put a PULLDOWN directive in the UCF for those pins. Check out
the Constraints Guide, I think. Or search for PULLDOWN on the website.
There is also a default setting in one of the files if you are using
the EDK. I think it has to do with bitgen options. I can't remember
exactly where that file is though. Sorry! Alternately, you can put an
attribute in your HDL. There are multiple ways to do it.

Good luck.

 

[motty]

You can make and add an IP core just like you do for other custom
things. You just won't connect it to a bus. You still need the same
folder structure and files as you would for another core though...mpd,
pao, etc.

I have a couple of these "glue logic" cores in our project. Then you
can just connect them internally however you want to. It is easier and
cleaner than modifying the emc's logic...if you are even allowed to.

Or you can follow Goran's advice and manually add it to the mhs.
Either way.

 

[John_H]

"vssumesh" <vssumesh_asic@yahoo.com> wrote in message
news:1141713318.376695.52550@u72g2000cwu.googlegroups.com...

Hi all,
I am facing a problem with my design. In which i assigned tri
state buffers to drive a bus which is connected to sixteen identical
blocks. This bus is controlling the register updation. But in the
default configuration when all blocks are driving high impedance to the
bus the bus is going to '1' state by internal pull up. I want to know
is there any way to pull down the internal signals in the Xilinx FPGA
(specifically Virtex 4 or Virtex E).
regards
Sumesh V S

If you're talking about an internal tristate which is emulated - not
instantiated - in more recent Xilinx families and all Altera devices, you
have two solutions I can think of:

Use logic that looks for no TRI enables in order to drive the tristate low,
or
Invert your logic so the inputs to all the tristates are inverted and the
destination of those tristates is also inverted; the undriven state is still
a logic 1 but you're now inverting it at your input.

 

Austin Lesea wrote:

http://www.eetimes.com/news/semi/showArticle.jhtml;jsessionid=2VY5CYWYDOXWUQSNDBCSKH0CJUMEKJVN?articleID=181501385

Well, I guess that about wraps it up for the attempt to disguise ASIC
design as something different...

Different than the ASIC's that a number of fabless vendors produce that
we call FPGA's? The business case for in-house fab, or fabless, has
been a difficult call for the last two decades, and all I see from this
announcement is that AMD reached the point where investing in 45nm fabs
wasn't in the cards with their current volumes. When you shed your fab,
with it goes your ASIC business.

There are still plenty of places to take your ASIC design, or there
wouldn't be the ASIC's produced by fabless FPGA vendors.

 

[austin]

toys,

That was the link to LSI logic dropping their structured ASIC business.

Austin

fpga_toys@yahoo.com wrote:

Austin Lesea wrote:

http://www.eetimes.com/news/semi/showArticle.jhtml;jsessionid=2VY5CYWYDOXWUQSNDBCSKH0CJUMEKJVN?articleID=181501385

Well, I guess that about wraps it up for the attempt to disguise ASIC
design as something different...


Different than the ASIC's that a number of fabless vendors produce that
we call FPGA's? The business case for in-house fab, or fabless, has
been a difficult call for the last two decades, and all I see from this
announcement is that AMD reached the point where investing in 45nm fabs
wasn't in the cards with their current volumes. When you shed your fab,
with it goes your ASIC business.

There are still plenty of places to take your ASIC design, or there
wouldn't be the ASIC's produced by fabless FPGA vendors.

 

austin wrote:

toys,

I've objected nicely to your changing my handle from fpga_toys, to
simply toys as the obvious intent in doing so was to play the childish
name altering riddicule game.

So, I suggest that maybe the posters here might find it equally
entertaining if we play the same game with your time .... such as
altering Aus-tin to be tin-Aus-whole

 

hi
thanks a lot man
i knew ther has to be a easy way out
util_reduced_logic is the way out

thank you

Göran Bilski wrote:

sachink321@gmail.com wrote:
HI
how would i use internal signals in XPS for microblaze on spartan 3
fpga board.

let me explain my project
in opb_emc
im using 2 memory banks
so im having two Output enable signals
but i have only one external pin
so i need to AND these two output signals and produce a single output
this output will be given to the external signal.

but i cant understand how can we produce a logic
for these internal signals?

any ideaz


Put a util_reduced_logic core in the .mhs

Göran

 

Austin Lesea wrote:

http://www.eetimes.com/news/semi/showArticle.jhtml;jsessionid=2VY5CYWYDOXWUQSNDBCSKH0CJUMEKJVN?articleID=181501385

Well, I guess that about wraps it up for the attempt to disguise ASIC
design as something different...

In the '80s small ASIC designs (large TTL designs) became PLD's. In the
'90's small ASIC designs (large PLD designs) became FPGAs. In this
decade small ASIC designs are still becoming FPGAs, just larger ones.

ASIC are now system level integration, not logic subsystems. And the
ASIC market continues to grow:


http://www.eetimes.com/conf/dac/showArticle.jhtml?articleID=164302400

ASIC sales in 2005 are estimated to be about $20B, while Xilinx's sales
are about $1.3B.

ASIC's have always been something different .... bigger, faster, and
larger market.

 

[Peter Alfke]

fpga_toys@yahoo.com wrote:

Different than the ASIC's that a number of fabless vendors produce that
we call FPGA's? The business case for in-house fab, or fabless, has
been a difficult call for the last two decades, and all I see from this
announcement is that AMD reached the point where investing in 45nm fabs
wasn't in the cards with their current volumes. When you shed your fab,
with it goes your ASIC business.

Mr Anonymous, who hides his name, but doesn't want to be called "toys":
Why do you bring up AMD, which was not at all mentioned in the press
release.
Just to stir the pot and create additional controversy?

There is understandable glee in the FPGA camp when one of the most
ardent proponents of "Structured ASICs" (the "FPGA-killer technology")
finally, after many unsuccessful money-losing years, throws in the
towel. Basta, finito, kaput.
So it is now clear again, as it has always been:
There are ASICs (with their well-known technical advantages and
economically-based disadvantages) and there are FPGAs (not as big, not
as fast, and not as frugal, but increasingly popular for reasonable
designs in reasonble volume, and far less risky).
Both camps will survive, but the trend is in favor of FPGAs.

Please, don't throw any more of your venom at this newsgroup.
You have stopped being entertaining or informative, a long time ago.
Peter Alfke, from home.

 

Peter Alfke wrote:

fpga_toys@yahoo.com wrote:
Different than the ASIC's that a number of fabless vendors produce that
we call FPGA's? The business case for in-house fab, or fabless, has
been a difficult call for the last two decades, and all I see from this
announcement is that AMD reached the point where investing in 45nm fabs
wasn't in the cards with their current volumes. When you shed your fab,
with it goes your ASIC business.

Mr Anonymous, who hides his name, but doesn't want to be called "toys":
Why do you bring up AMD, which was not at all mentioned in the press
release.
Just to stir the pot and create additional controversy?

Because, they were one of the most vocal camps against fabless
technology a few years back. That we now have LSI going fabless is a
material part of the discussion.

There is understandable glee in the FPGA camp when one of the most
ardent proponents of "Structured ASICs" (the "FPGA-killer technology")
finally, after many unsuccessful money-losing years, throws in the
towel. Basta, finito, kaput.
So it is now clear again, as it has always been:
There are ASICs (with their well-known technical advantages and
economically-based disadvantages) and there are FPGAs (not as big, not
as fast, and not as frugal, but increasingly popular for reasonable
designs in reasonble volume, and far less risky).
Both camps will survive, but the trend is in favor of FPGAs.

I agree both will survive to some extent for a very long time. Till at
least until the next technology comes along and replaces FPGA's as the
small ASIC step child, as FPGA's did PLDs in the last decade. The the
title the Austin puts forth, and the one liner in the body is laced
with sarcastic riddicule of the ASIC camp with the assumed thought that
somehow Xilinx has killed ASIC's. The fairy land here, is that Xilinx
has grown to be a pretty large step child to the ASIC industry, and
still growing - but that is hardly making Xilinx a giant slayer.

In fact, the most obvious thing missed in Austins post, is that he is
openly mocking the very potential clients that Xilinx needs for it's
high end market .... smaller ASIC designers wishing to move down to
FPGAs to balance NRE and production run costs. That is not going to win
Xilinx those customers.

Please, don't throw any more of your venom at this newsgroup.
You have stopped being entertaining or informative, a long time ago.
Peter Alfke, from home.

The venom is on your and Austin's part. Like where in the hell do you
get off on asking someone to leave CAF because they disagree with you?

I say take a flying hike yourself .... and as another reader commented
to this thread via email earlier .... that is "Mr. Toys to you".

Controversy, disagreement, debate, even when very passionate, NEVER
EVER justify your and Austins directly personal attacks in this forum.

Since you continue to press Tin-Aus's slur in your own way, let's adopt
"Peter Principle" for you, if you want to continue making discussions
in this forum personal.

Otherwise, stop being childish, get over the handle I use, and stick to
the facts with informed debate (however lively that gets) as address
your position responsibly and professionally. I'm hardly the only
person using a handle in this forum ... and you have no right in hell
to riddicule anyone that does.

 

fpga_toys@yahoo.com wrote:

Peter Alfke wrote:
Mr Anonymous, who hides his name, but doesn't want to be called "toys":

I say take a flying hike yourself .... and as another reader commented
to this thread via email earlier .... that is "Mr. Toys to you".

hmm ... I got that slightly wrong ... the other readers humor was:

<fpga_toys@yahoo.com> wrote:

austin wrote:
toys,

I was expecting your reply to be "That's _Mister_ Toys to you."

 

[Marc Randolph]

fpga_toys@yahoo.com wrote:
[...]

Since you continue to press Tin-Aus's slur in your own way, let's adopt
"Peter Principle" for you, if you want to continue making discussions
in this forum personal.

Otherwise, stop being childish, get over the handle I use, and stick to
the facts with informed debate (however lively that gets) as address
your position responsibly and professionally. I'm hardly the only
person using a handle in this forum ... and you have no right in hell
to riddicule anyone that does.

John,

You're not the only one using a handle on this newsgroup, and of others
that do, if they are long, they sometimes get abbreviated, just like
yours. Austin isn't the only one that does it, and he doesn't do it
just to you.

Why do you insist on dragging this nonsense out? Why not sign the
posts like you did when you first started posting under this alias?

http://groups.google.com/group/comp.arch.fpga/msg/823612151f9a694a

If you don't want to use John Bass, fine - pick a fake name.

I'll never defend Austin's attitude on this newsgroup, but fpga_toys is
obviously not a name, and "toys" is not a slur. But I suspect you know
that, because more than a month went by before you objected to him
using it. And even if you truely think it is a slur, you could end all
this stupidity by simply added four more characters to the end of your
post. I'm quite certain that that little gesture, based upon past
history, will get Austin and everyone else to addressing you in a
manner that you would not find offensive.

This newsgroup is a pretty professional newsgroup, and addressing the
person by name that one is replying to is a polite practice. That you
haven't provided a name recently isn't anyone elses fault.

As for this topic, I agree that Austin's subject on the original post
was someone misleading, but that's par for the course. All the
information was made available for someone to make their own decision
on the matter.

Marc

 

[Michael SchĂśberl]

bjzhangwn schrieb:

Hi,I now use the pio mode 0 to wrrite the registers in the device ,but
the device seem not to recceive the data [...]

standard PIO-0 is really slow and no miracle ...

- read the spec again
- verify your simulation model, simulate again
- read the spec again
- measure the voltages and timings (with a suitable
oscilloscope and logic analyzer)
- read the spec again
- measure and compare voltages and timings in a
working application (e.g. a regular pc)
- start from beginning


I think these steps are more than obvious and if
nothing of that came across your mind ... uhm ...
well - maybe you should do something different


bye,
Michael

 

Marc Randolph wrote:

John,

You're not the only one using a handle on this newsgroup, and of others
that do, if they are long, they sometimes get abbreviated, just like
yours. Austin isn't the only one that does it, and he doesn't do it
just to you.

Actually, Austin has addressed replys to me as John back in Jan. And
despite my objections, or specifically because I objected, he's choosen
to push the toy button as well as other much more direct attacks. I
was polite and firm asking that he stop.

Two, or three, or more can play his game. As I suggested quiet some
time ago, if he wants to play nasty that way, then he becomes
responsible for setting the tone and nature in which others can, and
will, interact with him as well.