EDK : FSL macros defined by Xilinx are wrong

[Austin Lesea]

Chris,

Have you looked at the device in FPGA_Editor?

You should.

Austin

Chris Francis wrote:

Hi (again!)

As we're still looking at this device on quite a low level (we're trying
to look at implementing a model of neurons in the brain on the device,
and in particular the connectivity) we've come across another problem in
our understanding...

When looking at the 'Hierarchical Routing Resources', the paragraph
states "... a number of resources counted between any two adjacent
switch matrix rows or columns.". Therefore, are we right in thinking
that in our device (which has 56x48 CLBs) for the '40 horizontal double
lines', from each row we can send out 40 connections (giving a total of
40x48 double connections), or is there something we've missed (as
depending on which way we look at it, it's either *loads* of
connections, or *very* few connections!). The same goes for the long
lines and hex lines etc.

Again, any pointers to documentation would be appreciated, or if someone
has the time to type a concise answer all the better (the reason we're
posting is because we can't find anything helpful, so we're hoping to
learn from your experience, rather than just leeching off you!)

Thanks again
Chris

 

[Austin Lesea]

toys,

Open FPGA_Editor. Start a new project for a part. Add nothing (or
maybe an output pin that drives a '1').

Write out the .ncd. That is the 'empty' design, with all rules checked
and met.

Start from there.

Austin

fpga_toys@yahoo.com wrote:

Austin Lesea wrote:

Chris,

Have you looked at the device in FPGA_Editor?

You should.


It would be nice if the fpga editor would allow you to start it without
a design loaded, select the device that you want to explore/edit/design
with, go into edit mode, and save the resulting design from the editing
(if any). Or open an existing design, and be able to extend it by
editing iob's and slices that do not have design elements loaded. ...
but that is another point ...

From the posters second question, it's likely he's not familar with how
to operate fpga editor.

Actually just looking at it probably will not answer his question, as
the defaults don't show you very much. He needs to get close in, turn
on all the resources (as many are turned off to reduce the visual
clutter), and put it in edit mode. IE from the tool bar, where the
yellow controls are:

1) turn on local lines

2) turn on long lines

3) turn on pin wires

4) turn on Pips

5) turn on switch boxes

Then from the loaded design, select a site entry from list 1, click on
the red find tool to zoom in on it, then zoom out one or two steps and
look around that are in detail.

start clicking on the circles at the edges of the switch boxes to see
the connection resources available, and open up the clb and iob blocks
that have design elements to see the internal connections.

 

[Austin Lesea]

Matt,

If you use a a cpld, you need to post in comp.arch.cpld

Austin

Matt Clement wrote:

Hey guys/gals

What are the advantages and disadvantages of using a CPLD instead of using
an FPGA for a design?

Thanks

 

[Anonymous]

"Matt Clement" <clement@nanotechsys.com> wrote in message
news:Qp1Of.111$eP4.86@trnddc05...

Hey guys/gals

What are the advantages and disadvantages of using a CPLD instead of using
an FPGA for a design?

Thanks

lower cost, less power consumption, smaller size, easier configuration

 

Austin Lesea wrote:

toys,

Open FPGA_Editor. Start a new project for a part. Add nothing (or
maybe an output pin that drives a '1').

Write out the .ncd. That is the 'empty' design, with all rules checked
and met.

Start from there.

Austin

Maybe that's fixed in current release .... I just get:

/home/jbass/bin/fpga_editor: line 5: 26156 Segmentation fault
/raid/xilinx/bin/lin/fpga_editor $*

 

[A. Karttunen]

zhangweidai@gmail.com wrote:

I have a Spartan 3 starter kit. Im going to build an expansion board
that will have some more components on it. does anyone know where i can
get some examples? or guides to do this? i know im going to use a
standard 2x20 right male connector, and i the pin functions. but an
example board would be most helpful. i also want to attach some sma
connectors on it to get testpoints.

the plan might be.... build pcb layout, have expert review design,
produce gerber, and send to be printed. someone recommended 33each.com

pz

If you are using Digilent's Spartan-3 Starter Kit, then a word of
warning: Most (or at least many) of the pins on expansion connectors
are located in various IO-blocks that contain also the pins connected
to the development board's leds, 7-segment display, push-buttons,
slide-switches and what else. And as these use only
2.5 V levels, you have to use IOSTANDARD = LVCMOS25
also for your own I/O-pins in the expansion connector,
as one cannot assign different levels to the pins in ONE
and SAME IOB. (I realized this only when the ISE started giving
error messages about different voltage levels...)

What I built is a simple opto-isolator card, with which I can
control (not very fast though, because of the optos...) my TTL-level
contraptions without fearing frying the Spartan-3. There are 16
output-lines and 8 input-lines, and I use the B1-expansion connector,
because its pins are not shared with SRAM (A2 would work as well). I
built this on a stripboard, with almost all the components sitting in
DIL-16 sockets (except the regulator which feeds the 5V-side of the
board). If I had a digicamera at hand, I would post a photo of it...


I guess you have the user's guide which details the pins. If not, then
the copy can be found at Xilinx' site:
http://www.xilinx.com/bvdocs/userguides/ug130.pdf

And indeed, Digilent has many nice expansion boards:

http://www.digilentinc.com/Products/Catalog.cfm?Nav1=Products&Nav2=Accessory&Cat=Accessory
and
http://www.digilentinc.com/Products/Catalog.cfm?Nav1=Products&Nav2=Peripheral&Cat=Peripheral



Cheers,

Antti Karttunen

 

sorry about the vagueness of my project.

here's what we are doing. ive posted it up before on this forum.
http://classes.engr.oregonstate.edu/eecs/fall2005/ece441/groups/g1/skematic.htm

 

[Simon Peacock]

There is also the issue that FPGA's configuration data is stored in external
FLASH where as CPLD's are programmed.
It is actually quite easy to reprogram a FPGA on the fly and field update
the external memory while the FPGA is still running. No special hardware or
algorithms are required. Downloading a CPLD is usually done from a PC via a
JTAG cable or via a External Chip Programmer.

Simon


"Peter Alfke" <peter@xilinx.com> wrote in message
news:1141424214.234508.233260@p10g2000cwp.googlegroups.com...

There is a big difference in logic capabilities. Let's express that in
the number of flip-flops or registers:

CPLDs are good for up to 200 flip-flops, they get disproportionally
expensive for larger designs.
Modern FPGAs start at 2,000 flip-flops, and go up to to 200,000
flip-flops, plus many other circuits, like RAM, multipliers etc.

CoolRunner CPLDs offer extremely low power consumption, and small
physical size, and low cost for the smallest parts.
FPGAs fit a much wider range of applications.

The choice between the two technologies is usually quite clear-cut.
Peter Alfke, Xilinx Applications
=====================================
Matt Clement wrote:
Hey guys/gals

What are the advantages and disadvantages of using a CPLD instead of
using
an FPGA for a design?

Thanks

 

[Antti Lukats]

"wicky" <wicky.zhang@gmail.com> schrieb im Newsbeitrag
news:1141476127.310105.11510@i40g2000cwc.googlegroups.com...

Great!

But i am confused with the "uClinux" you used? why not ppclinux
distribution?

Another question, is it possible to patch the "uClinux" on V4-fx with
RTAI which do support ppclinux?

thank you!

wicky

the uclinux is there actually only naming issue, it is actually FULL
ppclinux with MMU support

Antti

 

[Gob Stopper]

yyqonline wrote:

Hi, everyone.
I want to do a presentation about the introduction about Xilinx
Chipscope on the meeting of my lab. Since I have used this software for
not a long time, I need some comments, tips, and other information
about Chipscope from you, the veteran designers of Fpga.
Any advice would be appreciated very much, and my email is
yyqonline@gmail.com.
Thanks a lot.
yours,
YuQing Youth

You need to actually read the manual and/or use it. ChipScope is a bunch
of very different tools, including some very non-real-time, and some
full real-time. Most people think of ChipScope ILA, but there's a lot
more to it than that.

GS

 

[austin]

Brian,

Here are the apologies:

I am sorry that you feel compelled to post on this subject compulsively.

I am sorry to see that you discredit yourself in public by posting a
spice fantasy.

I am sorry I took your posting seriously enough to do a real simulation
and show that there is no problem (which I knew already from the
customers that are using our parts successfully).

I am sorry that I have been unable to resolve this issue with you in a
mutually positive way.

Austin

 

[Hendra]

Austin Lesea wrote:

Matt,

If you use a a cpld, you need to post in comp.arch.cpld

Austin

There is no comp.arch.cpld

Hendra

 

[austin]

Duane,

Yes, I apologize for my sarcasm.

I had just read the posting concerning newsgroups, and how to get the
best answers from them. This post was a classic example of someone who
had not even had the foresight to do any research on their own.

Given that everyone who posts here has access to google (or any other
search engine), it is generally annoying to see questions that could be
answered by three minutes of browsing and reading.

Sarcasm is the weapon of the weak, and I should have been more civil,

Austin

Duane Clark wrote:

Hendra wrote:

Austin Lesea wrote:

Matt,

If you use a a cpld, you need to post in comp.arch.cpld

Austin


There is no comp.arch.cpld


I suspect he was being facetious, and just forgot the smiley

 

[Vladimir Bondarenko]

clarence_gra...@hotmail.com writes on Thu, Mar 2 2006 7:12 am

CG> This conference looks suspicious. How can one manage so
CG> many conferences at once?

By looking through one's fingers.

The human possibilities have some limits; this is a kind of
law, or at least, a reliable rule of thumb. Nobody can beat it.


The Magical Number Seven, Plus or Minus Two: Some Limits on Our
Capacity for Processing Information

by George A. Miller (originally published in The Psychological
Review, 1956, vol. 63, pp. 81-97)

http://www.well.com/~smalin/miller.html

GAM> I have just shown you that there is a span of absolute
GAM> judgment that can distinguish about seven categories and
GAM> that there is a span of attention that will encompass
GAM> about six objects at a glance.


http://groups.google.com/group/sci.math.symbolic/msg/739a2eb2ef30dee7

Richard J. Fateman writes on Fri, Mar 3 2006 1:06 am

RJF> I think that one answer is to accept most, if not all,
RJF> papers, charge high registration fees, and hope that
RJF> the people who attend don't care about the quality of
RJF> the papers, as long as the food is good.

Often, absence of professional critics ends in bad way.

Until recently, there was not a single professional publicly
available Maple review; now look what has happened to Maple.

http://maple.bug-list.org/maple-crisis.php

In part, because not a single human being can test software
efficiently; more detail in our beta 0.2.

 

[wicky]

oh, I see. it seems that you only use the convenient building process
of uClinux and in fact the source code is based on ppclinux dist. am I
right?

thank you!

wicky

 

[Thomas Stanka]

Hallo,

Simon Peacock schrieb:

There is also the issue that FPGA's configuration data is stored in external
FLASH where as CPLD's are programmed.
It is actually quite easy to reprogram a FPGA on the fly and field update
the external memory while the FPGA is still running. No special hardware or
algorithms are required. Downloading a CPLD is usually done from a PC via a
JTAG cable or via a External Chip Programmer

This is wrong. At least if you accept other fpga vendors beside Xilinx
*g*

 

[Simon Peacock]

OK.. I admit there are a few minor players who have flash based or fuse
based FPGA's.. but then they aren't by definition field Programmable are
they?
They are in fact very large CPLD's as a FPGA is a Field Programmable Gate
Array and Fuse devices aren't field programmable (or at least are only
one-shot) FLASH devices could be considered field programmable... but some
can't be used while a new program is getting uploaded. So that excludes
them from what I would call Field Programmable.

Although some people might disagree.. I believe that A&X do hold the lions
share of the market so RAM based rocks for now... until nano-tube becomes
the fad.

Simon

"Thomas Stanka" <usenet_10@stanka-web.de> wrote in message
news:1141631210.694896.38720@u72g2000cwu.googlegroups.com...

Hallo,

Simon Peacock schrieb:

There is also the issue that FPGA's configuration data is stored in
external
FLASH where as CPLD's are programmed.
It is actually quite easy to reprogram a FPGA on the fly and field
update
the external memory while the FPGA is still running. No special
hardware or
algorithms are required. Downloading a CPLD is usually done from a PC
via a
JTAG cable or via a External Chip Programmer

This is wrong. At least if you accept other fpga vendors beside Xilinx
*g*

 

[Michael Schöberl]

bjzhangwn schrieb:

I want to know the default pio mode when device reset and powup,and if
the udma mode is surported when device reset and power up!thanks!

page 374 of the t13 spec/1410D revision 3b ... chapter 10.2.1
"Peripherals reporting support for PIO mode 3 or 4 shall power-up in PIO
mode 0, 1 or 2."

as the PIO timings are minimum I would assume worst case ...
this is power up in PIO mode 0

I could not find any definition for UDMA you should set the
UDMA mode after each power up


bye,
Michael

 

Hi,
i think u should clkout pin for verification.

 

[Alex]

Hi.

For the begining, the approach you described is fine (later you might want
to read out the signals from
your asic to the fpga, process them, etc.). From engineering point of
view, just be careful with signal driving.
I.e. use dedicated pins for clocks (check the xilinx manual), check the
impidance of the connection path (in some cases you
might want to place a pulling resistor, etc. etc.).
Regards
Alex

Hi,
I have a custom ASIC and I would like to interface this with my XUP V2P
(Xilinx
VII Pro) board. I am new to using the Xilinx boards. Please suggest a
simple
way to generate a clock from the FPGA and few synchronised control
signals
with
this clock. I have to feed the clock and the control signals to ASIC.
Basically
the FPGA is acting as a controller for the ASIC (The ASIC is on a simple
PCB, The ASIC is implemented using 0.12 micron libraries and run at 1.2
V).

Here is how my perceived test setup looks like.

FPGA XUP V2P --> Clk and Control Signals for ASIC --> ASIC | --
Oscilloscope for tracking signals

Please suggest a simpler method as I am just starting a project with the
FPGA.
I would be very thankful for any help.