EDK : FSL macros defined by Xilinx are wrong

Augast15 wrote:
hi,
There is 4.5 V supply for entire circuit throughout the board.

I am testing with schmitt trigger today
thanx guies
Can you give the full part number ?
You do realise the 95108 will get warm, anyway, because of
the high Icc - have you measured just how much current it
draws ?
'Getting heated' is not quite good enough...
-jg
 
bijoy wrote:
Object 'aw' cannot be used within the same interface as it is declared.
You could pass the generics as natural
and do the vector conversions elsewhere
as shown below.

-- Mike Treseler
--____________________________
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.numeric_std.all;

entity fifo is
generic(AW : natural := 16;
PROG_EMPTY_THD : natural := 255;
PROG_FULL_THD : natural := 22222);
port (rst : in std_logic;
write_address : out unsigned(AW-1 downto 0);
read_address : out unsigned(AW-1 downto 0);
wr_clk : in std_logic);
end entity fifo;

architecture synth of fifo is
subtype vec is unsigned (aw downto 0);
constant empty_c : vec := to_unsigned(PROG_EMPTY_THD, AW);
constant full_c : vec := to_unsigned(PROG_FULL_THD, AW);
begin -- architecture synth
end architecture synth;

-- vcom -93 -quiet -work work /evtfs/home/tres/vhdl/play/fifo.vhd
-- Compilation finished at Mon Feb 27 11:12:45
 
Hello,
Could U please suggest me a development board which really supports
partial/dynamic reconfiguration, satisfying one crucial requirement:

** being shipped with one or more reference designs exploiting
partial/dynamic reconf **

It would also be nice if the board:
- exploited FPGA self-reconf capabilities (e.g., the Xilinx ICAP
component)
- cost less than 1000 $
- had an embedded OS ported on it

I of course know not all these requirements can be satisfied at the
same time!! :)
the OS is not really important for now...

Many many thanks for your help

pablo
Hi pablo,

we have developed a rapid prototyping system with partial
reconfiguration in mind (and currently working on another one...). For
more information visit
http://www.raptor2000.de
http://www.raptor2000.de/sct/extern/raptor2000/module/
http://www.raptor2000.de/sct/extern/raptor2000/hauptplatine/
(mostly in german...sorry for that). Feel free to contact us for more
information, we are also working on partial reconfiguration.

Regards

Jens
 
I soldered a PQFP144 package with one of those dull pointed radio shack
irons. Used a lot of solder flux and dragged the tip along the 4 sides
of the chip. Worked great. Out of the two chips I soldered I had one
bridge. (which I found before the smoke test ;) ) I haven't had to do
one of those in a few years, but now I have a much better solder statio
so hopefully I could do better this time. :)

I was thinking about a transistor based computer last night. What kind
of memory can I use in a transistor computer without cheating? Core
memory? Should I just have a goal of "transistor CPU" and consider the
ram a peripheral?

One guy built a relay computer but used a 62256 for ram. :)
 
Jan Panteltje wrote:
On a sunny day (26 Feb 2006 15:33:20 -0800) it happened "Isaac Bosompem"
x86asm@gmail.com> wrote in
1140996800.146251.277360@e56g2000cwe.googlegroups.com>:

For myself, I hand-built a Z80 SBC about 2 yrs ago, it still works
today :) :
I clocked the CPU @ 2.45Mhz (same clock into USART), have 2KB of flash
and 32KB of RAM and a single 8-bit output port. It is a nice
development system. I wrote some IEEE754 FP library in Z80 assembly. It
was relatively painless since I am fairly comfortable with the x86 and
scores other CPU's instruction set.

Hey, Z80 cool.
I build a Z80 system in the eighties, needed an OS too, so I wrote a CP/M
emulator for it, disassembler, practically any application soft you can think
of, has even audio audio editor, and then wrote a multitasking kernel for the
z80 that ran text windows and mouse... then the 64 kByte was full.
http://panteltje.com/panteltje/z80/index.html
diagrams are there too, the thing is in the attic, 2 euro card backplanes
with CPU, IO (EPROM programmer), serial IO, DRAM RAM disk, VDU,
more, cannot remember.... lots of plug-in Euro cards.
But honestly I would not want to go back to Z80 today.
Should take some pictures some day, probably the EPROMS are duff by now...
For 1 M$ you can buy it and the rights to the CP/M emulator for embedded ;-)
However the multitasker is still on 5 inch flop, and I have no way these days
to make a copy..
That dz80 disassembler was actually one of my first C programs, and it shows....
People seem to be using it though.
Neat site, your system is far more complex than mine, from the
schematics I can see you are using some form of memory banking? I opted
out of using banking and DMA to make it easy for me to build. I will
take a look at your source, thanks for sharing ! :)

-Isaac
 
On a sunny day (27 Feb 2006 13:52:19 -0800) it happened "Isaac Bosompem"
<x86asm@gmail.com> wrote in
<1141077139.844754.322250@i40g2000cwc.googlegroups.com>:

Jan Panteltje wrote:
On a sunny day (26 Feb 2006 15:33:20 -0800) it happened "Isaac Bosompem"
x86asm@gmail.com> wrote in
1140996800.146251.277360@e56g2000cwe.googlegroups.com>:

For myself, I hand-built a Z80 SBC about 2 yrs ago, it still works
today :) :
I clocked the CPU @ 2.45Mhz (same clock into USART), have 2KB of flash
and 32KB of RAM and a single 8-bit output port. It is a nice
development system. I wrote some IEEE754 FP library in Z80 assembly. It
was relatively painless since I am fairly comfortable with the x86 and
scores other CPU's instruction set.

Hey, Z80 cool.
I build a Z80 system in the eighties, needed an OS too, so I wrote a CP/M
emulator for it, disassembler, practically any application soft you can think
of, has even audio audio editor, and then wrote a multitasking kernel for the
z80 that ran text windows and mouse... then the 64 kByte was full.
http://panteltje.com/panteltje/z80/index.html
diagrams are there too, the thing is in the attic, 2 euro card backplanes
with CPU, IO (EPROM programmer), serial IO, DRAM RAM disk, VDU,
more, cannot remember.... lots of plug-in Euro cards.
But honestly I would not want to go back to Z80 today.
Should take some pictures some day, probably the EPROMS are duff by now...
For 1 M$ you can buy it and the rights to the CP/M emulator for embedded ;-)
However the multitasker is still on 5 inch flop, and I have no way these days
to make a copy..
That dz80 disassembler was actually one of my first C programs, and it shows....
People seem to be using it though.

Neat site, your system is far more complex than mine, from the
schematics I can see you are using some form of memory banking?
It is the 265 kB dynamic RAMdisk.
It is addressed as floppy drive B
It has its own refresh, the Z80 main memory was originally 64k dynamic ram,
but as soon as I could get 32 kB static I replaced the main memory by 2 of those.

I opted
out of using banking and DMA to make it easy for me to build. I will
take a look at your source, thanks for sharing ! :)
Right, no DMA needed for the floppy, but the floppy controller used a FDC8072A
(as in IBM PC) and an analog PLL :)
In polling!
There is a DMA, but never used it for floppy transfers.
The other oddity is the display, i t is IO mapped, has its own memory.
The processor has to write a display address and data for each byte via IO.
Exactly the same mechanism as the RAM disk, but now with static RAM.
I also used the display memory (the invisible part) to store the CCP for warm boot....
Faster :)
 
fpga_toys@yahoo.com wrote:
Josh Rosen wrote:
I suspect, but didn't figure it out, that there is a Booth Recoding
analog for such a divider design. You can use the top bits of the
remainer to select the shift amount, which cuts the cycles in half for
a serial design, so I didn't worry it that hard.
This is the two bit at a time algorithm that I was talking about. Back in
the 70s this was the most cost effective way to implement division.

Is the two bit at a time algorithm a Booth Recoding analog, or variable
shifter algorithm?

Modern machines, and FPGAs, have fast multipliers so convergence division is the
best choice today.

Except for the fact that logjam is "I'm building a 64bit ALU using
standard TTL devices."
As noted earlier, there are sub-quadratic combinitorial designs for
both multiplication and division even when working with basic gates.
"Sub-quadratic" refers to the amount of hardware.
They are at worst linear in terms of delay.

Note that in two dimensions, quadratic in the amount of hardware
implies at least linear in the amount of delay.
 
ML wrote:
Hi all, for a Virtex II part, for slave serial mode, can I REALLY leave M1,
M2, M3 pins floating or is it safer to tie them to VCCaux ?

ML
Don't float these. This is almost never a good idea on control signals.
 
Jim's right,

CPLDs are power hungry... 300-400mA is no problem for bigger ones, there's
an equation to work it out somewhere... From
http://direct.xilinx.com/bvdocs/publications/DS066.pdf

You have ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f

say the valid range is 180 - 250 mA for high performance Then you have to
look at the package thermal characteristics for the package you use,
(PLCC-84 / PQFP-100 / TQFP -100 / PQFP - 160) In the document
http://www.xilinx.com/bvdocs/userguides/ug112.pdf to calculate the external
temperature.

I have some 95288 devices that run at 40-50 degrees, which is backed up by
these equations. Note that your finger is quite a good thermometer, if it
feels warm, its probably 40-50 degrees, if its not possible to touch for a
prolonged period it closer to ~60, and if you simply cant touch it it's ~70,
if you look at your finger and see XC95108 burned in it... then it's hotter
still =)

Anyways, post more info, an unusually heated CPLD could be due to many
factors.

Ben

"Jim Granville" <no.spam@designtools.co.nz> wrote in message
news:44034412$1@clear.net.nz...
Augast15 wrote:
hi,
There is 4.5 V supply for entire circuit throughout the board.

I am testing with schmitt trigger today thanx guies

Can you give the full part number ?
You do realise the 95108 will get warm, anyway, because of
the high Icc - have you measured just how much current it
draws ?
'Getting heated' is not quite good enough...
-jg
 
Benjamin Todd wrote:
Jim's right,

CPLDs are power hungry... 300-400mA is no problem for bigger ones, there's
an equation to work it out somewhere... From
http://direct.xilinx.com/bvdocs/publications/DS066.pdf

You have ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f

say the valid range is 180 - 250 mA for high performance Then you have to
look at the package thermal characteristics for the package you use,
(PLCC-84 / PQFP-100 / TQFP -100 / PQFP - 160) In the document
http://www.xilinx.com/bvdocs/userguides/ug112.pdf to calculate the external
temperature.

I have some 95288 devices that run at 40-50 degrees, which is backed up by
these equations. Note that your finger is quite a good thermometer, if it
feels warm, its probably 40-50 degrees, if its not possible to touch for a
prolonged period it closer to ~60, and if you simply cant touch it it's ~70,
if you look at your finger and see XC95108 burned in it... then it's hotter
still =)
It's the other way round - fingerprint burnt into the plastic! I once
put a finger on a chip that had been inserted into the socket the wrong
way round, so I know from experience. 8-(

The chip actually worked when it was inserted correctly, to my
surprise.

Leon
 
Thanks I'm going to read taht right away ;-)

Benjamin Todd wrote:
I agree,

check Xilinx Application Note 73
http://direct.xilinx.com/bvdocs/appnotes/xapp073.pdf

One of the last pages outlines the good approaches for decoupling.

Ben

"PeteS" <ps@fleetwoodmobile.com> wrote in message
news:1141118118.178506.30000@p10g2000cwp.googlegroups.com...

:) wrote:

Hey !

Cool everything fit into my XC9572 and work like a charm :)

Now should I used some decoupling for the xc9572, I/O change at low
freq (around 2kHz ).

My question is how and how much ;-)

:)

If you aren't switching a huge number of outputs, one 0.01uF or 0.1uF
cap per power pin (there are three) and a single bulk cap of about 1uF
should be perfectly adequate. I use that on a device connected to an
AC97 chain (clock at 12.288MHz, outbound stream at 256kb/s) and it
works just fine.

Cheers

PeteS
 
if you dont tel what your problem is how can anyone help?

IO cells powered with 2.5V can not drive aboe 2.5 and have
limited input voltage tolerance compared to 3.3v powered IO

but you can probably use LVTTL 3.3V iostandard even if
bank vccio is set to 2.5, but that depends on the application
 
Jim Granville wrote:

The simplest export scheme is SPI, which is also much faster than
i2c. i2c also has poorer noise immunity, so that needs watching in a
Motor Controller app. That said, if you can only get your DACs in
i2c, then the decision is made for you. An i2c master will need a
manager state engine, to handle ACK/NACK instances, and bus lockup
recovery, as well as organise the address / data. -jg
There are both I2C and SPI (master) cores on opencores. I've used both
and they work for me.

Regards,
Mark
 
I pass the input pulses through a shift register. For example, the
verilog equivalent is as follows
always @(posedge clk3 or negedge reset_n)
begin
if(~reset_n)
begin
delay_reg[0:29] <= 30'h000000;
end
else
begin
delay_reg[0:29] <= {video_in, delay_reg[0:28]};
end
end
assign delayed_video = delay_reg1[25];
So, the input pulses are delayed by 26 clock cycles.
Hope this makes things a little clear
 
I'd go for SPI for loading a DAC under FPGA control.
It is simple enough to do with minimal logic.

You do not need the sophistication of I2C.

On the subject of I2C master hardware, IMHO they're a bit of a waste of
resources. It is not much effort to bit-bash master behaviour. Why poll some
I2C widget when you can simply poll the I2C lines.

I2C slave hardware, now that is something worth doing.
 
"nezhate" <mazouz.nezhate@gmail.com> writes:
Hi all, I want to use a small cricuit (written in verilog and was
designed using ISE 3) in an other project using ISE 8.1. the problem is
that under ISE 3 the circuit worked perfectly, and under ISE 8.1 the is
an error. why this occur ?
Probably because you're not rubbing together a regurgitative purwell and
a supramitive wennelsprock.

You might get better results after reading:

http://www.catb.org/~esr/faqs/smart-questions.html
 
Peter Alfke wrote:
The difference between SRLs and "normal" shift registers is that the SRLs
use short-time capacitive storage between adjacent latches,
Doesn't this impose a maximum time for the clock to be in one state,
as compared to a fully static approach?
 
Thanks for the clarification, Peter. Austin lead some of us here (me
at least) to believe that the SRL might effectively preserve the
intermediate level within the shift operation, pushing the
metastability issue to the other side of the SRL.

It's good to know they can eliminate sampling uncertainty in a simple,
unconstrained SRL delay chain.
 
Well, there is always the inherent sampling time uncertainty of one
period of the asynchronous clock. I would reduce that by using a really
fast clock, like 200 MHz+.
Peter Alfke
 
Peter Alfke wrote:
Not externally, but inside the SRL there is (I think) a clock
differentiator. The idea is to put a low-pass filter between adjacent
latches, and make the transfer pulse so short, that the transfer is
only of the old, stable dta, not of the just arriving data. That avoids
any race condition. The conventional master-slave flip-flop uses a more
brute-force approach that requires two latches.
The "low-pass filter, clock differentator" approach was popular 50
years ago, when discrete transistors were expensive, and resistors and
capacitors were cheap.
I thought most modern LOGIC devices FlipFlips, were built using
transmission gates - which I think is what you are talking about with
the SRL's ?
eg my classic 74LVC74 data, shows 4 OR gates, and 4 transmission gates.

-jg
 

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