EDK : FSL macros defined by Xilinx are wrong

Logjam, it is hard for a rader of this newsgroup to understand why you
are doing what you are doing.
Why a combinatorial divider, when division is a rare operation, and
sequential circuits are more efficient?
And why insist on a 30-year old technology?
If you had picked a 50-year old technology, you would use Germanium
transistors, diodes, resistors, and capacitors, and you would really
learn the very details of circuit design. (I did, it was fun while
there was nothing better available!)
Or a 20-year old technology, using AMD bit-slice (2900) chips?
Or a 10-year-old original FPGA technology (XC3000), where all logic is
implemented in LUTs and flip-flops?

If you absolutely want to make life tough for yourself, what is so
special about 1975-vintage circuits? Just nostalgia, and those lovely
yellow books?

Peter Alfke, Xilinx Applications
=======================
logjam wrote:
Frist a little bit of information before my question. I don't know
where the best place is for this question. I'm building a 64bit ALU
using standard TTL devices. I made a 4bit adder with fast carry,
combined 4 of those with 16 AND gates (ends up as a 4x4=8bit
multiplier), and then combined 64 groups to provide 15 partial products
to a wallace tree (which I also had to make a model for). A final
summing adder takes the two partial products from the wallace tree and
adds them together. This final summing adder is built using 181 and
182 TTL devices, so I can also subtract and preform basic logic
operations if necessary.

I basically followed the datasheet from Texas Instruments from 1975.
;) I had to make models of the 74274 and 74275 because they weren't
included as standard Altera macros I guess (which is very
understandable... ;) )

Anyway, my schematic program produces an EDIF netlist which I'm able to
import into Altera's software and compile and simulate my schematic for
their FPGA devices. I've been simulating my project with great
success. So we are on topic with the whole FPGA thing. :)

Now on to my question. Is there a simple combinatorial design for
division? So far the whole schematic is made using "Combinatorial
logic"? I'm not sure that's the right word. The ALU can perform any
function without clock inputs, its also faster than a lot of the other
methods I've found. For example, calculating one partial product at a
time for multiplication.

For more info on the multiplication circuit I've described you can look
at the datasheet below. On page 7-398 through 7-400 is a schematic for
a 16x16 bit multiplier. Mine is pretty much the same, except mine is
4x larger. This is the first time I've used D size schematic layout.
:) For more informatio

http://www.tech-systems-labs.com/booksdata/TI-DATA-1976.pdf

Any hints for what I should be looking for or links would be great.
Searching for combinatorial division I found what looked like to be
some good hits, but the website was in the CGI error mood. :(
Click to expand...
 
all hydraxc modules have USB OTG connector on them so the LEEB isnt
even required, just power the module with 3.3V and plug the USB
connector. The USB chip is philips ISP1671

developing and validating (eg passing USB OTG compliance testing) an HS
OTG IP core is not less than 1 man year. So buying an IP core or using
some other options is possible better choice

both isp150x or usb3300 can be used for the OTG IP core, but it really
isnt so reasonable to be implemented in the FPGA also from the resource
utilization, etc

so if you need HS use ISP1671 for FS speed I would use Atmel
AT90USB1287 but there are other choices also available

Antti
 
thanks Uwe, it should have been my responsibility to fix :)

well I am really busy making more reference design and firmware for the
hydraxc modules,
tested working are
u-boot (microblaze), including file load from sd-card
sd-card support in uclinux
microwindows (uclinux, direct hardware access)
some ppc demos also, ppc-linux support in progress
for the ISP1761 there are some device mode demos
mass storage device, etc, for host mode now also
a minimal standalone application that configures the
internal hub and request some descriptors from
connected device, etc..

Antti
 
Martin Bosma <martinbosma@gmail.com> wrote:
Antti, thanks for your quick reply.

Right now im investigating all possibilities. The hydraXC seems indeed
a very interesting solution. But are you sure it hasnt the isp1761 on
board in stead of the isp1671. Cause i cant find any infromation of the
isp1671.

And what do you know about integrate the PHY into the FPGA? Is it even
possible? Cause we maybe want to make an asic of the usb interface. If
it isnt possible and just use an external PHY, there are many
possibilities. Because all the phys i have seen are using an ulpi or
utmi interface. And thats what i prefer.
Click to expand...

The page
http://wiki.openchip.org/index.php/HydraXC:FAQ#What_other_components_are_on-board.3F
had it wrong. I have now corrected it


--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
 
On a sunny day (23 Feb 2006 19:27:04 -0800) it happened "Peter Alfke"
<alfke@sbcglobal.net> wrote in
<1140751624.632774.85380@u72g2000cwu.googlegroups.com>:
If you absolutely want to make life tough for yourself, what is so
special about 1975-vintage circuits? Just nostalgia, and those lovely
yellow books?

Peter Alfke, Xilinx Applications
Click to expand...
Yes Peter, way to go, use the best of teh old and new technology:
http://www.neoseeker.com/Articles/Hardware/Reviews/aopenax4btube/
 
I was under the impression that the JTAG pins were multiplexed and
could be used for IO after the programming cycle is complete. While I
never implemented this so I didn't really investigate, I always figured
that the "mode" that the device came up in would depend on the status
of certain pins at reset and multiplexing these pins would require
external logic.

Hopefully somebody with more knowledge of the subject will answer your
inquiry. If not, I would suggest reading the configuration manual very
thoroughly and you could also contact Altera and or a local FAE.
 
Nial Stewart wrote:
Not every design has the need for million gate device functionality,
Altera and Xilinx's low cost families seem to be selling in big
numbers. Sometimes it's important to push the performance of these
lower cost devices to keep costs down. Getting the same functionality
into a smaller device can also be important if power consumtion is
critical (my original point).

How many power supplies do you need for your big devices?
Click to expand...
Who said anything about C based HLL's NEEDING a large FPGA? ... The
only NEED for a large FPGA is if you are doing reconfigurable computing
on a grand scale.

C based HLL's work just fine for small devices too. Since devices get
bigger in 100% size jumps for most product lines, and the cost penalty
for using a C based HLL is under a few percent, the window for
justifying an HDL on device fit is pretty small, or non-existant. Any
project which is crammed into a device with zero headroom, probably
needs the next large size just to make sure that minor fixes don't
obsolete the board or force an expensive rework replacing the chip with
the next larger device in the middle of the production run.

The days of FPGA's being only for hardware design are slipping away.
While this group has been dominated by hardware designers using FPGA's
for hardware designs, I suspect that we will see more and more
engineers of all kinds here doing computing on FPGA's, at all levels.

That's probably true, and I expect to be using other tools as well as
VHDL in 5 years. However as John posted above, there's alot more to
implementing an FPGA design than the description used for the logic
and I think we'll still be using HDLs to get the most out of them for
a long time to come (to a bigger extent than with C/asm).
Click to expand...
Probably the biggest change is that EE's will still be putting the
chips on boards as they have always done, and the FPGA programming will
shift to systems programming staff, which are frequently Computer
Engineering folks these days (1/2 EE and 1/2 CSc, or CSc types with a
minor in the digital side of EE). Similar to the 70's transition where
EE's were doing most of the low level software design and drivers, and
it shifted to a clearer hardware/software split over time. With that,
tools that expect a designer to mentally be doing gate level timing
design are less important that higher level tools which handle that
transparently.
 
logjam wrote:

For a while I wanted to build a computer out of relays, but I'm not
that brave yet. That's a LOT of time. :)
Click to expand...
Have you considered tinker toys? IIRC the Boston Computer Museum has a
computer built out of tinker toys that is hardwired (hardsticked?) for
playing tic tac toe.

I've just completed the soldering on a 19,008 LED display. Talk about
current, the thing draws 130A! So, yes...I am crazy. :)

http://www.stockly.com/images2/060129-LED_Display_Front_2718.jpg

http://www.stockly.com/images2/060129-LED_Display_Back_2716.jpg
Click to expand...
I don't see any drive electronics. Do they all just come on at the same
time, like a giant green lamp? If they were wired in series, you could
power them from a lightning rod.
 
Jeff Cunningham wrote:
logjam wrote:

For a while I wanted to build a computer out of relays, but I'm not
that brave yet. That's a LOT of time. :)

Have you considered tinker toys? IIRC the Boston Computer Museum has a
computer built out of tinker toys that is hardwired (hardsticked?) for
playing tic tac toe.

I've just completed the soldering on a 19,008 LED display. Talk about
current, the thing draws 130A! So, yes...I am crazy. :)

http://www.stockly.com/images2/060129-LED_Display_Front_2718.jpg

http://www.stockly.com/images2/060129-LED_Display_Back_2716.jpg

I don't see any drive electronics. Do they all just come on at the same
time, like a giant green lamp? If they were wired in series, you could
power them from a lightning rod.
Click to expand...
Out of interest, I saw an old LED matrix based device for stores to
advertise things and just took a peek inside under the LED matrix and
low and behold a ton of 74LS164. Serial In Parallel Out. Unfortunately
the store was still using the device so I couldn't open it up for more
investigation :(
 
have been modified to operate with radiation-hardened magnetic RAM. I
Click to expand...
Core?


--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.
 
The display is organized as 11x1728. When I had the boards made I
thought I could handle 33 rows per refresh, but after doing duty cycle
tests on the LEDs I switched to 11. 1728 bits are loaded into 216
addressable flip flops, then the data is transfered into a second set
of storage registers which drives the display. There are only 11
columns to refresh. I organized the display this way because 8x11 is a
very nice font. The first thing I want to do is program a pong game
for the Altair. After all, the Altair and other computers of its time
were known for blinking lights. I figure this is the next evolution of
blinking lights. :) At 90ma per LED and a maximum number of LEDs on
at any given time of 1728, well, you do the math. :)
 
Have you considered tinker toys? IIRC the Boston Computer Museum has a
computer built out of tinker toys that is hardwired (hardsticked?) for
playing tic tac toe.
Click to expand...
The most interesting thing I've read yet is the simple fact that the
first relay computers could have been built as early as 1890. Maybe
we'd be running around playing StarGate, or worse...Battlestar
Galactica... :)
 
logjam wrote:
I want to do all sorts of things. After this I want to build an 8bit
computer using transistors. I saw one on the internet, but it didn't
look like it ran any decent software.
Click to expand...
Way to go :) Excellent way to gain grounding experience, as nobody
will pay you to build one today!! The oldie moldies here are likely to
enjoy gabbing about the past too.

Ignore Peter, and those that are completely clueless about what drives
hobbiests. They are the ones that are clueless for working only on
projects that yield 8 digit dollar signs.

I kept one transistor computer, actually the only small one I had
worked with ... the others were much too large to pack around,
especially the NCR 315 which was five rack bays plus the CRAM unit and
a console. It's a rare desktop PDP-8 lab machine with the smoked
plexiglass covers. If you wanted to build a transistor machine I would
suggest an original PDP-8 design as it's well documented and there is
lots of PDP-8 software. I would do it based on the original module
design, as the boards are pretty inexpensive if done as panels, and I
would use a pcb backplane instead of wirewrapping it as the original
was done. I wish I had kept one drum and tube computer too ...
especially a single rack one like a Bendix G15. Anybody have a G15
they want to send to a good home?

I guess the reason I came up with 75 is because that's the year of the
Altair and other computers becoming "popular"? It will be fun to see
what kind of computer I can design out of commonly available parts,
what it would have cost, and how fast it is. So far my initial
calculations are 4-4.5 million 32x32bit multiplications per second.
That is pretty fast, comparable to a 50MHz 486.
Click to expand...
There are a number of people now doing retro designs both in TTL with
microprocessors, and in FPGA's for similar reasons. It's fun, good
learning experience, and yields an excellent grounding in low level
design and assembly processes. There are a number of folks doing this
for both old home computers and early video games.

For a while I wanted to build a computer out of relays, but I'm not
that brave yet. That's a LOT of time. :)

I've just completed the soldering on a 19,008 LED display. Talk about
current, the thing draws 130A! So, yes...I am crazy. :)
Click to expand...
Not crazy .... DRIVEN! ... something lacking in many current college
graduates this day that went into engineer for the pay check, and not
the love of technology. If you are half way local to Colorado, look me
up. Otherwise email, there are a few of us that still love technology
for the sake of technology, rather than just a paycheck.

My home project has been taking a few thousand older FPGA's to build a
home super computer into a desktop sized box (with water cooling, and a
lot of memory, fibre channel disks, etc) .... :) It takes a lot of
current too .... a few thousand amps for even a "small" super computer.
 
On Thu, 23 Feb 2006 02:08:50 -0800, logjam wrote:


Now on to my question. Is there a simple combinatorial design for
division? So far the whole schematic is made using "Combinatorial
logic"? I'm not sure that's the right word. The ALU can perform any
function without clock inputs, its also faster than a lot of the other
methods I've found. For example, calculating one partial product at a
time for multiplication.
Click to expand...
The answer is that there is no combinatorial divider that makes sense.
Division is done by successive approximation. The simplest algorithm for
division is a one bit per cycle operation. There is also a two bit per
cycle algorithm that's pretty efficient, thats what I used in the
mini-computers that I designed in the 70s and early 80s. If you have high
speed multipliers, which modern FPGAs have in abundance, then the highest
performance algorithm is a Newton-Raphson convergence algorithm. There are
similar algorithms for square root. The clearest explanation of how to do
a convergence divide is in the Cray 1 manual, if you do a Google search
you should be able to find a copy on the web.
 
o
fpga_toys@yahoo.com wrote:
Ignore Peter, and those that are completely clueless about what drives
hobbiests. They are the ones that are clueless for working only on
projects that yield 8 digit dollar signs.

In my defense (I am thin-skinned) the original posting did not tell the
Click to expand...
whole story. If I had known that this is a hobbyist with a historical
interest, my answer would have been far more friendly.
I was very much involved in the TTL era (at Fairchild 1969 to '72),
inolved in the launching of many MSI circuits, and I wrote most of the
"Fairchild TTL Applications Handbook" in 1973
So I am not "completely clueless" as -toys insinuates.
Peter Alfke, from home.
 
Josh Rosen wrote:
The answer is that there is no combinatorial divider that makes sense.
Division is done by successive approximation. The simplest algorithm for
division is a one bit per cycle operation.
Click to expand...
I'm not sure that long hand division is "successive approximation", as
it's a clear and precise algorithm when applied by computers, and does
yield a combinatorial divider that is only slightly more complex than a
similar multiplier design derived from long hand multiplication.

The design for such a divider is identical to a similar multiplier, but
with subtraction and a mux at each stage to keep the original value if
a barrow occurs. The "solution" is in the mux selectors for the
quotient, and the ending value at the end of the subtractors is the
remainder.

This was fairly fast, and easy to implement as a bit serial/parallel
design I did a while back for a distributed arithmetic problem.

I suspect, but didn't figure it out, that there is a Booth Recoding
analog for such a divider design. You can use the top bits of the
remainer to select the shift amount, which cuts the cycles in half for
a serial design, so I didn't worry it that hard.
 
I suspect, but didn't figure it out, that there is a Booth Recoding
analog for such a divider design. You can use the top bits of the
remainer to select the shift amount, which cuts the cycles in half for
a serial design, so I didn't worry it that hard.
Click to expand...
This is the two bit at a time algorithm that I was talking about. Back in
the 70s this was the most cost effective way to implement division. Modern
machines, and FPGAs, have fast multipliers so convergence division is the
best choice today.
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top